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1. 发明公开

EP1521997A2 PLASMA POLYMERIZED ELECTRON BEAM RESIST 审中-公开
标题翻译： Nachbehandlung eines belichteten Plasma-polymerisierten Resistsfürdie Elektronenstrahllitgraph
公开(公告)号：EP1521997A2
公开(公告)日：2005-04-13
申请号：EP03707949.8
申请日：2003-03-10
申请人： Quantiscript Inc.
发明人： AWAD, Yousef , LAVALLEE, Eric , BEAUVAIS, Jacques , DROUIN, Dominique
IPC分类号： G03F7/004 , G03F7/38
CPC分类号： G03F1/78 , G03F7/0046 , G03F7/038 , G03F7/38 , H01L21/0277 , H01L21/31138 , Y10S438/948 , Y10S438/95
摘要： A process for producing a pattern of negative electron beam resist comprises: depositing a layer of plasma polymerized fluoropolymer on a face of a substrate, the plasma polymerized fluoropolymer forming the negative electron beam resist; producing an electron beam; moving the electron beam on the layer of plasma polymerized fluoropolymer to define the pattern, the layer then having exposed fluoropolymer areas defining the pattern and unexposed fluoropolymer areas; and removing the unexposed fluoropolymer areas to leave only the pattern on the face of the subtrate. According to an alternative, the process comprises: depositing the layer of negative electron beam resist on a face of a substrate; producing an electron beam; moving the electron beam on the layer of negative electron beam resist to define the pattern, the layer then having exposed resist areas defining the pattern and unexposed resist areas; treating the patterned layer with a base solution to decrease a dry etch resistance of the unexposed resist areas; and dry etching the unexposed resist areas to leave only the pattern on the face of the substrate.
摘要翻译：用于制造负电子束抗蚀剂图案的方法包括：在基板的表面上沉积等离子体聚合的氟聚合物层，等离子体聚合的含氟聚合物形成负电子束抗蚀剂; 产生电子束; 将等离子体聚合的氟聚合物层上的电子束移动以限定图案，然后该层具有限定图案和未曝光的含氟聚合物区域的暴露的含氟聚合物区域; 并除去未曝光的含氟聚合物区域，仅留下基材表面上的图案。根据替代方案，该方法包括：将负电子束抗蚀剂层沉积在衬底的表面上; 产生电子束; 将电子束移动到负电子束抗蚀剂层上以限定图案，然后该层具有限定图案和未曝光的抗蚀剂区域的曝光的抗蚀剂区域; 用碱溶液处理图案化层以降低未曝光的抗蚀剂区域的耐干蚀刻电阻; 并干燥地蚀刻未曝光的抗蚀剂区域，仅留下基板表面上的图案。

2. 发明授权

EP0420489B1 Compensation of lithographic and etch proximity effects 有权转让
标题翻译：光刻和Ätznäheeffekten补偿
公开(公告)号：EP0420489B1
公开(公告)日：1997-12-29
申请号：EP90310242
申请日：1990-09-19
申请人： AT & T CORP
发明人： EISENBERG JULI HONG , FRITZINGER LARRY BRUCE , FU CHONG-CHENG , KOOK TAEHO , WOLF THOMAS MICHAEL
IPC分类号： G03F1/08 , G03F7/20 , H01L21/027 , H01L21/30 , H01L21/302 , H01L21/3065
CPC分类号： G03F7/20 , Y10S438/941 , Y10S438/948

3. 发明公开

EP0666592A3 Method for forming a dielectric layer on a high temperature metal layer 失效
标题翻译：一种用于在高熔点金属层上产生电介质层的过程。
公开(公告)号：EP0666592A3
公开(公告)日：1997-07-09
申请号：EP95101036.2
申请日：1995-01-26
申请人： MOTOROLA, INC.
发明人： Sellers, James A.
IPC分类号： H01L21/768
CPC分类号： H01L21/76895 , H01L21/768 , H01L23/5329 , H01L2924/0002 , Y10S438/948 , Y10S438/974 , H01L2924/00
摘要： A method for forming a dielectric layer (16) on a high temperature metal layer (14) is provided. By processing the high temperature metal layer (14) with a non-oxidizing photoresist stripper and absent a photoresist hardening step, adhesion between the high temperature metal layer (14) and a dielectric layer (16) subsequently formed on the high temperature metal layer (14) is significantly improved. The dielectric layer (16) will adhere to the high temperature metal layer (14) in high temperature environments. The method is suitable for forming multi-layer metallization and buried layer structures for semiconductor integrated circuits.

4. 发明公开

EP0718877A2 Method of manufacturing a MESFET 失效
标题翻译：一种用于MESFET的制造工艺
公开(公告)号：EP0718877A2
公开(公告)日：1996-06-26
申请号：EP95120152.4
申请日：1995-12-20
申请人： MURATA MANUFACTURING CO., LTD.
发明人： Yoshida, Kazuhiro
IPC分类号： H01L21/338 , H01L21/285
CPC分类号： H01L29/66863 , H01L21/0272 , H01L21/28587 , Y10S148/10 , Y10S438/948
摘要： A semiconductor device manufacturing method with which a GaAs MESFET and an integrated circuit using the same can be manufactured cheaply and with high yield by accurately forming a mushroom-shaped gate electrode with inexpensive equipment and a short process. The method includes the steps of: depositing a first mask layer 16 on a semiconductor substrate; forming an opening 16a in the first mask layer 16; causing the first mask layer 16 to flow by heat-treating the semiconductor substrate; depositing a second mask layer 17 on the first mask layer; forming in the second mask layer 17 an opening 17a larger than the opening 16a in the first mask layer 16 and exposing the opening 16a in the first mask layer 16; and forming a gate electrode 19 in the opening 17a in the second mask layer 17.

5. 发明公开

EP0683531A3 MOSFET with LDD structure and manufacturing method therefor 失效
标题翻译： MOSFET，具有LDD结构及其制造方法。
公开(公告)号：EP0683531A3
公开(公告)日：1996-02-28
申请号：EP95303269.5
申请日：1995-05-16
申请人： Samsung Electronics Co., Ltd.
发明人： Kim, Jhang-rae
IPC分类号： H01L29/78 , H01L29/08 , H01L21/336
CPC分类号： H01L29/6659 , H01L29/66659 , H01L29/7835 , H01L29/7836 , Y10S257/90 , Y10S438/948
摘要： A new high-voltage transistor and a method for manufacturing the same, in which a gate electrode (54) is formed on a semiconductor substrate (50) of a first conductivity type by interposing a gate insulation film (52). A first impurity region (51) of a first conductivity type having a first impurity concentration is formed on the surface of the lower gate electrode (54). Second and third impurity regions (56,56') of a second conductivity type having a second impurity concentration are formed on the substrate with the first impurity region included therebetween. A fourth impurity region (53) having a smaller junction depth than that of the second impurity region (56,56'), and having a third impurity concentration which is lower than that of the second impurity region is formed between the first impurity region (51) and second impurity region (56,56'). Since the intensity of the electric field applied to the drain region is reduced, transistor characteristics are improved. Also, the integration of a semiconductor device is increased by reducing the layout space.

6. 发明公开

EP0683531A2 MOSFET with LDD structure and manufacturing method therefor 失效
标题翻译： MOSFET mit LDD Struktur und Verfahren zur Herstellung。
公开(公告)号：EP0683531A2
公开(公告)日：1995-11-22
申请号：EP95303269.5
申请日：1995-05-16
申请人： Samsung Electronics Co., Ltd.
发明人： Kim, Jhang-rae
IPC分类号： H01L29/78 , H01L29/08 , H01L21/336
CPC分类号： H01L29/6659 , H01L29/66659 , H01L29/7835 , H01L29/7836 , Y10S257/90 , Y10S438/948
摘要： A new high-voltage transistor and a method for manufacturing the same, in which a gate electrode (54) is formed on a semiconductor substrate (50) of a first conductivity type by interposing a gate insulation film (52). A first impurity region (51) of a first conductivity type having a first impurity concentration is formed on the surface of the lower gate electrode (54). Second and third impurity regions (56,56') of a second conductivity type having a second impurity concentration are formed on the substrate with the first impurity region included therebetween. A fourth impurity region (53) having a smaller junction depth than that of the second impurity region (56,56'), and having a third impurity concentration which is lower than that of the second impurity region is formed between the first impurity region (51) and second impurity region (56,56'). Since the intensity of the electric field applied to the drain region is reduced, transistor characteristics are improved. Also, the integration of a semiconductor device is increased by reducing the layout space.
摘要翻译：一种新的高压晶体管及其制造方法，其中通过插入栅极绝缘膜（52）在第一导电类型的半导体衬底（50）上形成栅电极（54）。在下栅电极（54）的表面上形成具有第一杂质浓度的第一导电类型的第一杂质区（51）。具有第二杂质浓度的第二导电类型的第二和第三杂质区（56,56'）形成在衬底上，其间包括第一杂质区。具有比第二杂质区域（56,56'）小的结深的第四杂质区域（53），并且具有比第二杂质区域的第三杂质浓度低的第三杂质浓度形成在第一杂质区域 51）和第二杂质区（56,56'）。由于施加到漏极区域的电场强度降低，所以提高了晶体管特性。此外，通过减少布局空间来增加半导体器件的集成。

8. 发明公开

EP0666592A2 Method for forming a dielectric layer on a high temperature metal layer 失效
标题翻译：一种用于在高熔点金属层上产生电介质层的过程。
公开(公告)号：EP0666592A2
公开(公告)日：1995-08-09
申请号：EP95101036.2
申请日：1995-01-26
申请人： MOTOROLA, INC.
发明人： Sellers, James A.
IPC分类号： H01L21/768
CPC分类号： H01L21/76895 , H01L21/768 , H01L23/5329 , H01L2924/0002 , Y10S438/948 , Y10S438/974 , H01L2924/00
摘要： A method for forming a dielectric layer (16) on a high temperature metal layer (14) is provided. By processing the high temperature metal layer (14) with a non-oxidizing photoresist stripper and absent a photoresist hardening step, adhesion between the high temperature metal layer (14) and a dielectric layer (16) subsequently formed on the high temperature metal layer (14) is significantly improved. The dielectric layer (16) will adhere to the high temperature metal layer (14) in high temperature environments. The method is suitable for forming multi-layer metallization and buried layer structures for semiconductor integrated circuits.
摘要翻译：形成高温金属层上的介电层（16）（14），其具有良好的高温粘合性包括形成在衬底上的高温金属层（11），具有的氧化物形成，沉积暴露有利的自由能的金属和显影光致抗蚀剂以形成图案，以及蚀刻在金属图案。剩余的光致抗蚀剂被去除，使用非氧化性剥离，形成在电介质秉承层，然后在惰性气体中退火，以稳定为高温进一步处理。所以声称是如上所述的方法，其中所述金属为钛，氮化钛，V，V-N，铬，-N，Ta或钽 - N，和电介质不退火。进一步声称是如上其中金属是TiN和所述电介质在环境具有小于3000 O2退火时在的方法。

9. 发明授权

EP0370935B1 Method of forming conductive lines and studs 失效
标题翻译：制造导电迹线和支撑件的方法。
公开(公告)号：EP0370935B1
公开(公告)日：1994-12-28
申请号：EP89480158.8
申请日：1989-10-10
申请人： International Business Machines Corporation
发明人： Greco, Nancy Ann , Greco, Stephen Edward
IPC分类号： H01L21/60 , H01L21/90 , G03F7/008
CPC分类号： H01L21/76885 , H05K3/4647 , Y10S438/948

10. 发明公开

EP0628879A1 Surface-imaging technique for lithographic processes for device fabrication 失效
标题翻译：成像技术用于通过光刻工艺制造的设备获得。
公开(公告)号：EP0628879A1
公开(公告)日：1994-12-14
申请号：EP94303541.0
申请日：1994-05-18
申请人： AT&T Corp.
发明人： Taylor, Gary Newton , Wheeler, David Roger
IPC分类号： G03F7/38 , G03F7/075 , G03F7/09
CPC分类号： G03F7/094 , G03F7/0754 , G03F7/265 , Y10S430/168 , Y10S438/948
摘要： A surface-imaging technique for lithographic processes is disclosed. The lithographic processes are used to manufacture integrated circuit devices. An image is produced on a resist that is applied onto a substrate. The image is produced by exposing selected regions of the resist material to radiation. The selected exposed regions correspond to the image. The resist is then exposed to a silylating reagent that selectively reacts with either the exposed or the unexposed region of the resist. The silylated resist is then subjected to reactive ion etching, which forms an in situ silicon oxide etch mask over the silylated regions of the resist. The mask so formed provides etching selectivity which provides precise image transfer from the resist into the substrate.
摘要翻译：用于光刻工艺的表面成像技术是游离缺失盘。的光刻工艺被用于制造集成电路装置。的图像上的抗蚀剂也被施加到基片产生的。该图像由抗蚀剂材料的选定区域暴露于辐射产生的。所选择的曝光区域对应于图像。然后将抗蚀剂暴露于甲硅烷基化试剂做选择性地与任一曝光或未曝光的抗蚀剂的区域发生反应。然后甲硅烷基化的抗蚀剂进行反应性离子蚀刻，它比的区域中的原位氧化硅蚀刻掩模的甲硅烷基化形式的抗蚀剂。如此形成的掩模提供蚀刻选择性，其提供从所述抗蚀剂到基材精确的图像转印。

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