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1. 发明公开

EP3362907A1 DISTRIBUTED SELF-DIRECTED RDMA-BASED B-TREE KEY-VALUE MANAGER 审中-公开
公开(公告)号：EP3362907A1
公开(公告)日：2018-08-22
申请号：EP16785640.0
申请日：2016-10-10
申请人： Microsoft Technology Licensing, LLC
发明人： SHAMIS, Alexander , SUZUE, Yutaka
IPC分类号： G06F15/173 , G06F9/54 , G06F17/30
CPC分类号： G06F15/17331 , G06F9/544 , G06F17/30327 , H04L49/103 , H04L67/1097
摘要： A “Key-Value Manager” applies an RDMA-based memory allocator to implement a distributed and lock-free B-Tree based key-value store. In various implementations, the Key-Value Manager is implemented as a standalone library running concurrently on large numbers of networked computing devices. The RDMA-based memory allocator of the Key-Value Manager allocates and accesses the memory of the key-value store via various sequences of RDMA messages (e.g., RDMA reads, RDMA writes, and RDMA atomic compare and swap (CAS) operations). As such, CPUs of computing devices hosting the memory of the key-value store do not need to be notified of or involved in RDMA-based reads and writes to that memory. Consequently, CPU utilization for any computing device that hosts any portion of the key-value store is minimal, thereby enabling the Key-Value Manager to scale to very large numbers of concurrent accesses by very large numbers of computing devices.

2. 发明公开

EP3238395A1 APPARATUS AND METHOD FOR BUFFERING DATA IN A SWITCH 审中-公开
标题翻译：用于在开关中缓冲数据的装置和方法
公开(公告)号：EP3238395A1
公开(公告)日：2017-11-01
申请号：EP14909254.6
申请日：2014-12-24
申请人： Intel Corporation
发明人： CHENG, Albert S. , LOVETT, Thomas D. , PARKER, Michael A. , HOOVER, Steven F.
IPC分类号： H04L12/937 , H04L12/861
CPC分类号： H04L49/3036 , H04L12/6418 , H04L49/101 , H04L49/103 , H04L49/254 , H04L49/505
摘要： Apparatuses, methods and storage medium associated with buffering data in a switch are provided. In embodiments, the switch may include a plurality of queue buffers, a plurality of queues respectively associated with the plurality of queue buffers, a shared buffer, and a queue point controller coupled with the plurality of queue buffers and the shared buffer. In embodiments the queue point controller may be configured to determine an amount of available space in a selected queue buffer of the plurality of queue buffers. The queue point controller may be further configured to allocate at least a portion of the shared buffer to a selected queue that is associated with the selected queue buffer. In embodiments, this allocation may be based on the amount of available space determined in the selected queue buffer. Other embodiments may be described and/or claimed.
摘要翻译：提供了与在交换机中缓冲数据相关联的设备，方法和存储介质。在实施例中，交换机可以包括多个队列缓冲器，分别与多个队列缓冲器相关联的多个队列，共享缓冲器以及与多个队列缓冲器和共享缓冲器耦合的队列点控制器。在实施例中，队列点控制器可以被配置为确定多个队列缓冲器中的选定队列缓冲器中的可用空间量。队列点控制器可以进一步被配置为将共享缓冲区的至少一部分分配给与选择的队列缓冲区相关联的选定队列。在实施例中，该分配可以基于在所选择的队列缓冲器中确定的可用空间量。其他实施例可以被描述和/或要求保护。

3. 发明授权

EP1497961B1 PACKET SWITCHING 有权
标题翻译： IP启用交换中心
公开(公告)号：EP1497961B1
公开(公告)日：2012-12-05
申请号：EP03725335.8
申请日：2003-04-16
申请人： Cambridge Enterprise Limited , KING'S COLLEGE LONDON
发明人： HALL, Trevor James , CROSLAND, William Alden
IPC分类号： H04L12/56 , H04Q11/00
CPC分类号： H04L49/103 , H04L49/101 , H04L49/1569 , H04L49/1576 , H04L49/255 , H04L49/258 , H04L49/3018 , H04L49/50 , H04L2012/5605

4. 发明授权

EP1508225B1 METHOD FOR DATA STORAGE IN EXTERNAL AND ON-CHIP MEMORY IN A PACKET SWITCH 有权
标题翻译：与外部和片上存储器中的包交换单元数据的存储过程
公开(公告)号：EP1508225B1
公开(公告)日：2012-11-07
申请号：EP03726810.9
申请日：2003-05-08
申请人： Intel Corporation
发明人： CALDERON, Juan-Carlos , LING, Jing , CAIA, Jean-Michel , JOSHI, Vivek , HUANG, Anguo
IPC分类号： H04L12/56
CPC分类号： H04L49/103 , H04L49/109 , H04L49/254

5. 发明授权

EP1694004B1 Traffic policing with programmable registers 有权
标题翻译：与可编程寄存器流量监控
公开(公告)号：EP1694004B1
公开(公告)日：2012-10-03
申请号：EP05025592.6
申请日：2005-11-23
申请人： Broadcom Corporation
发明人： Smith, Brandon Carl , Cao, Jun
IPC分类号： H04L12/56
CPC分类号： H04L47/29 , H04L47/10 , H04L47/20 , H04L47/21 , H04L47/31 , H04L49/103 , H04L49/205 , H04L49/351

6. 发明公开

EP1839166A4 SHARED-MEMORY SWITCH FABRIC ARCHITECTURE 有权
标题翻译： SCHALTMATRIXARCHITEKTUR EINES GEMEINSAMEN SPEICHERS
公开(公告)号：EP1839166A4
公开(公告)日：2009-03-04
申请号：EP06717512
申请日：2006-01-05
申请人： FULCRUM MICROSYSTEMS INC
发明人： CUMMINGS URI , LINES ANDREW , PELLETIER PATRICK , SOUTHWORTH ROBERT
IPC分类号： G06F13/28 , G06F13/00
CPC分类号： G11C7/1048 , G11C7/1075 , H04L49/101 , H04L49/103 , H04L49/351
摘要： A shared memory is described having a plurality of receive ports and a plurality of transmit ports characterized by a first data rate. A memory includes a plurality of memory banks organized in rows and columns. Operation of the memory array is characterized by a second data rate. Non-blocking receive crossbar circuitry is operable to connect any of the receive ports with any of the memory banks. Non-blocking transmit crossbar circuitry is operable to connect any of the memory banks with any of the transmit ports. Buffering is operable to decouple operation of the receive and transmit ports at the first data rate from operation of the memory array at the second data rate. Scheduling circuitry is operable to control interaction of the ports, crossbar circuitry, and memory array to effect storage and retrieval of the data segments in the shared memory. The scheduling circuitry is further operable to facilitate striping of each data segment of a frame across the memory banks in one of the rows, and to facilitate striping of successive data segments of the frame across successive rows in the array.
摘要翻译：描述了具有以第一数据速率为特征的多个接收端口和多个发送端口的共享存储器。存储器包括按行和列组织的多个存储体。存储器阵列的操作以第二数据速率为特征。非阻塞接收交叉开关电路可操作以将任何接收端口与任何存储体连接。非阻塞发送交叉开关电路可操作以将任何存储体与任何发送端口连接。缓冲可操作以使第一数据速率下的接收和发送端口的操作与第二数据速率下的存储器阵列的操作解耦。调度电路可操作以控制端口，交叉开关电路和存储器阵列的交互，以实现共享存储器中的数据段的存储和检索。调度电路进一步可操作用于促进跨越一个行中的存储体的一个帧的每个数据段的条带化，并且促进该帧的连续数据段在该阵列中的连续行上的条带化。

7. 发明公开

EP1863234A1 System and method for managing forwarding database resources in a switching environment 审中-公开
标题翻译：系统和方法在交换环境管理重定向数据库资源
公开(公告)号：EP1863234A1
公开(公告)日：2007-12-05
申请号：EP07010676.0
申请日：2007-05-30
申请人： FUJITSU LIMITED
发明人： Miyoshi, Takashi , Nakagawa, Yukihiro , Shimizu, Takeshi
IPC分类号： H04L12/56 , H04L12/46
CPC分类号： H04L45/00 , H04L45/54 , H04L49/103 , H04L49/25 , H04L49/3009 , H04L49/351 , H04L49/354 , H04L49/356 , H04L67/1097
摘要： In particular embodiments of the present invention, a method for switching is provided. In particular embodiments, the method includes receiving a packet at an input port of a switch, the packet associated with a virtual local area network identifier (VLAN ID) and a Media Access Control (MAC) address, the switch comprising a forwarding database and a plurality of output ports. The method also includes masking the VLAN ID to create a masked VLAN ID comprising fewer bits than the VLAN ID associated with the packet. The method further includes applying a function to the MAC address and the masked VLAN ID to generate an index, and, at the forwarding database, using the index to identify an output port of the switch. The method also includes transmitting the packet from the identified output port.
摘要翻译：在本发明的具体实施方案中，提供了一种用于切换的方法。在特定实施例中，该方法包括以一个开关，与虚拟局域网标识符（VLAN ID）和介质访问控制（MAC）地址，交换机包括转发数据库和相关联的分组的输入端口接收的数据包输出端口的多个。因此，该方法包括掩蔽所述VLAN ID来创建掩蔽VLAN ID包括比与所述分组相关联的VLAN ID更少的比特。该方法包括：应用一个函数进一步的MAC地址和所述掩蔽VLAN ID以产生索引，并且，在所述转发数据库中，使用所述索引来识别在所述开关的输出端口。因此，该方法包括发送从所识别的输出端口该分组。

8. 发明授权

EP0947078B1 HIGH SPEED SWITCHING DEVICE 失效
标题翻译：快速开关装置
公开(公告)号：EP0947078B1
公开(公告)日：2007-02-14
申请号：EP97950980.9
申请日：1997-12-16
申请人： Juniper Networks
发明人： SINDHU, Pradeep, S. , ANAND, Ramalingam, K. , FERGUSON, Dennis, C. , LIENCRES, Bjorn, O.
IPC分类号： H04L12/56
CPC分类号： G06F15/167 , H04L12/5601 , H04L29/06 , H04L45/00 , H04L45/72 , H04L45/7457 , H04L47/6225 , H04L49/103 , H04L49/108 , H04L49/1538 , H04L49/203 , H04L49/25 , H04L49/252 , H04L49/3072 , H04L49/3081 , H04L49/608 , H04L49/90 , H04L49/901 , H04L49/9042 , H04L49/9047 , H04L49/9057 , H04L69/22 , H04L2012/5652 , H04L2012/5679 , H04L2012/5681 , H04Q11/0478
摘要： A router (20) for switching a data packet between a source (10) and destination (30) in a network including a plurality of input ports each including a data handler. The data handler divides a data packet into one or more fixed length cells. The router (20) includes a plurality of output ports at least one of which is for routing the data packet to the destination (30) and a memory divided into a plurality of memory banks. An input switch receives fixed length cells from the input ports and writes a single output switch routes cells received from the memory to an appropriate output port.

9. 发明授权

EP1261173B1 System on a chip for packet processing 有权
标题翻译：用于分组处理的单芯片系统
公开(公告)号：EP1261173B1
公开(公告)日：2007-01-03
申请号：EP02253533.0
申请日：2002-05-20
申请人： Broadcom Corporation
发明人： Hayter, Mark D., , Desai, Shailendra S. , Dobberpuhl, Daniel W. , Chui, Kwong-Tak A.
IPC分类号： H04L12/44 , H04L29/06
CPC分类号： H04L47/30 , G06F13/128 , H04L45/00 , H04L45/60 , H04L47/29 , H04L49/103 , H04L49/254 , H04L49/3018 , H04L49/3027 , H04L49/351 , H04L49/90 , H04L49/901 , H04L49/9042

10. 发明公开

EP1709772A1 A METHOD AND ARRANGEMENT FOR AN IMPROVED BUFFER SOLUTION WITHIN A COMMUNICATION NETWORK SWITCH 有权
标题翻译：方法和用于改良缓冲来在通信网络交换机
公开(公告)号：EP1709772A1
公开(公告)日：2006-10-11
申请号：EP05704639.3
申请日：2005-01-20
申请人： Telenor ASA
发明人： BJORNSTAD, Steinar
IPC分类号： H04L12/56 , H04Q11/00
CPC分类号： H04Q11/0005 , H04L49/103 , H04L49/254 , H04Q2011/002
摘要： In asynchronous optical packet switches, scheduling packets from a buffer randomly will cause less efficient utilisation of the buffer. Additionally, reordering of packets may cause problems for service quality demanding applications. According to the present invention a new electronic buffer scheduling algorithm is proposed and a switch utilizing this algorithm is disclosed. The algorithm is designed for utilizing the buffer resources efficiently, still avoiding serious packet reordering.

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