专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

EP1261173B1 System on a chip for packet processing 有权
标题翻译：用于分组处理的单芯片系统
公开(公告)号：EP1261173B1
公开(公告)日：2007-01-03
申请号：EP02253533.0
申请日：2002-05-20
申请人： Broadcom Corporation
发明人： Hayter, Mark D., , Desai, Shailendra S. , Dobberpuhl, Daniel W. , Chui, Kwong-Tak A.
IPC分类号： H04L12/44 , H04L29/06
CPC分类号： H04L47/30 , G06F13/128 , H04L45/00 , H04L45/60 , H04L47/29 , H04L49/103 , H04L49/254 , H04L49/3018 , H04L49/3027 , H04L49/351 , H04L49/90 , H04L49/901 , H04L49/9042

2. 发明公开

EP1357478A3 Tracking non-posted writes in a system 审中-公开
标题翻译：在系统瞬时写作的迫害
公开(公告)号：EP1357478A3
公开(公告)日：2006-09-06
申请号：EP03009171.4
申请日：2003-04-22
申请人： Broadcom Corporation
发明人： Chui, Kwong-Tak A. , Go, Shun Wai , Hayter, Mark D. , Ning, Chun H. , Silveria, Amy K.
IPC分类号： G06F13/42
CPC分类号： G06F13/4217
摘要： An apparatus includes a storage location and a write monitor circuit coupled to the storage location. The storage location is configured to store a write response indicator which is capable of indicating a reception of at least one write response. Each write response indicates that a corresponding write has reached a target device of that write. The write monitor circuit is configured to update the write response indicator in response to receiving an indication of a first write response. A computer accessible medium may comprises instructions which, when executed: (i) initialize the write response indicator; and (ii) issue one or more writes to a target device, wherein the target device is configured to response to each of the writes with a write response to be indicated by the write response indicator.

3. 发明公开

EP1261173A2 System on a chip for packet processing 有权
标题翻译： Ein-Chip System zur Paketverarbeitung
公开(公告)号：EP1261173A2
公开(公告)日：2002-11-27
申请号：EP02253533.0
申请日：2002-05-20
申请人： Broadcom Corporation
发明人： Hayter, Mark D., , Desai, Shailendra S. , Dobberpuhl, Daniel W. , Chui, Kwong-Tak A.
IPC分类号： H04L12/44 , H04L29/06
CPC分类号： H04L47/30 , G06F13/128 , H04L45/00 , H04L45/60 , H04L47/29 , H04L49/103 , H04L49/254 , H04L49/3018 , H04L49/3027 , H04L49/351 , H04L49/90 , H04L49/901 , H04L49/9042
摘要： A packet processing system may include a processor, a cache, a memory controller, and at least one packet interface circuit integrated into a single integrated circuit. In one embodiment (which may be used in integrated or non-integrated systems), the packet interface circuit is configured to cause allocation in the cache of a portion of a received packet. In one embodiment (which may be used in integrated or non-integrated systems), the memory controller may be configured to selectively block memory transactions. Particularly, the memory controller may implement at least two block signals, one for the packet interface circuit and one for other devices. The block signals may be used to control the initiation of memory transactions when the memory controller's input queue is approaching fullness.
摘要翻译：分组处理系统可以包括处理器，高速缓存，存储器控制器和集成到单个集成电路中的至少一个分组接口电路。在一个实施例中（其可以在集成或非集成系统中使用），分组接口电路被配置为在接收到的分组的一部分的高速缓存中引起分配。在一个实施例中（其可以在集成或非集成系统中使用），存储器控制器可以被配置为选择性地阻止存储器事务。特别地，存储器控制器可以实现至少两个块信号，一个用于分组接口电路，一个用于其他设备。当存储器控制器的输入队列接近饱和时，块信号可用于控制存储器事务的启动。

4. 发明公开

EP1261173A3 System on a chip for packet processing 有权
标题翻译：用于分组处理的单芯片系统
公开(公告)号：EP1261173A3
公开(公告)日：2005-01-05
申请号：EP02253533.0
申请日：2002-05-20
申请人： Broadcom Corporation
发明人： Hayter, Mark D., , Desai, Shailendra S. , Dobberpuhl, Daniel W. , Chui, Kwong-Tak A.
IPC分类号： H04L12/44 , H04L29/06
CPC分类号： H04L47/30 , G06F13/128 , H04L45/00 , H04L45/60 , H04L47/29 , H04L49/103 , H04L49/254 , H04L49/3018 , H04L49/3027 , H04L49/351 , H04L49/90 , H04L49/901 , H04L49/9042
摘要： A packet processing system may include a processor, a cache, a memory controller, and at least one packet interface circuit integrated into a single integrated circuit. In one embodiment (which may be used in integrated or non-integrated systems), the packet interface circuit is configured to cause allocation in the cache of a portion of a received packet. In one embodiment (which may be used in integrated or non-integrated systems), the memory controller may be configured to selectively block memory transactions. Particularly, the memory controller may implement at least two block signals, one for the packet interface circuit and one for other devices. The block signals may be used to control the initiation of memory transactions when the memory controller's input queue is approaching fullness.

5. 发明公开

EP1357478A2 Tracking non-posted writes in a system 审中-公开
标题翻译：在einem系统中的Verfolgung vonunverzögertenSchreiben
公开(公告)号：EP1357478A2
公开(公告)日：2003-10-29
申请号：EP03009171.4
申请日：2003-04-22
申请人： Broadcom Corporation
发明人： Chui, Kwong-Tak A. , Go, Shun Wai , Hayter, Mark D. , Ning, Chun H. , Silveria, Amy K.
IPC分类号： G06F13/42 , G06F13/10
CPC分类号： G06F13/4217
摘要： An apparatus includes a storage location and a write monitor circuit coupled to the storage location. The storage location is configured to store a write response indicator which is capable of indicating a reception of at least one write response. Each write response indicates that a corresponding write has reached a target device of that write. The write monitor circuit is configured to update the write response indicator in response to receiving an indication of a first write response. A computer accessible medium may comprises instructions which, when executed: (i) initialize the write response indicator; and (ii) issue one or more writes to a target device, wherein the target device is configured to response to each of the writes with a write response to be indicated by the write response indicator.
摘要翻译：一种装置包括存储位置和耦合到存储位置的写监视器电路。存储位置被配置为存储能够指示至少一个写入响应的接收的写入响应指示符。每个写入响应指示相应的写入已到达该写入的目标设备。写监视器电路被配置为响应于接收到第一写响应的指示而更新写响应指示符。计算机可访问介质可以包括指令，当被执行时：（i）初始化写入响应指示符; 以及（ii）向目标设备发出一个或多个写入，其中所述目标设备被配置为响应于由所述写入响应指示符指示的写入响应。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式