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1. 发明公开

EP3195318A1 PSEUDO DUAL PORT MEMORY 有权
标题翻译： PSEUDO双端口存储器
公开(公告)号：EP3195318A1
公开(公告)日：2017-07-26
申请号：EP15748352.0
申请日：2015-07-20
申请人： Qualcomm Incorporated
发明人： YOON, Sei Seung , KWOK, Tony Chung Yiu , JUNG, Changho , DESAI, Nishith Nitin
IPC分类号： G11C7/10 , G11C8/16
CPC分类号： G11C11/419 , G11C7/106 , G11C7/1072 , G11C7/1075 , G11C7/1087 , G11C7/22 , G11C7/222 , G11C8/16 , G11C11/412
摘要： A memory and a method for operating the memory provided. In one aspect, the memory may be a PDP memory. The memory includes a control circuit configured to generate a first clock and a second clock in response an edge of a clock for an access cycle. A first input circuit is configured to receive an input for a first memory access based on the first clock. The first input circuit includes a latch. The second input circuit configured to receive an input for a second memory access based on the second clock. The second input circuit includes a flip-flop.
摘要翻译：存储器和操作提供的存储器的方法。在一个方面，存储器可以是PDP存储器。存储器包括控制电路，该控制电路被配置为响应访问周期的时钟的边沿来产生第一时钟和第二时钟。第一输入电路被配置为基于第一时钟接收用于第一存储器访问的输入。第一输入电路包括一个锁存器。第二输入电路被配置为基于第二时钟接收用于第二存储器访问的输入。第二输入电路包括触发器。

2. 发明公开

EP3158458A1 TIME-CONSTRAINED DATA COPYING BETWEEN STORAGE MEDIA 审中-公开
标题翻译：存储介质之间的时间约束数据复制
公开(公告)号：EP3158458A1
公开(公告)日：2017-04-26
申请号：EP15732084.7
申请日：2015-05-28
申请人： Qualcomm Incorporated
发明人： AMARILIO, Lior , KHAZIN, Alexander
IPC分类号： G06F13/38 , G06F13/42
CPC分类号： G11C7/1075 , G06F13/287 , G06F13/364 , G06F13/385 , G06F13/4022 , G06F13/4282 , G06F13/4295 , G11C7/1036
摘要： Time-constrained data copying between storage media is disclosed. When an electronic device is engaged in real-time operations, multiple data blocks may need to be copied from one storage medium to another storage medium within certain time constraints. In this regard, a data port is operatively controlled by a plurality of registers of a first register bank. The plurality of registers is copied from the first register bank to a second register bank within a temporal limit and while the data port remains under control of the plurality of registers being copied. By copying the plurality of registers within the temporal limit, it is possible to prevent operational interruption in the data port and reduce bandwidth overhead associated with the register copying operation.
摘要翻译：公开了存储介质之间时间受限的数据复制。当电子设备进行实时操作时，可能需要在一定的时间限制内将多个数据块从一个存储介质复制到另一个存储介质。就这一点而言，数据端口由第一寄存器组的多个寄存器可操作地控制。多个寄存器在时间限制内从第一寄存器组复制到第二寄存器组，并且数据端口保持在被复制的多个寄存器的控制下。通过在时间限制内复制多个寄存器，可以防止数据端口中的操作中断并减少与寄存器复制操作相关的带宽开销。

3. 发明公开

EP3080813A2 SYSTÈME DE GESTION DE L'USURE D'UNE MÉMOIRE ÉLECTRONIQUE 有权
标题翻译： WEAR电子存储管理系统
公开(公告)号：EP3080813A2
公开(公告)日：2016-10-19
申请号：EP14814820.8
申请日：2014-12-12
申请人： Commissariat à l'Energie Atomique et aux Energies Alternatives
发明人： HARRAND, Michel , VIANELLO, Elisa
IPC分类号： G11C7/10 , G11C13/00 , G11C16/34 , G06F12/02
CPC分类号： G06F3/0616 , G06F3/0623 , G06F3/0629 , G06F3/0679 , G06F12/0246 , G06F12/1408 , G06F2212/402 , G06F2212/7211 , G11C7/1075 , G11C13/0002 , G11C13/0035 , G11C13/0061 , G11C16/3495
摘要： The invention relates to a system (600) comprising: a first memory (601) comprising several portions (S
i,j ) each of several pages, this memory comprising first (PT1) and second (PT2) ports that enable simultaneous access to two pages of distinct portions of the memory; and a control circuit (603) suitable for implementing, via the second port (PT2), a method for balancing the wear of the memory (601), comprising movements of data within the memory, while authorising simultaneous user access to the memory contents via the first port (PT1).

4. 发明公开

EP3038109A1 PSEUDO DUAL PORT MEMORY USING A DUAL PORT CELL AND A SINGLE PORT CELL WITH ASSOCIATED VALID DATA BITS AND RELATED METHODS 有权
标题翻译：具有双重PORT-CELL伪双端口存储器，并与相关有效数据位和相关程序的单一端口-CELL
公开(公告)号：EP3038109A1
公开(公告)日：2016-06-29
申请号：EP15187696.8
申请日：2015-09-30
申请人： STMicroelectronics International N.V.
发明人： Rawat, Harsh , JAIN, PIYUSH
IPC分类号： G11C8/16 , G11C7/10 , G11C11/419 , G11C11/418
CPC分类号： G11C11/419 , G11C7/1045 , G11C7/1075 , G11C8/16 , G11C11/418
摘要： A pseudo dual port memory includes a set of dual port memory cells having a read port and a write port, and configured to store data words in each of a plurality of addressed locations, and a set of single port memory cells having a read/write port, and configured to store data words in each of a plurality of addressed locations. A valid data storage unit is configured to store valid bits corresponding to the addressed locations of the set of dual port memory cells and the set of single port memory cells. Control circuitry is configured to access the addressed locations of the set of dual port memory cells and the set of single port memory cells. The control circuitry performs a simultaneous write operation using the write port of the set of dual port memory cells and the read/write port of the set of single port memory cells, and updates corresponding valid bits in the valid data storage unit, and performs a parallel read operation, at a same addressed location of the set of dual port memory cells and the set of single port memory cells, using the read port of the set of dual port memory cells and the read/write port of the set of single port memory cells, and determining which stored data word is valid based upon the corresponding valid bits in the valid data storage unit.
摘要翻译：伪双端口存储器包括一组具有一个读端口和一个写端口的双端口存储器单元，并且在每个寻址位置的多个被配置为存储数据字，并具有读一组单端口存储器单元的/写端口，和被配置为存储在每个寻址位置的多个数据字。一个有效的数据存储单元被配置为存储有效位对应给组双端口存储器单元和所述一组单端口存储器单元的位置。控制电路被配置成访问所述组双端口存储器单元和所述一组单端口存储器单元的被寻址的位置。所述控制电路使用所述一组双端口存储器单元和所述一组单端口存储器单元的读/写端口的写端口执行同时写入操作，而在有效数据存储单元对应的有效比特的更新，并执行并行读出手术，在所述一组双端口存储器单元和所述一组单端口存储器单元中的一个相同的寻址位置，使用所设置的双端口存储器单元的读取端口和该组单个端口的读/写端口存储单元，和确定性采矿哪个存储的数据字是有效的基于所述的有效数据存储单元中的对应的有效比特。

5. 发明授权

EP2757483B1 APPARATUS AND METHOD FOR EXTENDING MEMORY IN TERMINAL 有权
标题翻译：装置和方法用于扩展程序在终端
公开(公告)号：EP2757483B1
公开(公告)日：2016-03-16
申请号：EP14151614.6
申请日：2014-01-17
申请人： Samsung Electronics Co., Ltd
发明人： Yun, Sung-Hwan , Kim, Sei-Jin
IPC分类号： G06F13/38
CPC分类号： G11C7/1075 , G06F12/0246 , G06F13/382 , G06F13/385

6. 发明授权

EP2880542B1 TECHNIQUE FOR CONTROLLING MEMORY ACCESSES 有权
标题翻译： VERFAHREN ZUR STEUERUNG VON SPEICHERZUGRIFFEN
公开(公告)号：EP2880542B1
公开(公告)日：2015-12-09
申请号：EP12747975.6
申请日：2012-08-06
申请人： Telefonaktiebolaget LM Ericsson (PUBL)
发明人： VOELKL, Juergen , WOLFF, Winfried
IPC分类号： G06F13/16
CPC分类号： G06F12/023 , G06F13/1663 , G06F2212/1044 , G11C7/1075

7. 发明公开

EP2788985A4 INDEPENDENT WRITE AND READ CONTROL IN SERIALLY-CONNECTED DEVICES 审中-公开
标题翻译：独立写作读控制串行连接的设备
公开(公告)号：EP2788985A4
公开(公告)日：2015-12-09
申请号：EP12855470
申请日：2012-12-06
申请人： NOVACHIPS CANADA INC
发明人： PYEON HONG BEOM
IPC分类号： G11C7/10 , G11C16/06
CPC分类号： G11C7/1003 , G06F13/1668 , G11C7/1075

8. 发明授权

EP2186093B1 MÉMOIRE PARTAGÉE 有权
标题翻译：共享存储
公开(公告)号：EP2186093B1
公开(公告)日：2015-12-02
申请号：EP08787215.6
申请日：2008-08-14
申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives
发明人： HARRAND, Michel
IPC分类号： G11C5/06 , G11C5/02 , G11C7/10 , G11C8/12
CPC分类号： G11C7/1075 , G11C5/02 , G11C7/1012 , G11C7/1048 , G11C2207/108

9. 发明授权

EP2016497B1 MEMORY MODULE WITH REDUCED ACCESS GRANULARITY 有权
标题翻译：具有降低访问粒度内存模块
公开(公告)号：EP2016497B1
公开(公告)日：2014-07-16
申请号：EP07782931.5
申请日：2007-04-30
申请人： Rambus Inc.
发明人： HAMPEL, Craig E. , WARE, Frederick A.
IPC分类号： G06F13/16 , G11C7/10
CPC分类号： G06F13/1642 , G06F12/1081 , G06F13/1663 , G06F13/1678 , G06F13/1684 , G06F13/28 , G06F13/4243 , G06F2212/656 , G11C5/04 , G11C7/1012 , G11C7/1045 , G11C7/1075 , H05K1/181 , H05K2201/09227 , H05K2201/10159 , Y02D10/14 , Y02D10/151 , Y02P70/611
摘要： A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.

10. 发明公开

EP2502233A2 MEMORY DEVICE AND METHOD THEREOF 审中-公开
标题翻译：存储装置及方法
公开(公告)号：EP2502233A2
公开(公告)日：2012-09-26
申请号：EP10831941.9
申请日：2010-09-23
申请人： Freescale Semiconductor, Inc.
发明人： GUPTA, Ravi , BEARDEN, David R. , RAMARAJU, Ravindraraj
IPC分类号： G11C7/10 , G11C7/12 , G11C8/08
CPC分类号： G11C7/1006 , G11C7/1075 , G11C7/18 , G11C19/00 , G11C19/28
摘要： An array (10) of memory bit cells (20) are operable to provide a memory device (930) having data shifting capability, so that data can be flexibly stored and retrieved from the memory device in both parallel and serial fashions. The memory array (940) can thus be used for conventional memory storage operations, and also for operations, such as matrix operations, that provide for the alteration of the arrangement of stored data elements.

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