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1. 发明公开

EP3238395A1 APPARATUS AND METHOD FOR BUFFERING DATA IN A SWITCH 审中-公开
标题翻译：用于在开关中缓冲数据的装置和方法
公开(公告)号：EP3238395A1
公开(公告)日：2017-11-01
申请号：EP14909254.6
申请日：2014-12-24
申请人： Intel Corporation
发明人： CHENG, Albert S. , LOVETT, Thomas D. , PARKER, Michael A. , HOOVER, Steven F.
IPC分类号： H04L12/937 , H04L12/861
CPC分类号： H04L49/3036 , H04L12/6418 , H04L49/101 , H04L49/103 , H04L49/254 , H04L49/505
摘要： Apparatuses, methods and storage medium associated with buffering data in a switch are provided. In embodiments, the switch may include a plurality of queue buffers, a plurality of queues respectively associated with the plurality of queue buffers, a shared buffer, and a queue point controller coupled with the plurality of queue buffers and the shared buffer. In embodiments the queue point controller may be configured to determine an amount of available space in a selected queue buffer of the plurality of queue buffers. The queue point controller may be further configured to allocate at least a portion of the shared buffer to a selected queue that is associated with the selected queue buffer. In embodiments, this allocation may be based on the amount of available space determined in the selected queue buffer. Other embodiments may be described and/or claimed.
摘要翻译：提供了与在交换机中缓冲数据相关联的设备，方法和存储介质。在实施例中，交换机可以包括多个队列缓冲器，分别与多个队列缓冲器相关联的多个队列，共享缓冲器以及与多个队列缓冲器和共享缓冲器耦合的队列点控制器。在实施例中，队列点控制器可以被配置为确定多个队列缓冲器中的选定队列缓冲器中的可用空间量。队列点控制器可以进一步被配置为将共享缓冲区的至少一部分分配给与选择的队列缓冲区相关联的选定队列。在实施例中，该分配可以基于在所选择的队列缓冲器中确定的可用空间量。其他实施例可以被描述和/或要求保护。

2. 发明授权

EP1573950B1 APPARATUS AND METHOD TO SWITCH PACKETS USING A SWITCH FABRIC WITH MEMORY 有权
标题翻译：使用具有存储器的开关织物来切换数据包的装置和方法
公开(公告)号：EP1573950B1
公开(公告)日：2017-10-18
申请号：EP03762043.2
申请日：2003-06-27
申请人： Coriant Operations, Inc.
发明人： MAGILL, Robert, B. , LABERTEAUX, Kenneth, P.
IPC分类号： H04L12/931 , H04L12/933 , H04L12/935 , H04L12/937
CPC分类号： H04L49/3018 , H04L49/10 , H04L49/254 , H04L49/30 , H04L49/3027 , H04L49/3036 , H04L49/3045 , H04L49/3072 , H04L49/503

3. 发明授权

EP2541844B1 COMMUNICATION SYSTEM, COMMUNICATION METHOD, SERVER DEVICE, COMMUNICATION DEVICE 有权
标题翻译：通信系统，通信方法，服务器设备和通信设备
公开(公告)号：EP2541844B1
公开(公告)日：2015-05-06
申请号：EP11744798.7
申请日：2011-02-21
申请人： NEC Corporation
发明人： TORIGOE Keisuke , HIDAKA Youichi
IPC分类号： H04L12/44 , H04L29/08
CPC分类号： H04L49/3036 , H04L41/12 , H04L43/0811 , H04L49/15 , H04L49/55 , H04L69/40
摘要： A communication equipment notifies a server equipment of a communication port to which a communication cable is connected. If another communication port as a connection partner of the notified communication port is not yet connected to the communication cable, the server equipment transmits a first notification instruction to another communication equipment having the said another communication port. The said another communication equipment indicates, in a viewable manner, a communication port corresponding to the first notification instruction as a communication port to which the communication cable is required to be connected.

4. 发明授权

EP1162794B1 Gigabit switch with fast filtering processor 有权
标题翻译：具有快速滤波处理器千兆切换单元
公开(公告)号：EP1162794B1
公开(公告)日：2014-02-26
申请号：EP01305062.0
申请日：2001-06-11
申请人： Broadcom Corporation
发明人： Kalkunte, Mohan,c/o Broadcom Corporation , Ambe, Shekhar,c/o Broadcom Corporation , Kadambi,Shiri,c/o Broadcom Corporation
IPC分类号： H04L12/70
CPC分类号： H04L47/2458 , H04L12/462 , H04L45/00 , H04L45/16 , H04L45/245 , H04L45/52 , H04L45/742 , H04L47/10 , H04L47/266 , H04L47/29 , H04L47/32 , H04L49/102 , H04L49/109 , H04L49/15 , H04L49/3009 , H04L49/3018 , H04L49/3036 , H04L49/351 , H04L49/352 , H04L49/354 , H04L49/506 , H04L49/508 , H04L49/602 , H04L69/22 , Y02D50/30
摘要： A data switch for network communications includes a first data port interface which supports at least one data port which transmits and receives data. A second data port interface is also provided supporting at least one data port transmitting and receiving data. A CPU interface is provided, with the CPU interface configured to communicate with a CPU. A common memory is provided, and communicates with the first data port interface and the second data port interface. A memory management unit is provided, and communicates data from the first data port interface and the second data port interface and an common memory. At least two sets of communication channels are provided, with each of the communication channels communicating data and messaging information between the first data port interface, the second data port interface, and the memory management unit. One of the first data port interface and the second data port interface is configured to determine forwarding information from a flexible length header for an incoming data packet received at a port of the one data port interface, and is configured to determine the forwarding information by shifting the information field positions read from the flexible length header.

5. 发明授权

EP1777889B1 Method of processing information packets and telecommunication apparatus using the same 有权
标题翻译：处理信息和通信装置的分组中使用其的方法
公开(公告)号：EP1777889B1
公开(公告)日：2009-04-15
申请号：EP05292201.0
申请日：2005-10-19
申请人： Alcatel Lucent
发明人： Modena, Marco , Costantini, Carlo , Bobbo, Gianluca
IPC分类号： H04L12/56
CPC分类号： H04L49/3009 , H04L49/25 , H04L49/3036

6. 发明公开

EP1162796A3 Cascading of gigabit switches 有权
标题翻译：级联千兆交换单位
公开(公告)号：EP1162796A3
公开(公告)日：2009-03-18
申请号：EP01305065.3
申请日：2001-06-11
申请人： Broadcom Corporation
发明人： Kalkunte, Mohan.c/o Broadcom Corporation , Ambe, Shekhar.c/o Broadcom Corporation , Kadambi, Shiri.c/o Broadcom Corporation
IPC分类号： H04L12/56 , H04L12/46 , H04L12/44
CPC分类号： H04L47/2458 , H04L12/462 , H04L45/00 , H04L45/16 , H04L45/245 , H04L45/52 , H04L45/742 , H04L47/10 , H04L47/266 , H04L47/29 , H04L47/32 , H04L49/102 , H04L49/109 , H04L49/15 , H04L49/3009 , H04L49/3018 , H04L49/3036 , H04L49/351 , H04L49/352 , H04L49/354 , H04L49/506 , H04L49/508 , H04L49/602 , H04L69/22 , Y02D50/30
摘要： A method of handling data packets in a series of network switches includes receiving an incoming data packet at a data port of a first switch of the series of network switches. A module id bitmap of the incoming data packet is resolved and a bit corresponding to the first switch of the module id bitmap is examined to determine if the bit is set. A destination address of the incoming data packet is resolved when the corresponding bit is set and the incoming data packet is forwarded or dropped based on the destination address. When the corresponding bit is not set, the incoming data packet is forwarded to a next switch of the series of network switches. A network switch configured to allow for cascading of data packets is also disclosed.

7. 发明公开

EP1393498A4 DISTRIBUTED SHARED MEMORY PACKET SWITCH 有权
标题翻译：分组交换分布式共享存储
公开(公告)号：EP1393498A4
公开(公告)日：2006-09-06
申请号：EP02769758
申请日：2002-05-15
申请人： ALCATEL INTERNETWORKING INC
发明人： VANDENHOUDT JAN , MIMMS ALAN
IPC分类号： H04L12/56 , H04L12/02
CPC分类号： H04L49/30 , H04L47/50 , H04L47/52 , H04L47/6255 , H04L49/103 , H04L49/1523 , H04L49/254 , H04L49/3036 , H04L49/3045
摘要： A shared memory packet switch fabric (14) whose scheduling task is distributed to multiple egress schedulers (78) residing on multiple egress control units (12) and whose data storage is distributed to multiple packet buffer units (16), where the schedulers (78) and the packet buffer units (16) are interconnected via high speed links. An ingress control unit (10) receives and transmits a packet to one of a plurality of packet buffer units (PBUs) (16) making up the switch fabric (14). The receiving PBU (16) stores the packet in memory and transmits a notification message with the memory information to all interested egress control units (12). If an egress control unit (12) receiving the notification has enough queue space, it stores the memory information in its queue. The egress control unit (12) then transmits a booking message indicating that it is to request the packet in the future.

8. 发明公开

EP1183828A2 FABRIC ROUTER WITH FLIT CACHING 有权
标题翻译： FLIT CACHE在分组交换路由器
公开(公告)号：EP1183828A2
公开(公告)日：2002-03-06
申请号：EP00935995.1
申请日：2000-05-16
申请人： Avici Systems
发明人： DALLY, William, J. , CARVEY, Philip, P. , KING, P., Allen , MANN, William, F. , DENNISON, Larry, R.
IPC分类号： H04L12/44 , H04L29/06
CPC分类号： H04L49/9078 , H04L49/1515 , H04L49/251 , H04L49/3036 , H04L49/90 , H04L49/901 , H04L49/9047 , H04L49/9073
摘要： In a fabric router, flits are stored on chip in a first set of rapidly accessible flit buffers, and overflow from the first set of flit buffers is stored in a second set of off-chip flit buffers that are accessed more slowly than the first set. The flit buffers may include a buffer pool accessed through a pointer array or a set associative cache. Flow control between network nodes stops the arrival of new flits while transferring flits between the first set of buffers and the second of buffers.

9. 发明公开

EP0991231A1 Packet switch adapter for variable length packets 有权
标题翻译： Paketvermittlunganpassungseinrichtung fen Datenpaketen mit variablerLänge
公开(公告)号：EP0991231A1
公开(公告)日：2000-04-05
申请号：EP98117128.3
申请日：1998-09-10
申请人： International Business Machines Corporation
发明人： Clauberg, Rolf
IPC分类号： H04L12/56
CPC分类号： H04L49/103 , H04L49/205 , H04L49/25 , H04L49/3036
摘要： The present invention concerns a packet-processing apparatus and a packet switch adapter for the processing of variable-length packets comprising packet data and packet information. The adapter and/or the apparatus comprises a distributor for distributing the packets to several parallel, identical processing paths, each comprising at least one processing unit, whereto the packets are fed and which is able to process only for one of the packets its packet information at any moment in time. The feeding is interruptable for feeding a different of the packets to another of the processing paths. Furthermore, a packet-processing method for distributing received variable-length packets to several parallel, identical processing paths is disclosed.
摘要翻译：本发明涉及用于处理包括分组数据和分组信息的可变长度分组的分组处理装置和分组交换适配器。适配器和/或设备包括分配器，用于将分组分发到几个并行的相同的处理路径，每个处理路径包括至少一个处理单元，其中分组被馈送并且能够仅处理分组信息中的一个分组在任何时候。馈送是可中断的，用于将不同的分组馈送到另一个处理路径。此外，公开了一种用于将接收的可变长度分组分发到多个并行的相同处理路径的分组处理方法。

10. 发明公开

EP0614585A1 METHOD AND UNIT FOR THE RECONSTRUCTION OF THE CORRECT SEQUENCE OF ATM CELLS 失效
标题翻译：方法和设备恢复ATM信元的正确顺序。
公开(公告)号：EP0614585A1
公开(公告)日：1994-09-14
申请号：EP92923269.0
申请日：1992-11-05
申请人： ITALTEL SOCIETA ITALIANA TELECOMUNICAZIONI s.p.a.
发明人： COLLIVIGNARELLI, Marco
IPC分类号： H04L12 , H04Q11
CPC分类号： H04L49/50 , H04L49/20 , H04L49/30 , H04L49/3036 , H04L2012/565 , H04Q11/0478
摘要： Procédé et unité de reconstitution de l'ordre initial de la séquence du débit des cellules de données associées à un même canal virtuel (VC) ou trajet virtuel (VP) à la sortie du réseau de commutation en mode de transfert asynchrone (ATM) à commande de cellules de données de haute priorité. Le procédé se fonde sur une égalisation des temporisations maximum pour la programmation des cellules de données à transférer à la sortie, au moyen de listes adressées par des indicateurs et d'un système de files d'attente communes permettant la gestion des conflits d'utilisation par davantage de cellules de données pour chaque tranche de temps de sortie, ce qui permet de réaliser des économies significatives d'espace mémoire. L'unité de remise en séquence comprend des mémoires dont les dimensions dépendent du nombre maximal de cellules de données réellement présentes dans l'unité de remise en séquence.

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