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1. 发明公开

EP0877517A2 Output interface for a digital communication system 失效
标题翻译：输出接口，用于数字通信系统
公开(公告)号：EP0877517A2
公开(公告)日：1998-11-11
申请号：EP98202130.5
申请日：1996-03-19
申请人： Discovision Associates
发明人： Claydon, Anthony Peter John , MacFarlane, Charles D. , Gammack, Richard John , Jones, Anthony M. , Robbins, William P, , Barnes, Mark Michael
IPC分类号： H04L27/34 , H04L25/02
CPC分类号： H04L1/0057 , H03K5/24 , H03M13/15 , H03M13/151 , H03M13/2707 , H03M13/2764 , H04L1/0045 , H04L1/0071 , H04L7/0334 , H04L25/03038 , H04L25/03866 , H04L25/062 , H04L27/02 , H04L27/2273 , H04L27/3809 , H04L2027/0032 , H04L2027/0061 , H04L2027/0067 , H04L2027/0073 , H04L2027/0081 , H04N5/211 , H04N5/4401 , H04N5/4446 , H04N5/455 , H04N5/52
摘要： An output interface for transferring data from a data source operating at a first clock rate provided by a first clock signal to a data sink operating at a second clock rate provided by a second clock signal comprising :

first latch receiving data from said data source and operable at said first clock rate ;
second latch operable at said second clock rate, said second latch receiving data words from said first latch ;
first signal generator operable at said first clock rate, said first signal generator producing a data valid signal ;
It further comprises :
at least one third latch operable at said second clock rate, said third latch receiving said data valid signal from said first signal generator in response to said second clock signal ;
second signal generator operable at said second clock rate, said second signal generator activating a load data signal to said second latch in response to receipt of said data valid signal from said third latch ; and
a FIFO buffer coupled to said second latch and receiving data therefrom, wherein data words received by said FIFO buffer from said second latch are identical to corresponding data words received by said second latch from said first latch ; whereby data is transferred from said first latch to said second latch in response to receipt by said second latch of said second clock signal when said load data signal is active.

2. 发明授权

EP0877516B1 Signal Processing System 失效
标题翻译：信号处理系统
公开(公告)号：EP0877516B1
公开(公告)日：2001-05-23
申请号：EP98202129.7
申请日：1996-03-19
申请人： Discovision Associates
发明人： Claydon, Anthony Peter John , Gammack, Richard John
IPC分类号： H04L27/233 , H04L27/38
CPC分类号： H04L7/0029 , H04L1/0054 , H04L1/0057 , H04L1/0065 , H04L1/0068 , H04L7/0334 , H04L7/0335 , H04L27/3872 , H04L2027/0028 , H04L2027/0057 , H04L2027/0067 , H04N21/2383 , H04N21/4382

3. 发明公开

EP0877514A2 Matched filter 失效
标题翻译：调整的信号滤波
公开(公告)号：EP0877514A2
公开(公告)日：1998-11-11
申请号：EP98202131.3
申请日：1996-03-19
申请人： Discovision Associates
发明人： Claydon, Anthony Peter John , MacFarlane, Charles D. , Gammack, Richard John , Jones, Anthony M. , Robbins, William P. , Barnes, Mark Michael
IPC分类号： H04L25/03
CPC分类号： H04L1/0057 , H03K5/24 , H03M13/15 , H03M13/151 , H03M13/2707 , H03M13/2764 , H04L1/0045 , H04L1/0071 , H04L7/0334 , H04L25/03038 , H04L25/03866 , H04L25/062 , H04L27/02 , H04L27/2273 , H04L27/3809 , H04L2027/0032 , H04L2027/0061 , H04L2027/0067 , H04L2027/0073 , H04L2027/0081 , H04N5/211 , H04N5/4401 , H04N5/4446 , H04N5/455 , H04N5/52
摘要： Apparatus for processing a train of signal pulses having even-numbered and odd-numbered pulses, comprising :

a pulse shaping Nyquist filter having a plurality of even-numbered taps and a plurality of odd-numbered taps ;
a frequency down converter coupled to said filter, and operative on said signal pulses;
a circuit incorporated in said Nyquist filter for removing a portion of said signal pulses ;
This apparatus further comprises :
a stream-splitting circuit for connecting the even-numbered pulses to said even-numbered taps, and for connecting the odd-numbered pulses to said odd numbered taps ;
a plurality of first multipliers for multiplying said even-numbered pulses by a first set of coefficients ;
a plurality of second multipliers for multiplying said odd-numbered pulses by a second set of coefficients ; and
a plurality of adding circuits, each connected to an output of a said first multiplier and an output of a said second multiplier.

4. 发明公开

EP0748056A3 An error detection and correction system for a stream of encoded data 失效
标题翻译：用于编码数据流错误检测和纠正的方法
公开(公告)号：EP0748056A3
公开(公告)日：1997-07-02
申请号：EP96304168.6
申请日：1996-06-06
申请人： DISCOVISION ASSOCIATES
发明人： Claydon, Anthony Peter John , Thomas, Richard James , Gammack, Richard John , Foxcroft, Thomas , Robbins, William Philip , Kuligowski, Andrew Peter , MacFarlane, Charles Dunlop
IPC分类号： H03M13/00
CPC分类号： H04L1/0065 , H03M13/23 , H03M13/41 , H03M13/4169 , H03M13/6362 , H03M13/6502 , H04L1/0009 , H04L1/0054 , H04L1/0068 , H04L1/0071
摘要： The invention provides a decoder of symbols of received data, the data being encoded according to a convolutional encoding scheme and transmitted through a communications channel. The data is punctuated according to a puncturing matrix, and has a plurality of state values which describe a sequence of state transitions. The decoder has a generation unit that accepts the received data for calculating metrics of the transitions thereof. A selector responsive to the generation unit selects a path of transitions corresponding to the path produced by a transmitter of the data stream. A traceback unit maintains historical information representative of sequential decision operations of the selector. A counter is provided for counting illegal state transitions of the path selected by the selector, and a control unit, responsive to the counter, determines a puncture rate and adjusts a puncture phase of the received data. The decoder can be used in a VLSl receiver circuit which is adapted to the reception of QPSK modulated data.

5. 发明公开

EP0874499A2 Analog-to-digital converter for digital receiver 失效
标题翻译： A / D Wandler用于数字接收机
公开(公告)号：EP0874499A2
公开(公告)日：1998-10-28
申请号：EP98202124.8
申请日：1996-03-19
申请人： Discovision Associates
发明人： Claydon, Anthony Peter John , MacFarlane, Charles D. , Gammack, Richard John , Jones, Anthony M. , Robbins, William P. , Barnes, Mark
IPC分类号： H04L25/06
CPC分类号： H04L1/0057 , H03K5/24 , H03M13/15 , H03M13/151 , H03M13/2707 , H03M13/2764 , H04L1/0045 , H04L1/0071 , H04L7/0334 , H04L25/03038 , H04L25/03866 , H04L25/062 , H04L27/02 , H04L27/2273 , H04L27/3809 , H04L2027/0032 , H04L2027/0061 , H04L2027/0067 , H04L2027/0073 , H04L2027/0081 , H04N5/211 , H04N5/4401 , H04N5/4446 , H04N5/455 , H04N5/52
摘要： An analog-to-digital converter apparatus, comprising a comparator having first and second units, each of said units comprising :

a capacitor connected to a first node and a second node ;
a first switch means for connecting said first node to a selected one of an input voltage and a reference voltage ;
an inverter having an input connected to said second node, and an output; and
a second switch means for connecting said output of said inverter to said second node of an other of said units.

6. 发明公开

EP0874466A2 Reed-Solomon decoding circuit and method 失效
标题翻译：里德 - 所罗门 - dekodierungsschaltung und -Verfahren
公开(公告)号：EP0874466A2
公开(公告)日：1998-10-28
申请号：EP98202125.5
申请日：1996-03-19
申请人： Discovision Associates
发明人： Claydon, Anthony Peter John , MacFarlane, Charles D. , Gammack, Richard John , Jones, Anthony M. , Robbins, William P. , Barnes, Mark Michael
IPC分类号： H03M13/00 , H04L1/00
CPC分类号： H04L1/0057 , H03K5/24 , H03M13/15 , H03M13/151 , H03M13/2707 , H03M13/2764 , H04L1/0045 , H04L1/0071 , H04L7/0334 , H04L25/03038 , H04L25/03866 , H04L25/062 , H04L27/02 , H04L27/2273 , H04L27/3809 , H04L2027/0032 , H04L2027/0061 , H04L2027/0067 , H04L2027/0073 , H04L2027/0081 , H04N5/211 , H04N5/4401 , H04N5/4446 , H04N5/455 , H04N5/52
摘要： A Reed-Solomon decoding circuit for decoding a packet of information R(x), the packet being an assembled packet C(x) having an injected error E(x), the assembled packet C(x) being of the type having a plurality of information bytes and at least one parity byte, the circuit comprising :

a FIFO buffer that accepts a packet of data R(x) for storage therein, said stored data comprising at least a plurality of information bytes ;
means for calculating syndromes of said packet of data R(x) according to an equation : S j = i = 0 n - 1 rx i α i(j + m 0 ) wherein :

S j is the jth syndrome,
n is the number of bytes in said packet R(x),
m 0 is an arbitrary integer,
rx i is the ith byte in a packet,
α x is the xth α in a Galois Field ;

a first circuit coupled to said means for calculating syndromes for performing a Berlekamp algorithm to generate a first signal representative of a locator polynomial Λ(x) and second signal representative of an evaluator polynomial Ω(x), said first circuit comprising :

a first register for holding a portion of a locator polynomial Λ(x) in a first iteration of
said Berlekamp algorithm ;
a second register for holding a portion of a D polynomial in said first iteration of said
Berlekamp algorithm ; and
It comprises :

a first switch means for interchanging an address of said first register with an address of said second register to access a required portion of said D polynomial and of said locator polynomial Λ(x) from said first register and said second register respectively in a second iteration of said Berlekamp algorithm ;
a second circuit coupled to said first signal and said second signal of said first circuit for performing a Chien search on said locator polynomial Λ(x), and for determining a magnitude of error at a location in said packet R(x) according to the equation : E(x) = Ω ( α -i ) Λ' ( α -i ) α i ; and
an adder coupled to an output of said FIFO buffer and to an output of said second circuit.
摘要翻译：用于解码信息包R（x）的Reed-Solomon解码电路，该分组是具有注入错误E（x）的组合分组C（x），组合分组C（x）是具有多个的信息字节和至少一个奇偶校验字节，所述电路包括：FIFO缓冲器，其接收用于存储在其中的数据R（x）的分组，所述存储的数据至少包括多个信息字节; 用于根据以下等式计算所述数据分组R（x）的综合征的装置：其中：Sj是第j个综合征，n是所述分组R（x）中的字节数，m0是任意整数，rxi 是分组中的第i个字节，alpha 是伽罗瓦域中的第x个字母; 耦合到所述用于计算用于执行Berlekamp算法以产生表示定位多项式LAMBDA（x）的第一信号和表示评估器多项式OMEGA（x）的第二信号）的综合征的装置的第一电路，所述第一电路包括：第一寄存器用于在所述Berlekamp算法的第一次迭代中保持定位多项式LAMBDA（x）的一部分; 第二寄存器，用于在所述Berlekamp算法的所述第一次迭代中保持D多项式的一部分; 并且它包括：第一开关装置，用于将所述第一寄存器的地址与所述第二寄存器的地址交换以分别从所述第一寄存器和所述第二寄存器分别访问所述D多项式的所需部分和所述定位多项式LAMBDA（x）在所述Berlekamp算法的第二次迭代中; 耦合到所述第一信号的所述第一信号和所述第一电路的所述第二信号的第二电路，用于对所述定位多项式LAMBDA（x）执行Chien搜索，并且根据所述第二信号确定所述分组R（x）中的位置处的误差的大小，方程式： $; 以及耦合到所述FIFO缓冲器的输出和所述第二电路的输出的加法器。$

7. 发明公开

EP0748118A2 Signal processing system 无效
标题翻译： Signalverarbeitungssystem
公开(公告)号：EP0748118A2
公开(公告)日：1996-12-11
申请号：EP96301867.6
申请日：1996-03-19
申请人： DISCOVISION ASSOCIATES
发明人： Claydon, Anthony Peter John , Gammack, Richard John
IPC分类号： H04N7/12
CPC分类号： H04L7/0029 , H04L1/0054 , H04L1/0057 , H04L1/0065 , H04L1/0068 , H04L7/0334 , H04L7/0335 , H04L27/3872 , H04L2027/0028 , H04L2027/0057 , H04L2027/0067 , H04N21/2383 , H04N21/4382
摘要： A CMOS integrated signal processing system for a sampling receiver includes a timing recovery circuit, wherein an on-chip numerically controlled oscillator is operative at periods T that are initially equal to the nominal baud rate of the signals controls a sinc interpolator receiving samples at the sampling rate. A loop filter is coupled to the sinc interpolator and to the numerically controlled oscillator. The arrangement is capable of handling various symbol rates. The system includes a circuit for carrier recovery, having a second on-chip numerically controlled oscillator, a digital derotation circuit responsive to the second numerically controlled oscillator, accepting an in phase component and a quadrature component of the sampled signals. An adaptive phase error estimation circuit is coupled in a feedback loop.
摘要翻译：用于采样接收机的CMOS集成信号处理系统包括定时恢复电路，其中片上数控振荡器在周期T处工作，周期T最初等于信号的标称波特率，控制正弦内插器在采样时接收采样率。环路滤波器耦合到正弦内插器和数控振荡器。该装置能够处理各种符号率。该系统包括用于载波恢复的电路，具有第二片上数控振荡器，响应于第二数控振荡器的数字解旋转电路，接受采样信号的同相分量和正交分量。自适应相位误差估计电路耦合在反馈回路中。

8. 发明公开

EP0874499A3 Analog-to-digital converter for digital receiver 失效
标题翻译： A / D WandlerfürdigitalenEmpfänger
公开(公告)号：EP0874499A3
公开(公告)日：2001-02-07
申请号：EP98202124.8
申请日：1996-03-19
申请人： Discovision Associates
发明人： Claydon, Anthony Peter John , MacFarlane, Charles D. , Gammack, Richard John , Jones, Anthony M. , Robbins, William P. , Barnes, Mark
IPC分类号： H03K5/24 , H04L25/06
CPC分类号： H04L1/0057 , H03K5/24 , H03M13/15 , H03M13/151 , H03M13/2707 , H03M13/2764 , H04L1/0045 , H04L1/0071 , H04L7/0334 , H04L25/03038 , H04L25/03866 , H04L25/062 , H04L27/02 , H04L27/2273 , H04L27/3809 , H04L2027/0032 , H04L2027/0061 , H04L2027/0067 , H04L2027/0073 , H04L2027/0081 , H04N5/211 , H04N5/4401 , H04N5/4446 , H04N5/455 , H04N5/52
摘要： An analog-to-digital converter apparatus, comprising a comparator having first and second units, each of said units comprising : a capacitor connected to a first node and a second node ; a first switch means for connecting said first node to a selected one of an input voltage and a reference voltage ; an inverter having an input connected to said second node, and an output; and a second switch means for connecting said output of said inverter to said second node of an other of said units.
摘要翻译：提供了一种利用多级残留边带传输的综合数字通信系统。通信系统从有限带宽信道接收多电平脉冲幅度调制数字信号。该系统包括在恢复数字数据之前对输入信号进行解调，采样和滤波的处理阶段。其他级恢复定时并锁定到发射信号的频率和相位，并提供自动增益控制。自适应均衡器，纠错电路和输出接口恢复数字数据并提供传输到其他设备。

9. 发明授权

EP0748118B1 Signal processing system 无效
公开(公告)号：EP0748118B1
公开(公告)日：1999-09-01
申请号：EP96301867.6
申请日：1996-03-19
申请人： DISCOVISION ASSOCIATES
发明人： Claydon, Anthony Peter John , Gammack, Richard John
IPC分类号： H04N7/12 , H04L7/02
CPC分类号： H04L7/0029 , H04L1/0054 , H04L1/0057 , H04L1/0065 , H04L1/0068 , H04L7/0334 , H04L7/0335 , H04L27/3872 , H04L2027/0028 , H04L2027/0057 , H04L2027/0067 , H04N21/2383 , H04N21/4382

10. 发明公开

EP0877516A1 Signal Processing System 失效
标题翻译：信号处理系统
公开(公告)号：EP0877516A1
公开(公告)日：1998-11-11
申请号：EP98202129.7
申请日：1996-03-19
申请人： Discovision Associates
发明人： Claydon, Anthony Peter John , Gammack, Richard John
IPC分类号： H04L27/233 , H04L27/38
CPC分类号： H04L7/0029 , H04L1/0054 , H04L1/0057 , H04L1/0065 , H04L1/0068 , H04L7/0334 , H04L7/0335 , H04L27/3872 , H04L2027/0028 , H04L2027/0057 , H04L2027/0067 , H04N21/2383 , H04N21/4382
摘要： A circuit for processing modulated signals, comprising a semiconductor integrated carrier recovery circuit operative to control a demodulator, comprising :

an adaptive phase error estimation circuit executing a least-mean-square algorithm and comprising :

first and second slicers, accepting a derotated in-phase value and a derotated quadrature value respectively ;
first and second subtracters, for respectively determining first and second differences between said derotated in phase value and said sliced in phase value, and between said derotated quadrature value and said sliced quadrature value ; and
an angulator, accepting said first and second differences and outputting a phase error estimate ; and

a digital derotation circuit responsive to said phase error estimation circuit, and
accepting an in phase component and a quadrature component of sampled signals.
摘要翻译： 1。一种用于处理调制信号的电路，包括用于控制解调器的半导体集成载波恢复电路，包括：自适应相位误差估计电路，执行最小均方算法并且包括：第一和第二限幅器，接收反相值和一个消旋正交值; 第一和第二减法器，用于分别确定所述相位反转值与所述相位切分值之间以及所述反转正交值与所述切分正交值之间的第一和第二差值; 和角度器，接受所述第一和第二差值并输出相位误差估计值; 以及响应于所述相位误差估计电路并接受采样信号的同相分量和正交分量的数字消旋电路。

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