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1. 发明公开

EP0748124A3 Signal processing apparatus and method 失效
标题翻译：一种信号处理装置和方法
公开(公告)号：EP0748124A3
公开(公告)日：1999-05-06
申请号：EP96301869.2
申请日：1996-03-19
申请人： DISCOVISION ASSOCIATES
发明人： Claydon, Anthony P.J. , Macfarlane, Charles D. , Gammack, Richard J. , Jones, Anthony M. , Robbins, William P. , Barnes, Mark
IPC分类号： H04N7/52 , H04N7/60 , H04Q11/02
CPC分类号： H04L1/0057 , H03K5/24 , H03M13/15 , H03M13/151 , H03M13/2707 , H03M13/2764 , H04L1/0045 , H04L1/0071 , H04L7/0334 , H04L25/03038 , H04L25/03866 , H04L25/062 , H04L27/02 , H04L27/2273 , H04L27/3809 , H04L2027/0032 , H04L2027/0061 , H04L2027/0067 , H04L2027/0073 , H04L2027/0081 , H04N5/211 , H04N5/4401 , H04N5/4446 , H04N5/455 , H04N5/52
摘要： An integrated digital communication system utilizing multilevel vestigial sideband transmission is provided. The communication system receives a multi-level pulse-amplitude modulated digital signal from a limited bandwidth channel. The system includes processing stages which demodulate, sample and filter the incoming signal prior to recovery of the digital data. Other stages recover the timing and lock on to the frequency and phase of the transmitted signal, as well as provide for automatic gain control. An adaptive equalizer, error correction circuitry, and an output interface recover the digital data and provide for transfer to other devices.

2. 发明公开

EP0895167A3 Method and apparatus for interfacing with ram 失效
公开(公告)号：EP0895167A3
公开(公告)日：1999-03-10
申请号：EP98202092.7
申请日：1995-02-28
申请人： Discovision Associates
发明人： Jones, Anthony M. , Robbins, William Philip , Patterson, Donald William Walker , Wise, Adrian Philip , Finch, Helen Rosemary , Sotheran, Martin William
IPC分类号： G06F13/42
CPC分类号： G06F13/1689 , G06F12/0207 , G06F12/04 , G06F12/0607 , G06F13/1673 , G06F13/28 , H04N19/13 , H04N19/42 , H04N19/423 , H04N19/61 , H04N19/91
摘要： A configurable RAM interface for connecting a bus to RAM comprising :
a bus configuration register for specifying a number of bits on the bus ; means for receiving from the bus a plurality of data words comprising multiword tokens; means for receiving from the bus a complete address associated with the plurality of data words ; means for generating a series of addresses in RAM into which the buffered data words will be written ; means for writing the buffered data words into RAM at the generated addresses ; and means for buffering the received data words comprising : at least three memory buffers for use as a swing buffer including an arrival buffer, an output buffer and at least one intermediate buffer ; a buffer manager for allocating said buffers for reference by said means for generating a series of addresses, clearing said buffers for occupation by subsequently arriving data, and maintaining status information of said buffers, wherein said status information comprises a state VACANT, wherein one of said buffers is available, a state IN_USE, wherein said one buffer is referenced by said means for receiving from the bus an address and by said means for receiving from the bus a plurality of data words, a state FULL, wherein said one buffer is occupied by data, and a state READY; wherein said buffer manager asserts a late arrival signal indicating that a buffer in said state READY is not in synchronization with a data output rate.

3. 发明公开

EP0895161A3 Method for addressing variable width memory data 失效
标题翻译：寻址可变宽度存储器数据的方法
公开(公告)号：EP0895161A3
公开(公告)日：1999-02-10
申请号：EP98202093.5
申请日：1995-02-28
申请人： Discovision Associates
发明人： Jones, Anthony M. , Robbins, William Philip , Patterson, Donald William Walker , Wise, Adrian Philip , Finch, Helen Rosemary , Sotheran, Martin William
IPC分类号： G06F12/04
CPC分类号： G06F13/1689 , G06F12/0207 , G06F12/04 , G06F12/0607 , G06F13/1673 , G06F13/28 , H04N19/13 , H04N19/42 , H04N19/423 , H04N19/61 , H04N19/91
摘要： A method for generating a substituted address in a memory comprising the steps of :
providing a first memory having words of predetermined width and composed of partial words ; rotating a partial word to be accessed to a least significant bit justification ; extending a remaining part of a word which contains the partial word so that an accessed word will be recognized as the partial word ; delimiting a substitution field of the partial word with a termination marker, said substitution field being variable in size ; substituting data in all of said substitution field to define a part of an address of a second memory, said address comprising said substituted field and an unsubstituted portion of said partial word ; restoring the remaining part of the word ; and
rotating the word until the partial word is restored to its original position.
摘要翻译：一种用于在存储器中产生替换地址的方法，包括以下步骤：提供具有预定宽度并由部分字组成的字的第一存储器; 将要访问的部分字旋转到最低有效位对齐; 扩展包含部分单词的单词的剩余部分，以便将访问的单词识别为部分单词; 利用终止标记来限定所述部分词的替代字段，所述替换字段的大小是可变的; 用所有所述替换字段中的数据进行替换以定义第二存储器的地址的一部分，所述地址包括所述替换字段和所述部分字的未替代部分; 恢复单词的其余部分; 并旋转单词直到部分单词恢复到其原始位置。

4. 发明公开

EP0895422A2 Image formatter for processing encoded video data 失效
标题翻译：图像格式化器用来处理编码的视频数据
公开(公告)号：EP0895422A2
公开(公告)日：1999-02-03
申请号：EP98202090.1
申请日：1995-02-28
申请人： Discovision Associates
发明人： Jones, Anthony M. , Robbins, William Philip , Patterson, Donald William Walker , Wise, Adrian Philip , Finch, Helen Rosemary , Sotheran, Martin William
IPC分类号： H04N7/24
CPC分类号： G06F13/1689 , G06F12/0207 , G06F12/04 , G06F12/0607 , G06F13/1673 , G06F13/28 , H04N19/13 , H04N19/42 , H04N19/423 , H04N19/61 , H04N19/91
摘要： An image formatter for processing encoded video data comprising :

an input element for receiving encoded data having a frame rate and an arrival rate ;
a memory defining at least three buffers for storage of the encoded data, one of said buffers being a display buffer, and another of said buffers being an arrival buffer ;
a write address generator for generating write addresses for data being stored thereat in said memory ;
a read address generator for generating read addresses for reading data stored thereat in said memory ;
an output interface linked to said read address generator that produces decoded data at a display rate ; and
a buffer manager responsive to said arrival rate, said display rate, and said frame rate for allocating said buffers to said write address generator and said read address generator, wherein said buffers are allocated to said write address generator in response to a timing regime

5. 发明公开

EP0877514A2 Matched filter 失效
标题翻译：调整的信号滤波
公开(公告)号：EP0877514A2
公开(公告)日：1998-11-11
申请号：EP98202131.3
申请日：1996-03-19
申请人： Discovision Associates
发明人： Claydon, Anthony Peter John , MacFarlane, Charles D. , Gammack, Richard John , Jones, Anthony M. , Robbins, William P. , Barnes, Mark Michael
IPC分类号： H04L25/03
CPC分类号： H04L1/0057 , H03K5/24 , H03M13/15 , H03M13/151 , H03M13/2707 , H03M13/2764 , H04L1/0045 , H04L1/0071 , H04L7/0334 , H04L25/03038 , H04L25/03866 , H04L25/062 , H04L27/02 , H04L27/2273 , H04L27/3809 , H04L2027/0032 , H04L2027/0061 , H04L2027/0067 , H04L2027/0073 , H04L2027/0081 , H04N5/211 , H04N5/4401 , H04N5/4446 , H04N5/455 , H04N5/52
摘要： Apparatus for processing a train of signal pulses having even-numbered and odd-numbered pulses, comprising :

a pulse shaping Nyquist filter having a plurality of even-numbered taps and a plurality of odd-numbered taps ;
a frequency down converter coupled to said filter, and operative on said signal pulses;
a circuit incorporated in said Nyquist filter for removing a portion of said signal pulses ;
This apparatus further comprises :
a stream-splitting circuit for connecting the even-numbered pulses to said even-numbered taps, and for connecting the odd-numbered pulses to said odd numbered taps ;
a plurality of first multipliers for multiplying said even-numbered pulses by a first set of coefficients ;
a plurality of second multipliers for multiplying said odd-numbered pulses by a second set of coefficients ; and
a plurality of adding circuits, each connected to an output of a said first multiplier and an output of a said second multiplier.

6. 发明公开

EP0874499A3 Analog-to-digital converter for digital receiver 失效
标题翻译： A / D WandlerfürdigitalenEmpfänger
公开(公告)号：EP0874499A3
公开(公告)日：2001-02-07
申请号：EP98202124.8
申请日：1996-03-19
申请人： Discovision Associates
发明人： Claydon, Anthony Peter John , MacFarlane, Charles D. , Gammack, Richard John , Jones, Anthony M. , Robbins, William P. , Barnes, Mark
IPC分类号： H03K5/24 , H04L25/06
CPC分类号： H04L1/0057 , H03K5/24 , H03M13/15 , H03M13/151 , H03M13/2707 , H03M13/2764 , H04L1/0045 , H04L1/0071 , H04L7/0334 , H04L25/03038 , H04L25/03866 , H04L25/062 , H04L27/02 , H04L27/2273 , H04L27/3809 , H04L2027/0032 , H04L2027/0061 , H04L2027/0067 , H04L2027/0073 , H04L2027/0081 , H04N5/211 , H04N5/4401 , H04N5/4446 , H04N5/455 , H04N5/52
摘要： An analog-to-digital converter apparatus, comprising a comparator having first and second units, each of said units comprising : a capacitor connected to a first node and a second node ; a first switch means for connecting said first node to a selected one of an input voltage and a reference voltage ; an inverter having an input connected to said second node, and an output; and a second switch means for connecting said output of said inverter to said second node of an other of said units.
摘要翻译：提供了一种利用多级残留边带传输的综合数字通信系统。通信系统从有限带宽信道接收多电平脉冲幅度调制数字信号。该系统包括在恢复数字数据之前对输入信号进行解调，采样和滤波的处理阶段。其他级恢复定时并锁定到发射信号的频率和相位，并提供自动增益控制。自适应均衡器，纠错电路和输出接口恢复数字数据并提供传输到其他设备。

7. 发明公开

EP0874491A2 Signal processing apparatus and method 失效
标题翻译：一种信号处理装置和方法
公开(公告)号：EP0874491A2
公开(公告)日：1998-10-28
申请号：EP98202126.3
申请日：1996-03-19
申请人： Discovision Associates
发明人： Claydon, Anthony Peter John , MacFarlane, Charles D. , Gammack, Richard John , Jones, Anthony M. , Robbins, Williams P. , Barnes, Mark Michael
IPC分类号： H04L1/00 , H03M13/22
CPC分类号： H04L1/0057 , H03K5/24 , H03M13/15 , H03M13/151 , H03M13/2707 , H03M13/2764 , H04L1/0045 , H04L1/0071 , H04L7/0334 , H04L25/03038 , H04L25/03866 , H04L25/062 , H04L27/02 , H04L27/2273 , H04L27/3809 , H04L2027/0032 , H04L2027/0061 , H04L2027/0067 , H04L2027/0073 , H04L2027/0081 , H04N5/211 , H04N5/4401 , H04N5/4446 , H04N5/455 , H04N5/52
摘要： A deinterleaving circuit for processing of a signal comprising blocks of interleaved data packets represented therein, comprising :

a random access memory for memorizing a data stream of said blocks of interleaved packets, wherein a capacity of said memory does not exceed any of said blocks ;
a first circuit for generating an address signal representing a sequence of addresses of said random access memory, wherein successive addresses differ by an addressing interval ;
a second circuit for successively reading and writing data out of and into said random access memory respectively at a reading address and a writing address of said random access memory, said reading address and said writing address being determined by said address signal, wherein said address signal is constant during an operation comprising reading and writing data at said address ; and
a third circuit responsive to a signal ACCEPT_BLOCK for periodically increasing said addressing interval by a value equal to an interleaving depth of said interleaved packets wherein said signal ACCEPT_BLOCK is asserted after completion of an operation comprising a complete deinterleaving of one of said blocks of data.

8. 发明公开

EP0748124A2 Signal processing apparatus and method 失效
标题翻译： Signalverarbeitungsgerätund Verfahren
公开(公告)号：EP0748124A2
公开(公告)日：1996-12-11
申请号：EP96301869.2
申请日：1996-03-19
申请人： DISCOVISION ASSOCIATES
发明人： Claydon, Anthony P.J. , Macfarlane, Charles D. , Gammack, Richard J. , Jones, Anthony M. , Robbins, William P. , Barnes, Mark
IPC分类号： H04N7/52 , H04N7/60 , H04Q11/02
CPC分类号： H04L1/0057 , H03K5/24 , H03M13/15 , H03M13/151 , H03M13/2707 , H03M13/2764 , H04L1/0045 , H04L1/0071 , H04L7/0334 , H04L25/03038 , H04L25/03866 , H04L25/062 , H04L27/02 , H04L27/2273 , H04L27/3809 , H04L2027/0032 , H04L2027/0061 , H04L2027/0067 , H04L2027/0073 , H04L2027/0081 , H04N5/211 , H04N5/4401 , H04N5/4446 , H04N5/455 , H04N5/52
摘要： An integrated digital communication system utilizing multilevel vestigial sideband transmission is provided. The communication system receives a multi-level pulse-amplitude modulated digital signal from a limited bandwidth channel. The system includes processing stages which demodulate, sample and filter the incoming signal prior to recovery of the digital data. Other stages recover the timing and lock on to the frequency and phase of the transmitted signal, as well as provide for automatic gain control. An adaptive equalizer, error correction circuitry, and an output interface recover the digital data and provide for transfer to other devices.
摘要翻译：提供了一种利用多级残留边带传输的综合数字通信系统。通信系统从有限带宽信道接收多电平脉冲幅度调制数字信号。该系统包括在恢复数字数据之前对输入信号进行解调，采样和滤波的处理阶段。其他级恢复定时并锁定到发射信号的频率和相位，并提供自动增益控制。自适应均衡器，纠错电路和输出接口恢复数字数据并提供传输到其他设备。

9. 发明公开

EP0895166A3 Method and apparatus for interfacing with ram 失效
标题翻译：用于与RAM连接的方法和设备
公开(公告)号：EP0895166A3
公开(公告)日：1999-03-10
申请号：EP98202091.9
申请日：1995-02-28
申请人： Discovision Associates
发明人： Jones, Anthony M. , Robbins, William Philip , Patterson, Donald William Walker , Wise, Adrian Philip , Finch, Helen Rosemary , Sotheran, Martin William
IPC分类号： G06F13/42
CPC分类号： G06F13/1689 , G06F12/0207 , G06F12/04 , G06F12/0607 , G06F13/1673 , G06F13/28 , H04N19/13 , H04N19/42 , H04N19/423 , H04N19/61 , H04N19/91
摘要： An apparatus for connecting a bus to a RAM comprising :
a single address generator providing complete addresses that is clocked at a first clock rate; a RAM interface, comprising :
a plurality of swing buffers connected to a bus for receiving therefrom a plurality of data words from a source at a second clock rate ; a control coupled to said swing buffers a two-wire link connecting said control with said address generator wherein a request/acknowledge protocol is implemented therebetween via said link, wherein said two-wire link comprises a sender, a receiver, and a clock connected to said sender and said receiver, wherein data is transferred from said sender to said receiver upon a transition of said clock only when said sender is ready and said receiver is ready; wherein the interface is clocked at a third clock rate that is asynchronous with said first clock rate and said second clock rate, and data is transferred between a selected swing buffer and a RAM in response to a first signal that is generated by said control when said control receives an address from the address generator and said control receives a second signal from said selected swing buffer via said communication link
摘要翻译：一种用于将总线连接到RAM的设备，包括：提供以第一时钟速率计时的完整地址的单个地址发生器; RAM接口，包括：多个摆动缓冲器，连接到总线，用于以第二时钟速率从源接收来自源的多个数据字; 耦合到所述摆动缓冲器的控制器连接所述控制器和所述地址发生器的双线链路，其中经由所述链路在它们之间实现请求/确认协议，其中所述双线链路包括发送器，接收器和连接到所述发送者和所述接收者，其中，只有当所述发送者准备好并且所述接收者准备好时，在所述时钟转换时，数据才从所述发送者传送到所述接收者; 其中所述接口以与所述第一时钟速率和所述第二时钟速率不同步的第三时钟速率被时钟控制，并且响应于所述控制器在所述第一时钟速率和所述第二时钟速率之间产生的第一信号，在选择的摆动缓冲器和RAM之间传送数据控制器从地址发生器接收地址并且所述控制器经由所述通信链路从所述选择的摆动缓冲器接收第二信号

10. 发明公开

EP0895167A2 Method and apparatus for interfacing with ram 失效
标题翻译：用于与RAM连接的方法和设备
公开(公告)号：EP0895167A2
公开(公告)日：1999-02-03
申请号：EP98202092.7
申请日：1995-02-28
申请人： Discovision Associates
发明人： Jones, Anthony M. , Robbins, William Philip , Patterson, Donald William Walker , Wise, Adrian Philip , Finch, Helen Rosemary , Sotheran, Martin William
IPC分类号： G06F13/42
CPC分类号： G06F13/1689 , G06F12/0207 , G06F12/04 , G06F12/0607 , G06F13/1673 , G06F13/28 , H04N19/13 , H04N19/42 , H04N19/423 , H04N19/61 , H04N19/91
摘要： A configurable RAM interface for connecting a bus to RAM comprising :

a bus configuration register for specifying a number of bits on the bus ;
means for receiving from the bus a plurality of data words comprising multiword tokens;
means for receiving from the bus a complete address associated with the plurality of data words ;
means for generating a series of addresses in RAM into which the buffered data words will be written ;
means for writing the buffered data words into RAM at the generated addresses ; and
means for buffering the received data words comprising :
at least three memory buffers for use as a swing buffer including an arrival buffer, an output buffer and at least one intermediate buffer ;
a buffer manager for allocating said buffers for reference by said means for generating a series of addresses, clearing said buffers for occupation by subsequently arriving data, and maintaining status information of said buffers, wherein said status information comprises a state VACANT, wherein one of said buffers is available, a state IN_USE, wherein said one buffer is referenced by said means for receiving from the bus an address and by said means for receiving from the bus a plurality of data words, a state FULL, wherein said one buffer is occupied by data, and a state READY; wherein said buffer manager asserts a late arrival signal indicating that a buffer in said state READY is not in synchronization with a data output rate.
摘要翻译：一种用于将总线连接到RAM的可配置RAM接口，包括：总线配置寄存器，用于指定总线上的多个位; 用于从总线接收包括多词记号的多个数据字的装置; 用于从总线接收与多个数据字相关联的完整地址的装置; 用于在RAM中产生一系列地址的装置，缓冲数据字将被写入其中; 用于在所生成的地址处将缓冲的数据字写入RAM的装置; 以及用于缓冲所接收的数据字的装置，包括：至少三个存储器缓冲器，用作包括到达缓冲器，输出缓冲器和至少一个中间缓冲器的摆动缓冲器; 缓冲器管理器，用于通过所述用于产生一系列地址的装置分配所述缓冲器以供参考，通过随后到达的数据清除所述缓冲器以用于占用，并且维持所述缓冲器的状态信息，其中所述状态信息包括状态VACANT，其中所述缓冲器是可用的，状态IN_USE，其中所述一个缓冲器由所述用于从总线接收地址的装置以及通过所述用于从总线接收多个数据字的装置来引用，状态为FULL，其中所述一个缓冲器被数据和状态READY; 其中所述缓冲器管理器声明延迟到达信号，所述延迟到达信号指示所述状态READY中的缓冲器不与数据输出速率同步。

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