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1. 发明授权

EP2241050B1 RECEIVER WITH ENHANCED CLOCK AND DATA RECOVERY 有权转让
公开(公告)号：EP2241050B1
公开(公告)日：2018-08-08
申请号：EP09708941.1
申请日：2009-01-30
申请人： Rambus Inc.
发明人： LEE, Hae-Chang , LEIBOWITZ, Brian, S. , KIM, Jaeha , SAVOJ, Jafar
IPC分类号： H04L7/033 , H04L7/00 , H04L25/03 , H04L25/49
CPC分类号： H04L7/0016 , G06Q10/06312 , G06Q10/103 , H04L7/0004 , H04L7/0062 , H04L7/033 , H04L7/0331 , H04L7/0334 , H04L25/062 , H04L2025/0349 , H04L2027/004 , H04L2027/0067 , H04L2027/0069
摘要： A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

2. 发明公开

EP3331193A1 PHASE ADJUSTMENT CIRCUIT FOR CLOCK AND DATA RECOVERY CIRCUIT 有权
公开(公告)号：EP3331193A1
公开(公告)日：2018-06-06
申请号：EP18152216.0
申请日：2014-11-21
申请人： Intel Corporation
发明人： Giaconi, Stefano , Xu, Mingming
IPC分类号： H04L7/033 , H04L25/03 , H04L7/00
CPC分类号： H04L25/03057 , H04L7/0041 , H04L7/0058 , H04L7/033 , H04L7/0331 , H04L7/0332 , H04L7/0334 , H04L25/03025 , H04L2025/03598
摘要： Described are phase adjustment circuits for clock and data recovery circuits (CDRs). Systems and apparatuses may include an input to receive a serial data signal, an edge data tap to sample transition edges in the serial data signal for generating a data edge detection signal, a CDR circuit including a phase detector to receive the serial data signal and the data edge detection signal, and to output a phase lead/lag signal indicating the phase difference between the serial data signal and the data edge detection signal, and a phase adjustment circuit utilizing a decision feedback equalization (DFE) circuit. The CDR circuit is to output a recovered clock signal. During the operation of the phase adjustment circuit the CDR utilizes the DFE circuit to determine a locking position of the recovered clock signal.

3. 发明授权

EP3039810B1 OFFSET CALIBRATION AND ADAPTIVE CHANNEL DATA SAMPLE POSITIONING 有权
标题翻译：偏移量校准和自适应通道数据采样定位
公开(公告)号：EP3039810B1
公开(公告)日：2017-11-15
申请号：EP14725850.3
申请日：2014-04-09
申请人： Xilinx, Inc.
发明人： JENKINS, Michael O. , HSIEH, Cheng-Hsiang
IPC分类号： H04L7/033 , H04L25/06
CPC分类号： H04L7/0334 , H04L25/069

4. 发明公开

EP2643929A1 METHOD AND CIRCUIT FOR CLOCK RECOVERY OF A DATA STREAM DESCRIPTION 失效转让
标题翻译：方法与电路数据流的卒中恢复
公开(公告)号：EP2643929A1
公开(公告)日：2013-10-02
申请号：EP10807749.6
申请日：2010-11-23
申请人： Power-One Italy S.p.a.
发明人： VALIANI, Massimo , TAZZARI, Davide , VERNIA, Filippo
IPC分类号： H03D13/00 , H04L7/00
CPC分类号： H04L7/0331 , H03L7/0807 , H03L7/093 , H03L2207/50 , H04L7/0334
摘要： A method for clock recovery and data recovery from a data stream on a communication channel includes sampling a data stream on the communication channel at a sampling frequency determined by a clock signal and generating a sampled signal. The method further includes determining a phase shift between the communication data stream and the sampled signal and modifying the phase of the clock signal on the basis of the phase shift to obtain a desired phase difference between the sampled signal and the data stream.

5. 发明公开

EP2515467A1 Symbol clock recovery circuit 有权
标题翻译： Symboltaktrückgewinnungsschaltung
公开(公告)号：EP2515467A1
公开(公告)日：2012-10-24
申请号：EP11163565.2
申请日：2011-04-21
申请人： NXP B.V.
发明人： Ciacci, Massimo , Van De Beek, Remco , Al-Kadi, Ghiath
IPC分类号： H04L7/033 , H04L7/04 , H04L27/00
CPC分类号： H04L7/0334 , H04L7/046 , H04L27/22 , H04L2007/047
摘要： A symbol clock recovery circuit is provided for a data communication system using coherent demodulation. The symbol clock recovery circuit comprises an analog-to-digital converter (101) comprising a first input for receiving a coherent-detected baseband analog signal (104) derived from a carrier signal, a second input for receiving an adapted symbol clock signal (106), and an output for outputting a digital signal (107) comprising a frame having a preamble with at least two symbols. The symbol clock recovery circuit comprises further a phase shifting unit (102) comprising a first input for receiving a symbol clock signal (105) derived from the carrier signal, and a timing detector (103), comprising a first input for receiving the digital signal from the analog-to-digital converter and an output for providing a signal (108) comprising information about an optimum sample phase to the phase shifting unit. The timing detector is adapted for detecting at least one zero crossing between the at least two symbols of the preamble of the frame of the digital signal, for determining a phase being associated with the zero crossing, and for calculating an optimum phase for sampling the coherent-detected baseband analog signal based on the calculated phase being associated with the zero crossing. The phase shifting unit comprises a second input for receiving from the timing detector the optimum phase for sampling the coherent-detected baseband analog signal, and is adapted for shifting the phase of the symbol clock signal according to the received optimum phase to generate an adapted symbol clock signal and for providing the adapted symbol clock signal to the analog-to-digital converter.
摘要翻译：为使用相干解调的数据通信系统提供符号时钟恢复电路。符号时钟恢复电路包括模数转换器（101），包括用于接收从载波信号导出的相干检测的基带模拟信号（104）的第一输入端，用于接收适配符号时钟信号（106 ）和用于输出数字信号（107）的输出，包括具有至少两个符号的具有前同步码的帧的数字信号（107）。符号时钟恢复电路还包括相移单元（102），包括用于接收从载波信号导出的符号时钟信号（105）的第一输入端和定时检测器（103），包括用于接收数字信号的第一输入端以及用于向相移单元提供包括关于最佳采样相位的信息的信号（108）的输出端。定时检测器适于检测数字信号的帧的前导码的至少两个符号之间的至少一个零交叉，用于确定与过零点相关联的相位，并且用于计算用于采样相干的最佳相位基于计算出的与过零点相关联的相位的检测到的基带模拟信号。相移单元包括第二输入，用于从定时检测器接收用于对相干检测的基带模拟信号进行采样的最佳相位，并且适于根据所接收的最佳相位移位符号时钟信号的相位，以产生适配符号时钟信号，并用于将适配符号时钟信号提供给模数转换器。

6. 发明公开

EP2405577A1 Phase detection method and circuit 失效
标题翻译： Phasenbestimmungsverfahren und Schaltung
公开(公告)号：EP2405577A1
公开(公告)日：2012-01-11
申请号：EP10168601.2
申请日：2010-07-06
申请人： Cisco Technology, Inc.
发明人： Stojanovic, Nebojsa
IPC分类号： H03L7/091
CPC分类号： H03L7/091 , H04L7/0087 , H04L7/0334
摘要： This invention relates to phase detection methods. According to a first embodiment, a signal is sampled in order to obtain an amplitude sample. Then an absolute value of the difference of the amplitude sample minus an average of amplitude samples is calculated. According to a second embodiment, the signal (50) is sampled at a first and second phase. This results in first and second amplitude samples (1, 2) which are compared to a first and second plurality of thresholds (3, 4), respectively, in order to assign first and second weighting values (w A1 , w B2 ) to each first and second amplitude sample, respectively, depending on to which range (S 2 , S 3 , S 4 ) between two adjacent thresholds the first and second amplitude sample belong. Then the sum or difference (45) of said first and second weighting values (w A1 , w B2 ) is calculated. The invention further relates to phase detection circuits that implement the inventive methods.
摘要翻译：本发明涉及相位检测方法。根据第一实施例，为了获得幅度采样，对信号进行采样。然后计算振幅样本的差的绝对值减去振幅样本的平均值。根据第二实施例，信号（50）在第一和第二阶段被采样。这导致分别与第一和第二多个阈值（3,4）进行比较的第一和第二振幅样本（1,2），以便将第一和第二加权值（w A1，w B2）分配给每个分别取决于第一和第二振幅样本所属的两个相邻阈值之间的哪个范围（S 2，S 3，S 4）的第一和第二振幅样本。然后计算所述第一和第二加权值（w A1，w B2）的和或差（45）。本发明还涉及实现本发明方法的相位检测电路。

7. 发明授权

EP1640733B1 Method and device for digitally measuring the phase of a signal 有权
标题翻译：用于信号的数字相位测量的方法和装置
公开(公告)号：EP1640733B1
公开(公告)日：2011-04-27
申请号：EP04292278.1
申请日：2004-09-22
申请人： Alcatel Lucent
发明人： Skerlj, Maurizio , Razzetti, Luca , Gastaldello, Stefano
IPC分类号： G01R25/08 , G01R25/00 , H04L7/033 , H04L1/20 , H03L7/091
CPC分类号： G01R25/08 , G01R25/005 , H03L7/091 , H04J3/1611 , H04L7/033 , H04L7/0334

8. 发明授权

EP1786165B1 CLOCK REGENERATION CIRCUIT 有权
标题翻译：时钟再生电路
公开(公告)号：EP1786165B1
公开(公告)日：2010-11-03
申请号：EP05780288.6
申请日：2005-08-15
申请人： NEC Corporation
发明人： KAWAI, Masahiro, NEC Corporation
IPC分类号： H04L27/38
CPC分类号： H04L7/0083 , H04L7/0334
摘要： It is possible to improve clock synchronization resistance against selectivity fading without lowering the stability of the clock phase synchronization control. A clock phase detector (7) constituting a clock reproduction PLL is preceded by an orthogonal component equalizer (6) for removing only an orthogonal component interference wave not affecting the clock regeneration, thereby assuring an opening of an eye pattern and maintaining the gain of the clock phase detector (7) without erasing the clock phase information. Accordingly, even when an inter-code interference is caused in a reception signal by selectivity fading or the like, it is possible to erase a part of the interference component and maintain a wide eye pattern opening. Thus, it is possible to improve the clock synchronization resistance against the selectivity fading without lowering the stability of the clock phase synchronization control.

9. 发明授权

EP0803998B1 Demodulation apparatus for data carried by a carrier wave 失效
标题翻译：解调数据调制的载波
公开(公告)号：EP0803998B1
公开(公告)日：2007-07-04
申请号：EP97302730.3
申请日：1997-04-22
申请人： SANYO ELECTRIC CO., LTD.
发明人： Masumoto, Takahiko , Kimura, Kazuhiro , Kaneko, Hiroshi
IPC分类号： H04H1/00 , H04L25/06
CPC分类号： H04L7/0334 , H04H40/18 , H04H2201/13 , H04L7/0331

10. 发明公开

EP1780931A2 Reception apparatus and method 审中-公开
标题翻译： Empfangsgerätund -verfahren
公开(公告)号：EP1780931A2
公开(公告)日：2007-05-02
申请号：EP07003247.9
申请日：2000-09-14
申请人： Matsushita Electrical Industrial Co., Ltd
发明人： Abe, Katsuaki c/oMatsushita El. Ind.Co.Ltd IPROC , Orihashi,Masayuki c/oMatsushita E. I.Co.Ltd IPROC , Msuya,Job Cleopa c/oMatsushita E. I.Co.Ltd IPROC , Sagawa,Morikazu c/oMatsushita E. Ind.Co.Ltd IPROC , Yoneyama,Masayoshi c/oMatsushita E.I.Co.Ltd IPROC
IPC分类号： H04L7/033
CPC分类号： H04L7/042 , H04L7/0004 , H04L7/007 , H04L7/0334
摘要： A phase of a sampling clock provided from clock generating circuit 107 is switched periodically and alternately with a phase difference of 180 degrees, and during a period of each phase, timing estimating circuit 105 estimates a symbol timing. High-accuracy timing estimating circuit 109 selects an estimated result with higher reliability among symbol timing estimated results obtained in respective periods, thereby enabling estimation of the symbol timing with time resolution twice a sampling period. It is possible to decrease an operation frequency in an A/D conversion circuit even in a system requiring timing synchronization accuracy with high accuracy.
摘要翻译：从时钟发生电路107提供的采样时钟的相位以180度的相位差周期性地交替地切换，并且在每个相位的周期期间，定时估计电路105估计符号定时。高精度定时估计电路109在各周期中获得的符号定时估计结果中选择具有较高可靠性的估计结果，从而能够以采样周期两倍的时间分辨率来估计符号定时。即使在需要高精度的定时同步精度的系统中也可以降低A / D转换电路的工作频率。

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