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1. 发明公开

EP3235135A1 FREQUENCY DIVIDER 审中-公开
标题翻译：频率分配器
公开(公告)号：EP3235135A1
公开(公告)日：2017-10-25
申请号：EP15813506.1
申请日：2015-12-11
申请人： Nordic Semiconductor ASA
发明人： WEBERG, Stein Erik , PIHL, Johnny
IPC分类号： H03L7/193
CPC分类号： H03L7/193
摘要： A variable frequency divider is arranged to divide a frequency of an incoming signal by a variable number D to provide a resultant signal. The arrangement comprises: a first counter 108 having a first clock input and an output undergoing a single cycle for P cycles of the first clock if a first control input is in a first state, or undergoing a single cycle for P+1 cycles of the first clock if the first control input is in a second state; a second counter 110 with a second clock input clocked by the output of the first counter 108 and having a second output undergoing a single cycle for N second clock cycles, wherein N is an integer predetermined by a second control input; and a controller 112 arranged to determine the first and second control inputs such that the first control input is in said second state for a number A of first clock cycles such that D=N•P+A and wherein the controller 112 selects N and A such that the resultant signal has cumulative high and low times which are the same to within half a cycle of said second clock input.
摘要翻译：可变频率分频器装置被设置为将输入信号的频率除以可变数字D以提供结果信号。该装置包括：第一计数器（108），其具有第一时钟输入和第一输出，如果第一控制输入处于第一状态或者经历P + 1个周期的单个周期，则第一输出经历用于所述第一时钟的P个周期的单个周期如果所述第一控制输入处于第二状态，与所述第一计数器（108）串联并且具有第二时钟输入和第二输出的第二计数器（110），所述第二时钟输入和第二输出对于所述第二时钟的每N个周期经历单个周期，其中N是由第二控制输入预定的整数; （112）确定所述第一和第二控制输入，使得所述第一控制输入处于所述第二状态达A个第一时钟周期，使得D = N * P + A，并且其中所述控制器（112）被设置为选择N和A，使得所得到的信号具有在所述第二时钟输入的半个周期内相同的累积高和低时间。

2. 发明公开

EP2668723A1 FREQUENCY DIVIDER WITH SYNCHRONOUS RANGE EXTENSION ACROSS OCTAVE BOUNDARIES 有权
标题翻译：与八度极限同步区域扩展分频器
公开(公告)号：EP2668723A1
公开(公告)日：2013-12-04
申请号：EP12703652.3
申请日：2012-01-24
申请人： Coherent Logix Incorporated
发明人： CAVIN, Mark S.
IPC分类号： H03L7/193 , H03K23/64
CPC分类号： H03L7/193 , G06F1/04 , G06F1/08 , H03K23/667
摘要： A frequency divider based on a series of divide-by-2/3 cells and divide-by-1/2/3 cells using extended division range is disclosed. The frequency divider uses modified divide-by-1/2/3 cells and additional circuit elements to correctly divide an input frequency by a divisor on successive output cycles while the divisor transitions across an octave boundary. The frequency divider creates a divide-by-1 mode for unused divide-by-1/2/3 cells in the series of cells. The divide-by-1 mode passes the input clock in the unused latches of each unused divide-by-1/2/3 cell as opposed to having each unused divide-by-1/2/3 cell implement divide-by-3 mode.

3. 发明公开

EP2351236A2 ELECTRONIC DEVICES FOR COMMUNICATION UTILIZING ENERGY DETECTION AND/OR FREQUENCY SYNTHESIS 审中-公开
标题翻译：适用于通信电子协定的用能检测和/或频率合成
公开(公告)号：EP2351236A2
公开(公告)日：2011-08-03
申请号：EP09745185.0
申请日：2009-10-14
申请人： QUALCOMM Incorporated
发明人： LINSKY, Joel Benjamin , FONG, Gene , SABOURI, Faramarz , YANG, Eugene , ZHAO, Desong , LANE, Mark , CARGILL, Thomas P.
IPC分类号： H04B1/16 , H03L7/02 , H04W52/02
CPC分类号： H04W52/029 , H03L7/183 , H03L7/193 , H03L7/23 , H03L2207/06 , H04W52/0245 , H04W68/00 , Y02D70/142 , Y02D70/144 , Y02D70/164
摘要： An electronic device for communication comprises a processor. The processor comprises a power scan module configured to receive an energy detection signal identifying detection of energy of a page signal or an inquiry signal. The power scan module is further configured to provide, upon receiving the energy detection signal, an instruction to perform a page scan or an inquiry scan.

4. 发明公开

EP2267900A1 High resolution auto-tuning for a voltage controlled oscillator 审中-公开
标题翻译： Hochauflösendeautomatische Abstimmungfüreinen spannungsgesteuerten Oszillator
公开(公告)号：EP2267900A1
公开(公告)日：2010-12-29
申请号：EP10182591.7
申请日：2006-10-13
申请人： Skyworks Solutions, Inc.
发明人： Ripley, David, S , Wang, Hua , Roll, Bryan, J
IPC分类号： H03L7/10 , H03L7/099 , H03L7/187
CPC分类号： H03L7/0992 , H03L7/099 , H03L7/10 , H03L7/18 , H03L7/187 , H03L7/193
摘要： According to one exemplary embodiment, an auto-tuning circuit (104) coupled to a voltage controlled oscillator (102) in a phase locked loop, where the voltage controlled oscillator is coupled to a capacitor array (105), includes a prescaler circuit (106) configured to provide a divided voltage controlled oscillator frequency, where the prescaler circuit is used in the phase locked loop during fine tuning of the voltage controlled oscillator in the auto-tuning circuit during coarse tuning of the voltage controlled oscillator. The auto-tuning circuit further includes a digital processing logic circuit (108) coupled to the prescaler circuit and configured to determine a capacitance of the capacitor array by comparing comp_cnt to a predetermined value, where comp_cnt is determined by a number of cycles of the divided voltage controlled oscillator frequency that occur in a calibration interval.
摘要翻译：根据一个示例性实施例，耦合到锁相环中的压控振荡器（102）的自调谐电路（104），其中压控振荡器耦合到电容器阵列（105），包括预分频器电路（106）），其配置为提供分压控制的振荡器频率，其中在电压控制振荡器的粗调谐期间，在自调谐电路中的压控振荡器的微调时，预分频器电路用于锁相环。自动调谐电路还包括耦合到预分频器电路的数字处理逻辑电路（108），并且被配置为通过将comp_cnt与预定值进行比较来确定电容器阵列的电容，其中comp_cnt由所分割的多个周期确定在校准间隔内发生的压控振荡器频率。

5. 发明授权

EP1671423B1 PHASE-SWITCHING DUAL MODULUS PRESCALER 有权
标题翻译： PHASENUMSCHALT双模预分频器
公开(公告)号：EP1671423B1
公开(公告)日：2008-07-02
申请号：EP04770110.7
申请日：2004-09-28
申请人： NXP B.V.
发明人： LEENAERTS, Dominicus, M., W. , PAVLOVIC, Nenad , MISTRY, Ketan
IPC分类号： H03L7/197 , H03K23/66
CPC分类号： H03K23/667 , H03K23/662 , H03L7/193
摘要： A phase-switching dual modulus prescaler having a dual modulus divider is provided. Said divider comprises a first and second divide-by-2 circuit (A;B), wherein said second divide-by-2 circuit (B) is coupled to the output of said first divide-by-2 circuit (A) and at least said second divide-by-two circuit (B) comprises a four phase output each separated by 90°. A phase selection unit (PSU) is provided for selecting one of the four phase outputs (Ip, In, Qp, Qn; INi, INni, INq, Innq) of the second divide-by-2 circuit (B). Moreover, a phase control unit is provided for providing control signal (Cl, NC0; C2, NC2; C3, NC3) to the phase selection unit, wherein the phase selection unit (PSU) performs the selection of the four phase outputs( Ip, In, Qp, Qn; INi, INni, INq, Innq) according to the control signals (C0, NC0; C1, NC1; C2, NC2). Said phase selection unit (PSU) is implemented based on direct logic. The implementation of the phase selection unit based on direct logic enables a higher speed and saves area on the chip.

6. 发明公开

EP1281237A1 POWER ADAPTIVE FREQUENCY DIVIDER 有权
标题翻译：分频器可变部比例的功耗和调整
公开(公告)号：EP1281237A1
公开(公告)日：2003-02-05
申请号：EP01927915.7
申请日：2001-04-13
申请人： Koninklijke Philips Electronics N.V.
发明人： VAUCHER, Cicero, S. , VEREIJKEN, Hubertus, H., M.
IPC分类号： H03K3/012 , H03K21/38 , H03L7/08 , H03L7/193
CPC分类号： H03K23/66 , H03L7/0802 , H03L7/193
摘要： The power consumption of a frequency divider can effectively be reduced when the frequency of the input signal varies by more than the division factor of a divider cell in the frequency divider. A low frequency input signal requires a lower division factor, and a divider cell in the frequency divider can be bypassed and switched off to obtain this lower division factor, thereby reducing the power consumption.

7. 发明公开

EP0641082A2 PLL frequency synthesizer and PLL frequency synthesizing method capable of obtaining high-speed lock-up and highly-reliable oscillation 失效
标题翻译： PLL-频谱合成和PLL-频谱合成技术在Schwangen和稳定Schwingungen。
公开(公告)号：EP0641082A2
公开(公告)日：1995-03-01
申请号：EP94112984.3
申请日：1994-08-19
申请人： NEC CORPORATION
发明人： Fukuda, Shinri, c/o NEC Corporation
IPC分类号： H03L7/197 , H03L7/087
CPC分类号： H03L7/1972 , H03L7/087 , H03L7/193 , Y10S331/02
摘要： According to an output from a voltage-controlled oscillator (1), there are generated by a fractional divider (2) a high-frequency division signal (S1) and a low-frequency division number (S2). A phase comparison is conducted betwen the high-frequency division signal (S1) and a high-frequency reference signal (REF1) by a phase comparator (5). A phase comparison is carried out between the low-frequency division signal (S2) and a low-frequency reference signal (REF2) by a phase comparator (6). Either one of the outputs from the phase comparators (5 and 6) is selected by a selector (7) to be fed to a filter (8), thereby producing a control voltage (Vc) for the voltage-controlled oscillator (1). A high-resolution division is achieved by the fractional division; consequently, disturbance of the oscillation frequency due to a change-over of the selector (7) is suppressed. There is obtained a PLL frequency synthesizer developing a high-speed lock-up and a highly stable oscillation.
摘要翻译：根据压控振荡器（1）的输出，由小数分频器（2）产生高频分频信号（S1）和低频分频数（S2）。通过相位比较器（5）在高频分频信号（S1）和高频参考信号（REF1）之间进行相位比较。通过相位比较器（6）在低分频信号（S2）和低频参考信号（REF2）之间进行相位比较。来自相位比较器（5和6）的输出中的任何一个由选择器（7）选择以馈送到滤波器（8），从而产生用于压控振荡器（1）的控制电压（Vc）。高分辨率划分是通过分数除法实现的; 因此，抑制了由于选择器（7）的转换引起的振荡频率的干扰。获得了开发高速锁定和高稳定振荡的PLL频率合成器。

8. 发明公开

EP0171162A2 Phase-locked loop frequency synthesiser with a variable modulus prescaler 失效
标题翻译：一种频率合成器与锁相环和定标器的可变模量。
公开(公告)号：EP0171162A2
公开(公告)日：1986-02-12
申请号：EP85304602.7
申请日：1985-06-27
申请人： JOHN FLUKE MFG. CO., INC.
发明人： Cok, Steven Peter , Drucker, Eric Ross
IPC分类号： H03L7/18
CPC分类号： H03L7/193 , H03L7/1974
摘要： A three modulus prescaler for a phase-locked loop frequency synthesizer includes a No modulus prescaler inputting into a divide-by-two circuit. A microprocessor and internal logic control a three modulus prescaler synchronizer to receive signals from the divide-by-two circuit and output control commands to the No modulus prescaler so as to cause the N 0 modulus prescaler to divide solely by a first or second modulus, or alternately between said first and second modulus, between output pulses of the divide-by-two circuit to extend the synthesizer's bandwidth.

9. 发明公开

EP0075591A1 FREQUENCY SYNTHESIZED TRANSCEIVER 失效
标题翻译：用合成频率发送/接收装置。
公开(公告)号：EP0075591A1
公开(公告)日：1983-04-06
申请号：EP82901282.0
申请日：1982-03-30
申请人： MOTOROLA, INC.
发明人： BORRAS, Jaime Andres , GONZALEZ, Ruben Jesus , SMITH, Daniel Martin , WIECZOREK, Alfred Bruno , SUAREZ, Jose Ignacio , VICTOR, Alan Michael , POPEK, Marc Howard
IPC分类号： H03C3 , H03D13 , H03J5 , H03K23 , H03L7 , H04B1
CPC分类号： H03C3/0966 , H03C3/0933 , H03C3/0941 , H03C3/0958 , H03C3/227 , H03D13/005 , H03J5/0281 , H03K23/66 , H03K23/667 , H03L7/0802 , H03L7/193 , H03L7/199 , H04B1/405
摘要： Un emetteur-recepteur a frequence synthetisee peut etre syntonise sur une pluralite de canaux de communication. L'emetteur-recepteur comprend une section receptrice (72) et une section emettrice (74) qui sont couplees au synthetiseur qui genere les signaux d'injection appropries pour effectuer la syntonisation. Le synthetiseur de frequence comprend un commutateur a multipositions (52, 200) qui a acces a diverses adresses de memoires adressables dans une memoire fixe programmable (60) ou les diviseurs appropries sont stockes pour effectuer la syntonisation du synthetiseur sur le canal de communication approprie. Un commutateur selecteur de zone (202) permet un groupement et une recherche aisee des canaux. Les diviseurs sont envoyes dans un compteur d'absorption binaire synchrone simple (46) qui travaille en association avec un predemultiplicateur a module double (44) pour controler la sortie de frequence de l'oscillateur commande par tension (42). Un diviseur programmable (32) couple a une source d'oscillateur de reference (30) est compare a la sortie du compteur synchrone dans un detecteur de phase digitale et analogique (34). Le detecteur de phase (34) envoie des signaux par l'intermediaire d'un filtre a boucle (40) pour appliquer la tension appropriee a l'oscillateur commande par tension (42). Le detecteur de phase (34) comprend des moyens d'avance rapide de l'oscillateur commande par tension pour effectuer la syntonisation de la frequence.

10. 发明公开

EP0045799A4 AN IMPROVED FREQUENCY SYNTHESIZER USING MULTIPLE DUAL MODULUS PRESCALERS. 失效
标题翻译：与不同，以两件式改进的频率合成器可编程的因素预分频器。
公开(公告)号：EP0045799A4
公开(公告)日：1982-07-13
申请号：EP81900769
申请日：1981-01-05
申请人： MOTOROLA INC
发明人： OOMS WILLIAM JAY
IPC分类号： H03L7/18 , H03K23/66 , H03L7/193 , H03L7/197 , H03K21/36
CPC分类号： H03L7/193 , H03K23/667

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