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1. 发明公开

EP3062444A1 PHASE LOCKED LOOP HAVING FRACTIONAL VCO MODULATION 有权转让
标题翻译： PHASENREGELKREIS MIT FRAKTIONIERTER VCO调制
公开(公告)号：EP3062444A1
公开(公告)日：2016-08-31
申请号：EP16155022.3
申请日：2016-02-10
申请人： Freescale Semiconductor, Inc.
发明人： WAHEED, Khurram , TRAYLOR, Kevin B.
IPC分类号： H03L7/197 , H03C3/09
CPC分类号： H03L7/099 , H03B5/124 , H03B5/1265 , H03C3/00 , H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/0958 , H03C3/0975 , H03L7/081 , H03L7/197 , H03M3/422 , H03M7/165
摘要： An integrated circuit comprises a dual port modulator (24) and a voltage controlled oscillator (VCO) (16). The dual port modulator has a first input for receiving a transmitter modulation signal, a first output for providing a fractional portion of a high port modulation signal, a second output for providing a integer portion of the high port modulation signal, and a third output for providing a low port modulation signal. The VCO is coupled to the dual port modulator and has a first input for receiving the fractional portion of the high port modulation signal, a second input for receiving the integer portion of the high port modulation signal, a third input for receiving a tuning signal based on the low port modulation signal, and a first output for outputting an RF signal. The dual port modulator provides a signed single bit signal (s1) for generating the fractional portion of the high port modulation signal.
摘要翻译：集成电路包括双端口调制器（24）和压控振荡器（VCO）（16）。双端口调制器具有用于接收发射机调制信号的第一输入端，用于提供高端口调制信号的小数部分的第一输出端，用于提供高端口调制信号的整数部分的第二输出端和用于提供低端口调制信号。 VCO耦合到双端口调制器，并且具有用于接收高端口调制信号的小数部分的第一输入端，用于接收高端口调制信号的整数部分的第二输入端，用于接收基于调制信号的调谐信号的第三输入端在低端口调制信号上，以及第一输出端用于输出RF信号。双端口调制器提供用于产生高端口调制信号的小数部分的带符号单位信号（s1）。

2. 发明公开

EP1915817A4 DUAL PORT MODULATOR 有权转让
标题翻译：双端口调制器
公开(公告)号：EP1915817A4
公开(公告)日：2011-09-07
申请号：EP06773897
申请日：2006-06-23
申请人： MOTOROLA SOLUTIONS INC
发明人： CHAN EVELYN L , MOKHTAR FUAD HAJI , LIM ANNYEN
IPC分类号： H03C3/06 , H03C3/09 , H03C3/22
CPC分类号： H03C3/0925 , H03C3/08 , H03C3/0933 , H03C3/0941 , H03C3/0958 , H03C3/0975 , H03C3/20

3. 发明授权

EP1345375B1 Method and apparatus for frequency modulation 有权
标题翻译：对频率调制的方法和装置
公开(公告)号：EP1345375B1
公开(公告)日：2010-09-01
申请号：EP03005251.8
申请日：2003-03-10
申请人： Panasonic Corporation
发明人： Adachi, Hisashi , Sakakura, Makoto
IPC分类号： H04L27/12 , H03C3/09
CPC分类号： H03C3/0966 , H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/095 , H03C3/0958 , H03L7/1976 , H03M7/3022 , H03M7/3037 , H03M7/304 , H04L27/12

4. 发明授权

EP1612931B1 Circuit for driving a voltage controlled oscillator for frequency modulation 有权
标题翻译：电路用于驱动spannungsgesteurten振荡器频率调制
公开(公告)号：EP1612931B1
公开(公告)日：2009-08-05
申请号：EP05253397.3
申请日：2005-06-02
申请人： Micrel, Inc.
发明人： Pettersen, Fred-Johan , Eide, Petter
IPC分类号： H03C3/08 , H03C3/09 , H03C3/22 , H03L7/099
CPC分类号： H03L7/099 , H03C3/0958 , H03L2207/06

5. 发明授权

EP1485989B8 OSCILLATOR AND PLL CIRCUIT USING THE SAME 有权
标题翻译：振荡器和PLL电路
公开(公告)号：EP1485989B8
公开(公告)日：2007-10-10
申请号：EP03719331.5
申请日：2003-02-25
申请人： SONY ELECTRONICS, INC.
发明人： KATAKURA, Masayuki , KOMATSU, Yoshihiro , HIROMOTO, Kenji , KOUSAKA, Tsuyoshi , FAI BEN, Li, Ping
IPC分类号： H03B5/24 , H03B5/04 , H03L1/00 , H03L7/099 , H03C3/09 , H03K3/03
CPC分类号： H03C3/095 , H03C3/0958 , H03K3/0315 , H03L7/0995 , H03L7/18
摘要： An oscillator (1083) having a modulation function capable of controlling a frequency by adding a signal to a control signal and a PLL (108A) circuit using the same, wherein the oscillator forms a ring (200) comprised of a plurality of cascade connected delay stages (201-203) controlled in delay value by an inverter or a buffer and a control signal and forming a closed loop by an inverted phase and comprises a modulation function modulating an oscillation frequency by adding a modulation signal to the control signal in a part of the plurality of delay stages.

6. 发明授权

EP1032988B1 APPARATUS FOR LOW POWER RADIO COMMUNICATIONS 失效
标题翻译：设备对低强度无线通信
公开(公告)号：EP1032988B1
公开(公告)日：2006-05-03
申请号：EP98967173.0
申请日：1998-07-21
申请人： Cleveland Medical Devices, Inc.
发明人： DACUS, Farron, L. , SCHMIDT, Robert, N. , HENDRIX, Steven, P.
IPC分类号： H04B7/26 , H03J7/04 , H03C3/09 , H03L7/14 , H04B1/04
CPC分类号： H03C3/0958 , H03C3/095 , H03J7/04 , H03L7/0802 , H03L7/14 , H04W52/028
摘要： An apparatus for low power radio communication comprising a transmitter having a frequency synthesizer and transmit antenna such that the frequency synthesizer comprises a phase locked loop circuit with a voltage controlled oscillator having a variable frequency output and with a loop filter/sample and hold circuit that allows opening of the synthesizer control loop and with special means of limiting the resulting frequency drift in the open loop state. The transmitter produces an output signal and the loop filter/sample and hold circuit holds the voltage controlled oscillator substantially on frequency such that the output signal remains stable, with a minimum of frequency drift, over a period of time when the phase lock loop synthesizer is set to an open loop state to allow frequency modulation unimpeded by the normal frequency correcting action of the synthesizer and for the frequency synthesizer to be partially powered down to reduce power consumption. The frequency modulation is linearized over a band of interest and undesired frequency shift at the initiation of modulation is suppressed. Receiver having automatic frequency control is included to extend the open loop transmit time of the transmitter, where the automatic frequency control system automatically tunes the receiver to correct for frequency error and for the frequency drift resulting from opening the phase locked loop of the frequency synthesizer, allowing communications to continue in the presence of such drift and of other frequency error.

7. 发明公开

EP1318598A1 Modulator unter Verwendung eines Phasenregelkreises und Verfahren dazu 有权
标题翻译：调制解调器Verwendung eines Phasenregelkreises und Verfahren dazu
公开(公告)号：EP1318598A1
公开(公告)日：2003-06-11
申请号：EP01811194.8
申请日：2001-12-07
申请人： Ascom AG
发明人： Bolliger, Urs
IPC分类号： H03C3/09
CPC分类号： H03C3/0958 , H03C3/095
摘要： Der Phasenregelkreis weist einen Nachlaufoszillator (VCO) auf, dessen Ausgangssignal f out , das bei geöffnetem Regelkreis modulierbar ist, in einem Phasendetektor (PD) mit einem Referenzsignal f ref verglichen wird, dessen Ausgangssignal uϕ über einen der Öffnung des Regelkreises dienenden Schalter (SW) sowie ein Schleifenfilter (LF) einem ersten Eingang in tune des Nachlaufoszillators (VCO) zuführbar ist. Erfindungsgemäss ist eine Kompensationseinheit (CMP) vorgesehen, von der dem Schleifenfilter (LF) oder dem Nachlaufoszillator (VCO) ein Kompensationssignal s cmp zuführbar ist, durch das bei geöffnetem Regelkreis auftretende Signalverschiebungen kompensierbar sind. Der Phasenregelkreis kann daher derart gestaltet werden, dass erzeugte Trägerfrequenzen schneller umschaltbar sind und eingestellte Trägerfrequenzen bei geöffnetem Regelkreis eine höhere Stabilität aufweisen. Der Phasenregelkreis ist daher insbesondere in Kommunikationsgeräten vorteilhaft einsetzbar, in denen Mehrfachzugriffsverfahren TDMA, FDMA angewendet werden, die rasche Umschaltungen und stabile Einstellungen von Trägerfrequenzen erfordern.
摘要翻译：锁相环包括压控振荡器，相位检测器和环路滤波器。补偿单元（CMP）从环路滤波器或压控振荡器接收补偿信号，用于补偿当开关（SW）打开控制回路时发生的信号偏移。以下也包括独立权利要求：（1）操作锁相环的方法，以及（2）通信终端。

8. 发明公开

EP1032988A1 APPARATUS FOR LOW POWER RADIO COMMUNICATIONS 失效
标题翻译：设备对低强度无线通信
公开(公告)号：EP1032988A1
公开(公告)日：2000-09-06
申请号：EP98967173.0
申请日：1998-07-21
申请人： Cleveland Medical Devices, Inc.
发明人： DACUS, Farron, L. , SCHMIDT, Robert, N. , HENDRIX, Steven, P.
IPC分类号： H04B7/26
CPC分类号： H03C3/0958 , H03C3/095 , H03J7/04 , H03L7/0802 , H03L7/14 , H04W52/028
摘要： An apparatus for low power radio communication comprising a transmitter having a frequency synthesizer and transmit antenna such that the frequency synthesizer comprises a phase locked loop circuit with a voltage controlled oscillator having a variable frequency output and with a loop filter/sample and hold circuit that allows opening of the synthesizer control loop and with special means of limiting the resulting frequency drift in the open loop state. The transmitter produces an output signal and the loop filter/sample and hold circuit holds the voltage controlled oscillator substantially on frequency such that the output signal remains stable, with a minimum of frequency drift, over a period of time when the phase lock loop synthesizer is set to an open loop state to allow frequency modulation unimpeded by the normal frequency correcting action of the synthesizer and for the frequency synthesizer to be partially powered down to reduce power consumption. The frequency modulation is linearized over a band of interest and undesired frequency shift at the initiation of modulation is suppressed. Receiver having automatic frequency control is included to extend the open loop transmit time of the transmitter, where the automatic frequency control system automatically tunes the receiver to correct for frequency error and for the frequency drift resulting from opening the phase locked loop of the frequency synthesizer, allowing communications to continue in the presence of such drift and of other frequency error.

9. 发明授权

EP0215651B1 A circuit including a DC-FM phase locked loop 失效
标题翻译：包括DC-FM相位锁定环路的电路
公开(公告)号：EP0215651B1
公开(公告)日：1992-06-17
申请号：EP86307046.2
申请日：1986-09-12
申请人： SCHLUMBERGER MESSGERÄTE GMBH
发明人： Schutz, Johann
IPC分类号： H03C3/09
CPC分类号： H03C3/0966 , H03C3/0941 , H03C3/0958

10. 发明公开

EP0403492A1 BANDSWITCHING A TWO-WAY RADIO HAVING A PLL 失效
标题翻译：与PLL A双向无线电设备的频段切换。
公开(公告)号：EP0403492A1
公开(公告)日：1990-12-27
申请号：EP89901792.0
申请日：1989-01-05
申请人： MOTOROLA, INC.
发明人： HANSEN, Kenneth, Adolph , ENDERBY, Ralph, Thomas
IPC分类号： H04B1 , H03C3 , H03J5
CPC分类号： H03C3/0966 , H03C3/0941 , H03C3/0958 , H03J5/0272 , H03J5/242 , H04B1/16
摘要： Le procédé et l'agencement décrits, qui servent à commuter électroniquement la gamme d'ondes d'une radio (100), utilisent au moins un récepteur (110, 111), une boucle à verrouillage de phase (120), ainsi qu'un compteur programmable totalement synchronisé qui sert de diviseur de fréquence (140) et qui est couplé entre le récepteur et la boucle à verrouillage de phase. La boucle à verrouillage de phase comporte au moins un générateur de signal de référence (121, 122), un détecteur de phase (124) et un oscillateur commandé par tension (127) comportant une sortie (129) couplée, via un circuit de retour, à une seconde entrée (131) du détecteur de phase (124). La forme et la disposition du diviseur de fréquence programmable totalement synchronisé (140) sont conçues pour qu'ils fournissent un signal de sortie (143) ayant un cycle de travail, presque égal à 50 %, qui est indépendant d'un diviseur et qui simplifie les tâches de filtrage en aval, assurant ainsi une commutation électronique de la gamme d'ondes pour la radio tout en présentant des caractéristiques de verrouillage rapide et de bruit faible.

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