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1. 发明授权

EP3152636B1 CLOCK SWALLOWING APPARATUS AND METHOD FOR REDUCING VOLTAGE NOISE 有权
标题翻译：时钟消除装置和用于降低电压噪声的方法
公开(公告)号：EP3152636B1
公开(公告)日：2017-09-27
申请号：EP15726833.5
申请日：2015-05-18
申请人： Qualcomm Incorporated
发明人： COUTTS, Ryan Michael , PAL, Dipti Ranjan
IPC分类号： G06F1/08 , G06F1/20 , G06F1/32
CPC分类号： G06F1/08 , G06F1/206 , G06F1/324 , H03K21/026 , H03K23/662 , H03L1/022 , Y02D10/126 , Y02D10/16
摘要： Systems and methods for controlling a frequency of a clock signal by selectively swallowing pulses in the clock signal are described herein. In one embodiment, a method for adjusting a frequency of a clock signal comprises receiving the clock signal, and swallowing pulses in the clock signal according to a repeating clock-swallowing pattern, wherein the pattern is defined by a sequence of numbers.
摘要翻译：本文描述了通过选择性地吞服时钟信号中的脉冲来控制时钟信号的频率的系统和方法。在一个实施例中，一种用于调整时钟信号的频率的方法包括：接收时钟信号;以及根据重复的时钟吞咽模式吞服时钟信号中的脉冲，其中该模式由一系列数字限定。

2. 发明授权

EP0249128B1 TTL technology digital timing unit 失效
标题翻译： TTL技术数字时序单元
公开(公告)号：EP0249128B1
公开(公告)日：1992-09-09
申请号：EP87107952.1
申请日：1987-06-02
申请人： BULL HN INFORMATION SYSTEMS ITALIA S.p.A.
发明人： Zulian, Ferruccio
IPC分类号： G06F1/04
CPC分类号： H03K23/662 , G06F1/06 , H03K23/68

3. 发明公开

EP0189744A1 Diviseur de fréquences 失效
标题翻译： Frequenzteiler。
公开(公告)号：EP0189744A1
公开(公告)日：1986-08-06
申请号：EP86100023.0
申请日：1986-01-02
申请人： ALCATEL, Société Anonyme dite:
发明人： Borgne, Eric , Niquel, Maurice
IPC分类号： H03K23/54
CPC分类号： H03K23/662 , H03K23/54
摘要： L'invention concerne un diviseur de fréquences comportant un nombre déterminé (n) de bistables (B1 à Bn) dans lequel la sortie Q de chaque bistable (B1 à Bn-1) est connectée à l'entrée (D) du bistable (B2 à Bn) de rang suivant, la sortie (Qn) du dernier bistable (Bn) étant connectée à l'entrée (D1) du premier bistable (B1). La sortie (Qn) du dernier bistable (Bn) est connectée par une ligne à retard (τ) à l'entrée de forçage (R) du premier bistable (B1).
摘要翻译：本发明涉及一种分频器，其包括指定数量（n）个触发器（B1至Bn），其中每个触发器（B1至Bn-1）的输出Q连接到触发器（B2至Bn），下一个触发器（Bn）的输出（Qn）连接到第一触发器（B1）的输入端（D1）。最后一个触发器（Bn）的输出（Qn）经由具有延迟（τ）的线连接到第一触发器（B1）的设置输入（R）。

4. 发明公开

EP2506438A1 METHOD AND DEVICE FOR GENERATING LOW-JITTER CLOCK 审中-公开
标题翻译： VERFAHREN UND VORRICHTUNG ZUR ERZEUGUNG EINER UHR MIT GERINGEM FLIMMERN
公开(公告)号：EP2506438A1
公开(公告)日：2012-10-03
申请号：EP10832656.2
申请日：2010-11-24
申请人： ZTE Corporation
发明人： ZHOU, Chang
IPC分类号： H03K23/00
CPC分类号： G06F1/04 , H03K23/662
摘要： The present invention discloses a method for generating a low-jitter clock, including: inserting a time delay in each low-speed clock period to finely adjust a high-speed clock, and then performing frequency division operation on the adjusted high-speed clock to obtain the required low-speed clock. The present invention also discloses an apparatus for generating the low-jitter clock at the same time. By using the method and the apparatus, the jitter of the low-speed clock can be decreased. The implementation method is simple and convenient and the device cost is saved.
摘要翻译：本发明公开了一种生成低抖动时钟的方法，包括：在每个低速时钟周期内插入时间延迟以精细调整高速时钟，然后对经调整的高速时钟进行分频运算获得所需的低速时钟。本发明还公开了一种用于同时产生低抖动时钟的装置。通过使用该方法和装置，可以降低低速时钟的抖动。实现方法简单方便，节省设备成本。

5. 发明授权

EP1603243B1 Prescaling stage for high frequency applications 有权
标题翻译： Vorteilerstufe高频应用
公开(公告)号：EP1603243B1
公开(公告)日：2010-04-28
申请号：EP04425401.9
申请日：2004-05-31
申请人： STMicroelectronics Srl
发明人： Copani, Tino , Smerzi, Santo Alessandro , Girlando, Giovanni , Palmisano, Giuseppe
IPC分类号： H03K23/66
CPC分类号： H03K23/662

6. 发明公开

EP1748560A1 Frequency divider for generating an output signal having fifty percent duty cycle 审中-公开
标题翻译：分频器用于产生与百分之五十脉冲间歇比的输出信号
公开(公告)号：EP1748560A1
公开(公告)日：2007-01-31
申请号：EP05106809.6
申请日：2005-07-25
申请人： Harris Broadcast Systems Europe
发明人： Poppa, Heinz
IPC分类号： H03K23/66 , H03K21/02 , H03B21/01
CPC分类号： H03B21/02 , H03K21/026 , H03K23/662
摘要： The invention relates to a frequency divider (1), in particular for radio frequency (RF) applications, wherein the division ratio can be expressed by an ― preferably odd numbered ― integer divisor. The frequency divider (1) comprises an input circuit (10), which receives an input signal (5) as well as a first output signal (25). The input circuit (10) generates an intermediate signal (15), which has at least one main spectral component whose frequency corresponds to the sum or the difference of frequencies of said main spectral components of said input (5) and first output signal (25). Further, the frequency divider (1) of the invention has an output circuit (20), which receives said intermediate signal (15) and generates said first output signal (25). The main spectral component of said first output signal (25) has a frequency corresponding to the frequency of the main spectral component of said intermediate signal (15) divided by a - preferably even numbered ― integer. Particularly preferred this even numbered integer is 4.
摘要翻译：本发明涉及到一个分频器（1），特别是用于射频（RF）应用中，worin分频比可通过在€•中过表达优选奇数€•整数除数。分频器（1）包括到输入电路（10），输入信号（5），以及一个第一输出信号（25）的接收。所述输入电路（10）生成的中间信号（15），其具有至少一个主光谱分量，其频率对应于总和或所述的频率之差的速率，所述输入（5）和第一输出信号的主频谱分量（25 ）。此外，本发明的分频器（1）具有接收所述中间信号（15）和基因率，所述输出电路（20），第一输出信号（25）。所述第一输出信号（25）的主频谱分量具有由划分一个频率对应于所述中间信号（15）的主频谱分量的频率 - 优选偶数€•完整性。特别优选的此偶数整数第四

7. 发明公开

EP1626501A4 VARIABLE DIVISION METHOD AND VARIABLE DIVIDER 有权
标题翻译：可变分割方法和可变分频器
公开(公告)号：EP1626501A4
公开(公告)日：2006-08-02
申请号：EP04733432
申请日：2004-05-17
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： HARADA MITSURU , YAMAGISHI AKIHIRO
IPC分类号： H03K23/66
CPC分类号： H03K23/667 , H03K23/662
摘要： A feedback path (307) is formed between an output (310c) of a fixed divider (305) and a control terminal (310b) of a reverse/non-reverse device (304). A connection device (306) is arranged on the feedback path (307). The feedback path (307) is connected/disconnected according to the level of the control signal M from outside, thereby switching the number of divisions. The delay time of the signal given to the input terminal (310a) of the reverse/non-reverse device (304) to pass through the feedback path (307) and return to the control terminal (310b) is set greater than the pulse width of the input clock signal. A small pulse input invalidating function is provided in the fixed divider (305). Alternatively, a small pulse output prohibiting function is provided in the reverse/non-reverse device (304). The fixed divider (305) divides the clock signal before division from the reverse/non-reverse device (304) according to the rise edge of the clock pulse of the normal pulse width in the signal (a change point corresponding to the rise edge of the input clock signal).

8. 发明公开

EP1671423A1 PHASE-SWITCHING DUAL MODULUS PRESCALER 有权
标题翻译： PHASENUMSCHALT双模预分频器
公开(公告)号：EP1671423A1
公开(公告)日：2006-06-21
申请号：EP04770110.7
申请日：2004-09-28
申请人： Koninklijke Philips Electronics N.V.
发明人： LEENAERTS, Dominicus, M., W. , PAVLOVIC, Nenad , MISTRY, Ketan
IPC分类号： H03L7/197 , H03K23/66
CPC分类号： H03K23/667 , H03K23/662 , H03L7/193
摘要： A phase-switching dual modulus prescaler having a dual modulus divider is provided. Said divider comprises a first and second divide-by-2 circuit (A;B), wherein said second divide-by-2 circuit (B) is coupled to the output of said first divide-by-2 circuit (A) and at least said second divide-by-two circuit (B) comprises a four phase output each separated by 90°. A phase selection unit (PSU) is provided for selecting one of the four phase outputs (Ip, In, Qp, Qn; INi, INni, INq, Innq) of the second divide-by-2 circuit (B). Moreover, a phase control unit is provided for providing control signal (Cl, NC0; C2, NC2; C3, NC3) to the phase selection unit, wherein the phase selection unit (PSU) performs the selection of the four phase outputs( Ip, In, Qp, Qn; INi, INni, INq, Innq) according to the control signals (C0, NC0; C1, NC1; C2, NC2). Said phase selection unit (PSU) is implemented based on direct logic. The implementation of the phase selection unit based on direct logic enables a higher speed and saves area on the chip.

9. 发明公开

EP1626501A1 VARIABLE DIVISION METHOD AND VARIABLE DIVIDER 有权
标题翻译：变量分割法和变量分割器
公开(公告)号：EP1626501A1
公开(公告)日：2006-02-15
申请号：EP04733432.1
申请日：2004-05-17
申请人： NIPPON TELEGRAPH AND TELEPHONE CORPORATION
发明人： HARADA, Mitsuru NTT Intellectual Property Center , YAMAGISHI, Akihiro NTT Int. Property Center
IPC分类号： H03K23/00
CPC分类号： H03K23/667 , H03K23/662
摘要： A feedback path (307) is formed between an output (310c) of a fixed divider (305) and a control terminal (310b) of an inverting/noninverting unit (304). A connection device (306) is arranged on the feedback path (307). The feedback path (307) is connected/disconnected according to the level of the control signal M from outside, thereby switching the number of divisions. The delay time of the signal given to the input terminal (310a) of the inverting/noninverting unit (304) to pass through the feedback path (307) and return to the control terminal (310b) is set greater than the pulse width of the input clock signal. A small pulse input invalidating function is provided in the fixed divider (305). Alternatively, a small pulse output prohibiting function is provided in the inverting/noninverting unit (304). The fixed divider (305) divides the clock signal before division from the inverting/noninverting unit (304) according to the leading edge of the clock pulse of the normal pulse width in the signal (a change point corresponding to the leading edge of the input clock signal).
摘要翻译：反馈路径（307）形成在固定分频器（305）的输出（310c）和反相/非反相单元（304）的控制端子（310b）之间。连接装置（306）被布置在反馈路径（307）上。反馈路径（307）根据来自外部的控制信号M的电平进行连接/断开，从而切换分割数。赋予反相/非反相单元（304）的输入端（310a）以通过反馈路径（307）并返回到控制端（310b）的信号的延迟时间设置为大于输入时钟信号。在固定分频器（305）中提供小脉冲输入无效功能。或者，在反相/非反相单元（304）中设置小脉冲输出禁止功能。固定分频器（305）根据信号中的正常脉冲宽度的时钟脉冲的前沿（与输入的前沿相对应的变化点）将来自反相/同相单元（304）的分频之前的时钟信号分频时钟信号）。

10. 发明公开

EP0446527A3 Method and circuit for controlling the frequency of an electronic inverter 失效
标题翻译：用于控制电子逆变器频率的方法和电路
公开(公告)号：EP0446527A3
公开(公告)日：1991-10-23
申请号：EP90313709.9
申请日：1990-12-14
申请人： SUNDSTRAND CORPORATION
发明人： Kessler, Leland Louis , Fox, David Alan , Jones, Kevin Michael
IPC分类号： H03K5/156 , H03K23/66 , H03L7/18
CPC分类号： H03B23/00 , H03B2200/0092 , H03K5/156 , H03K23/662
摘要： A method for modifying the frequency of a clock signal includes the steps of producing a clock signal having voltage pulses which occur at a first frequency and producing a control signal having voltage pulses which occur at a lower frequency. The frequency of the voltage pulses in the control signal is incremented in successive time intervals and the clock signal and control signal are combined such that one voltage pulse in the clock signal is deleted for each voltage pulse in the control signal. This results in a modified clock signal having a frequency which may be ramped up or down depending upon the initial frequency of the control signal and the direction in which, the frequency of the control signal is incremented.

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