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1. 发明授权

EP0044156B1 Phase-locked loop frequency synthesizer 失效
标题翻译：相位锁定频率合成器
公开(公告)号：EP0044156B1
公开(公告)日：1984-10-31
申请号：EP81302908.9
申请日：1981-06-26
申请人： JOHN FLUKE MFG. CO., INC.
发明人： Erps, Floyd D. , Fried, Raymond L.
IPC分类号： H03L7/22 , H03B21/02 , H03K21/36
CPC分类号： H03K23/665 , H03K23/667 , H03L7/185

2. 发明授权

EP0011164B1 Digitale Frequenzteileranordnung 有权
标题翻译：数字频率分路电路
公开(公告)号：EP0011164B1
公开(公告)日：1983-03-02
申请号：EP79104145.2
申请日：1979-10-25
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Sonntag, Fritz, Dipl.-Ing.
IPC分类号： H03K23/00 , H03K21/36 , H04J1/06
CPC分类号： H03K23/00 , H03K23/662 , H04J1/06

3. 发明公开

EP0045799A4 AN IMPROVED FREQUENCY SYNTHESIZER USING MULTIPLE DUAL MODULUS PRESCALERS. 失效
标题翻译：与不同，以两件式改进的频率合成器可编程的因素预分频器。
公开(公告)号：EP0045799A4
公开(公告)日：1982-07-13
申请号：EP81900769
申请日：1981-01-05
申请人： MOTOROLA INC
发明人： OOMS WILLIAM JAY
IPC分类号： H03L7/18 , H03K23/66 , H03L7/193 , H03L7/197 , H03K21/36
CPC分类号： H03L7/193 , H03K23/667

4. 发明授权

EP0009438B1 Elément de mémoire dynamique à transfert de charges, et application notamment à un registre à décalage 失效
标题翻译：动态电荷转移记忆元件及其应用，特别适用于移位寄存器
公开(公告)号：EP0009438B1
公开(公告)日：1983-09-21
申请号：EP79400633.8
申请日：1979-09-10
申请人： THOMSON-CSF
发明人： Berger, Jean-Luc
IPC分类号： G11C11/34 , G11C19/28 , H01L27/10 , H03K21/36
CPC分类号： H03K23/66 , G11C11/35 , G11C19/285 , H01L27/1057

5. 发明公开

EP0045800A4 IMPROVED DIVIDER WITH DUAL MODULUS PRESCALER. 失效
标题翻译：带两剖分改进PIECE因素可编程预分频器。
公开(公告)号：EP0045800A4
公开(公告)日：1982-07-13
申请号：EP81900770
申请日：1981-01-05
申请人： MOTOROLA INC
发明人： OOMS WILLIAM JAY , BARNETT RICHARD EDWARD
IPC分类号： H03L7/18 , H03K23/66 , H03K21/36
CPC分类号： H03K23/667

6. 发明公开

EP0030857A3 Programmable counter circuit 失效
标题翻译：可编程计数器电路
公开(公告)号：EP0030857A3
公开(公告)日：1981-10-21
申请号：EP80304498
申请日：1980-12-12
申请人： FUJITSU LIMITED
发明人： Asami, Fumitaka , Takagi, Osamu
IPC分类号： H03K21/32 , H03K21/36 , H03K23/30
CPC分类号： H03K23/665 , H03K3/356104
摘要： Load terminals of flip-flops P D1 to P D12 of respective stages of an N step counter are cascade-connected via buffers BUF and a load signal LOAD is applied to the load terminals from a load signal generator circuit LDG. The load signal generator circuit LDG has a detector DET for detecting a specific count value which occurs a little before initial value loading of the flip-flop stages of the counter circuit is to be begun. A shift register SHR receives a detection output of the detector DET and the detection output is shifted through the stages of the shift register SHR independence upon clock signals the same as those used for driving the counter circuit. The detection output is delivered from the shift register SHR as a load signal LOAD at the moment at which initial value loading is to be begun. For the duration of the load signal LOAD and a selected period of time subsequent thereto a load control circuit LCT inhibits the application of a detection output from the detector DET to the shift register SHR, thus preventing erroneous loading.

7. 发明授权

EP0031638B1 A logic circuit 失效
标题翻译：逻辑电路
公开(公告)号：EP0031638B1
公开(公告)日：1984-10-03
申请号：EP80303960.1
申请日：1980-11-06
申请人： FUJITSU LIMITED
发明人： Sugihara, Takanori , Yoshida, Makoto
IPC分类号： H03K21/36 , H03K23/00 , G11C19/00
CPC分类号： H03K23/54 , G11C19/00

8. 发明公开

EP0044156A1 Phase-locked loop frequency synthesizer 失效
标题翻译：频率合成锁相环。
公开(公告)号：EP0044156A1
公开(公告)日：1982-01-20
申请号：EP81302908.9
申请日：1981-06-26
申请人： JOHN FLUKE MFG. CO., INC.
发明人： Erps, Floyd D. , Fried, Raymond L.
IPC分类号： H03L7/22 , H03B21/02 , H03K21/36
CPC分类号： H03K23/665 , H03K23/667 , H03L7/185
摘要： A programmable divide-by-N phase-locked loop having a pulse incrementor circuit (12) and a single sideband mixer circuit (14) embedded in the loop feedback path is disclosed. In each disclosed arrangement, one input port of the single sideband mixer (14) receives the signals supplied by the phase-locked loop voltage-controlled oscillator (16) and, depending upon whether the mixer employed is configured for supplying an upper sideband signal or a lower sideband signal, either increases or decreases the frequency of the phase-locked loop feedback signal by a factor fs, where f s is the frequency of a control signal applied to the second input port of the single sideband mixer (14). The pulse incrementor circuit (12) receives the signal supplied by the single sideband mixer (14) and, depending on whether the pulse incrementor (12) is configured for deleting signal pulses or adding signal pulses, either decreases or increases the average frequency of the signals supplied to the phase-locked loop programmable divider by a factor f d , where f d is the frequency of a control signal applied to the pulse incrementor Since the phase-locked loop synchronizes or locks when the phase of the signal supplied by the programmable divider is equal to the phase of a reference frequency f" which is supplied to the phase-locked loop phase detector, the arrangement causes the phase-locked loop voltage-controlled oscillator to supply a signal at a frequency of Nf r ±fd±f s , where N is the selected divisor of the phase-locked loop programmable divider and the operations of addition and subtraction are determined by the type of single sideband mixer and pulse incrementor utilized. To suppress spurious output signals, both control frequencies f d and f s are maintained substantially above the phase-locked loop cutoff frequency.

9. 发明公开

EP0020764A4 SEQUENCE CONTROL SYSTEM. 失效
标题翻译：过程控制装置。
公开(公告)号：EP0020764A4
公开(公告)日：1981-05-15
申请号：EP78900237
申请日：1980-04-22
申请人： KUZE YOSHIKAZU
发明人： KUZE YOSHIKAZU
IPC分类号： G05B19/045 , G05B19/10 , G05B19/04 , G04F3/00 , H03K17/28 , H03K21/36
CPC分类号： G05B19/045 , G05B19/102 , G05B19/104
摘要： This sequence control system divides data of a time-chart into "l" datum (hereinafter referred to as "black dot") and "0" datum (hereinafter referred to as "white dot"), and is capable of programing parallel-output data of about 16 figures (this is an approximate standard) in an inner memory within 2-3 minutes by only being operated some black dot and white dot key switches by anybody and also of changing the program in about 10 seconds per line. The data is outputted by only presetting a cycle-time and putting a start switch. The present sequence control system is light, compact such as a palm of hand and cheap, so that it might contribute for automation and elimination of labor of every system used in the industrial field from small enterprises to large ones.

10. 发明公开

EP0019412A1 A method of synthesizing an output frequency and circuit arrangement therefor 失效
标题翻译： Verfahren zur Ausgangsfrequenzsynthese und Schaltungsanordnung dazu。
公开(公告)号：EP0019412A1
公开(公告)日：1980-11-26
申请号：EP80301485.1
申请日：1980-05-07
申请人： THE MARCONI COMPANY LIMITED
发明人： Sosin, Boleslaw Marian
IPC分类号： H03L7/18 , H03B21/02 , H03K21/36
CPC分类号： H03L7/1978 , H03B21/025 , H03K23/662 , H03L7/23
摘要： A frequency synthesiser receives a sequence of digital pulses (Fq) and provides as an output a lower frequency consisting of a slightly irregular sequence of pulses. The synthesiser divides the received frequency by a non-integral value by arranging for a variable frequency divider (5) to divide the received sequence of pulses and by periodically removing the received pulses prior to division so as to in effect, temporarily alter the division ratio.
摘要翻译：频率合成器接收数字脉冲序列（Fq）并提供由稍微不规则的脉冲序列组成的较低频率的输出。合成器通过排列可变分频器（5）来分配接收的脉冲序列，并通过在分割之前周期性地去除接收到的脉冲，从而将接收频率除以非积分值，从而实际上暂时改变分频比。

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