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1. 发明授权

EP3179260B1 APPARATUS AND METHOD FOR MONITORING PERFORMANCE OF INTEGRATED CIRCUIT 有权
公开(公告)号：EP3179260B1
公开(公告)日：2018-09-26
申请号：EP15199266.6
申请日：2015-12-10
申请人： Stichting IMEC Nederland
发明人： STUIJT, Jan
IPC分类号： G01R31/30 , G01R31/317 , H02M3/00 , G01R31/28 , G05F1/10 , H03K5/19 , H03K5/00
CPC分类号： H03K5/19 , G01R31/2882 , G01R31/3016 , G01R31/31725 , G05F1/10 , H03K2005/00019
摘要： The present invention discloses an apparatus and method for monitoring performance of an integrated circuit. The apparatus (10) comprises: a delay line (30), which receives a pulse signal, wherein the delay line (30) has a controllable, variable length and propagates the pulse signal through a set length; a comparator (40), which receives the propagated pulse signal from the delay line (30) and a clock signal, said comparator (40) being arranged to determine whether the received signal is received early or late; and a feedback loop (50; 150), which receives input from the comparator (40) for dynamically increasing or decreasing the set length of the delay line (30) in dependence of the determination by the comparator (40); wherein said apparatus (10) determines a speed of the integrated circuit based on a determination by the comparator (40) that the signal from the delay line (30) closely matches the clock signal.

2. 发明公开

EP2980803A1 DELAY CIRCUIT, ELECTRONIC CIRCUIT USING DELAY CIRCUIT AND ULTRASONIC IMAGING DEVICE 有权转让
标题翻译： VERZÖGERUNGSSCHALTUNG，ELEKTRONISCHE SCHALTUNG MIT EINERVERZÖGERUNGSSCHALTUNGUND ULTRASCHALLBILDGEBUNGSVORRICHTUNG
公开(公告)号：EP2980803A1
公开(公告)日：2016-02-03
申请号：EP13879941.6
申请日：2013-03-28
申请人： Hitachi, Ltd.
发明人： NAKAGAWA Tatsuo
IPC分类号： G11C27/00 , A61B8/00 , H03H11/26 , H03H19/00
CPC分类号： H03K5/133 , A61B8/4494 , A61B8/54 , G01S7/52025 , G01S7/5208 , G01S15/8927 , G10K11/346 , G11C27/00 , G11C27/024 , H03H11/265 , H03H19/00 , H03K2005/00019
摘要： A delay circuit and an ultrasonic imaging apparatus with the higher-accuracy delay time, the longer maximum delay time, and the lower power consumption are provided. An input line to which an analog input signal is input, a plurality of analog signal memory devices, an output line, a plurality of sampling switches that control connection/disconnection between the input line and the plurality of analog signal memory devices, a plurality of output switches that control connection/disconnection between the plurality of analog signal memory devices and the output line, and a clock generation part that generates sampling switch control signals for controlling the sampling switches and output switch control signals for controlling the output switches are provided, and phase of the sampling switch control signals may be shifted with respect to phase of the output switch control signals.
摘要翻译：提供具有更高精度的延迟时间，更长的最大延迟时间和更低的功耗的延迟电路和超声成像设备。输入模拟输入信号的输入线，多个模拟信号存储装置，输出线，控制输入线与多个模拟信号存储装置之间的连接/断开的多个采样开关，多个提供了控制多个模拟信号存储装置与输出线之间的连接/断开的输出开关，以及产生用于控制采样开关的采样开关控制信号和用于控制输出开关的输出开关控制信号的时钟产生部分，采样开关控制信号的相位可以相对于输出开关控制信号的相位移动。

3. 发明授权

EP0929901B1 MEMORY ARRAY, MEMORY CELL, AND SENSE AMPLIFIER TEST AND CHARACTERIZATION 失效
标题翻译：测试和表征存储矩阵，存储单元和读出放大器的
公开(公告)号：EP0929901B1
公开(公告)日：2001-11-28
申请号：EP97945392.5
申请日：1997-09-29
申请人： ADVANCED MICRO DEVICES INC.
发明人： WENDELL, Dennis, L.
IPC分类号： G11C29/00 , G06F11/24 , G11C8/00
CPC分类号： G11C29/026 , G11C7/065 , G11C7/1006 , G11C7/12 , G11C7/22 , G11C8/08 , G11C8/14 , G11C11/401 , G11C11/4087 , G11C11/41 , G11C11/412 , G11C11/418 , G11C16/04 , G11C17/14 , G11C29/02 , G11C29/021 , G11C29/025 , G11C29/028 , G11C29/18 , G11C29/32 , G11C29/50 , G11C29/50004 , G11C29/50012 , G11C29/50016 , G11C2029/5004 , G11C2029/5006 , H03K3/356156 , H03K5/13 , H03K2005/00019 , H03K2005/00071 , H03L7/08 , H03L7/0995
摘要： A memory array test and characterization capability is disclosed which allows DC characterization of the memory cells, the bit lines, and the sense amplifiers. A row decoder is provided which includes a static wordline select signal to disable self-resetting logic within the row decoder and allow the word line to remain active for a user-controlled length of time. An analog wordline drive capability allows the active wordline to be driven to a user-controllable analog level. Direct access to a pair of bitlines is provided by a multiplexer which is statically decoded to couple a pair of isolated terminals to the respective bitlines within the decoded column. This allows DC voltage levels to be impressed upon each of the two bitlines within the decoded column and/or the two bitline currents to be sensed. A separate power connection is provided for the memory array which allows operating the memory array at a different power supply voltage than the remainder of the circuit. By utilizing one or more of these features together, several tests of the memory array may be performed, including characterizing the DC transfer function of the memory cells, the standby power of the memory array, the static noise margin of the memory cells, the alpha particle susceptibility of the memory cells as a function of memory cell supply voltage, the offset voltage of bitline sense amplifiers, and others.

4. 发明公开

EP0929900A1 DATA RETENTION TEST FOR STATIC MEMORY CELL 失效
标题翻译：隐私测试静态CELL
公开(公告)号：EP0929900A1
公开(公告)日：1999-07-21
申请号：EP97945360.0
申请日：1997-09-29
申请人： ADVANCED MICRO DEVICES INC.
发明人： WENDELL, Dennis, L.
IPC分类号： G06F12 , G11C7 , G11C8 , G11C11 , G11C29 , H03K3 , H03K5 , H03L7
CPC分类号： G11C29/026 , G06F12/1054 , G11C7/065 , G11C7/1006 , G11C7/12 , G11C7/22 , G11C8/08 , G11C8/14 , G11C11/401 , G11C11/4087 , G11C11/41 , G11C11/412 , G11C11/418 , G11C16/04 , G11C17/14 , G11C29/02 , G11C29/021 , G11C29/025 , G11C29/028 , G11C29/18 , G11C29/32 , G11C29/50 , G11C29/50004 , G11C29/50012 , G11C29/50016 , G11C2029/5004 , G11C2029/5006 , H03K3/356156 , H03K5/13 , H03K2005/00019 , H03K2005/00071 , H03L7/08 , H03L7/0995
摘要： A manufacturing defect which causes a memory cell load device to be non-functional is frequently difficult to test. Such a defective memory cell can be written and subsequently read successfully even without the missing load device. But if the delay between the write and the subsequent read is long enough, the internal node of the memory cell leaks down to a degraded high level, and only then will the memory cell fail. The delay required to detect such a failure may easily reach tens of seconds, which is entirely inconsistent with the required economies of manufacturing test. A data retention circuit and method allows high speed test of a static memory cell to ensure that the load devices within the cell are actually present and functioning. An analog word line drive capability allows the active word line to be driven to a user-controllable analog level. This is accomplished by connecting the "VDD" and N-well of the final PMOS stage of the row decoder to an isolated terminal which is normally connected to VDD when assembled , but which is independently available prior to packaging. By lowering the analog word line voltage compared to the memory array power supply voltage, a written high level in a memory cell lacking a load device is not pulled high (because the load device in question is missing) and is already low enough to cause a subsequent read to immediately fail. Consequently, the memory array can be tested without requiring long delays between the write and read of each memory cell. Advantageously, the row and column support circuits and sensing circuits operate at the normal power supply levels for which they were designed and which may be independently margin tested.

5. 发明授权

EP3195317B1 DELAY CIRCUIT WITH PARALLEL DELAY LINES AND INTERNAL SWITCHES BETWEEN THE DELAY LINES 有权
公开(公告)号：EP3195317B1
公开(公告)日：2018-12-26
申请号：EP15747891.8
申请日：2015-07-22
申请人： Qualcomm Incorporated
发明人： SINGH, Guneet , CHENG, Yuehchun Claire , DIFFENDERFER, Jan Christian , SRINIVAS, Vaishnav , KIM, Robert Won Chol
IPC分类号： G11C7/10 , G11C11/4076 , G11C29/02 , G11C7/22
CPC分类号： H03K5/13 , G11C7/1066 , G11C7/1093 , G11C7/222 , G11C11/4076 , G11C29/023 , G11C29/028 , H03K2005/00019
摘要： Systems and methods for delay control are described herein. In one embodiment, a delay circuit comprises a first delay path and a second delay path. The delay circuit also comprises a plurality of switches, wherein each switch is coupled between different points on the first and second delay paths, and each switch is configured to turn on or off in response to a respective one of a plurality of select signals. The delay circuit further comprises a multiplexer having a first input coupled to an output of the first delay path, a second input coupled to an output of the second delay path, and an output coupled to an output of the delay circuit, wherein the multiplexer is configured to selectively couple one of the outputs of the first and second delay paths to the output of the delay circuit in response to a second select signal.

6. 发明公开

EP3195317A1 DELAY CIRCUIT WITH PARALLEL DELAY LINES AND INTERNAL SWITCHES BETWEEN THE DELAY LINES 有权
标题翻译：延迟线与延迟线之间的并行延迟线和内部开关
公开(公告)号：EP3195317A1
公开(公告)日：2017-07-26
申请号：EP15747891.8
申请日：2015-07-22
申请人： Qualcomm Incorporated
发明人： SINGH, Guneet , CHENG, Yuehchun Claire , DIFFENDERFER, Jan Christian , SRINIVAS, Vaishnav , KIM, Robert Won Chol
IPC分类号： G11C7/10 , G11C11/4076 , G11C29/02 , G11C7/22
CPC分类号： H03K5/13 , G11C7/1066 , G11C7/1093 , G11C7/222 , G11C11/4076 , G11C29/023 , G11C29/028 , H03K2005/00019
摘要： Systems and methods for delay control are described herein. In one embodiment, a delay circuit comprises a first delay path and a second delay path. The delay circuit also comprises a plurality of switches, wherein each switch is coupled between different points on the first and second delay paths, and each switch is configured to turn on or off in response to a respective one of a plurality of select signals. The delay circuit further comprises a multiplexer having a first input coupled to an output of the first delay path, a second input coupled to an output of the second delay path, and an output coupled to an output of the delay circuit, wherein the multiplexer is configured to selectively couple one of the outputs of the first and second delay paths to the output of the delay circuit in response to a second select signal.
摘要翻译：这里描述了用于延迟控制的系统和方法。在一个实施例中，延迟电路包括第一延迟路径和第二延迟路径。延迟电路还包括多个开关，其中每个开关耦合在第一延迟路径和第二延迟路径上的不同点之间，并且每个开关被配置为响应于多个选择信号中的相应一个而导通或截止。延迟电路还包括多路复用器，其具有耦合到第一延迟路径的输出的第一输入，耦合到第二延迟路径的输出的第二输入和耦合到延迟电路的输出的输出，其中多路复用器是被配置为响应于第二选择信号选择性地将第一延迟路径和第二延迟路径的输出中的一个耦合到延迟电路的输出。

7. 发明公开

EP3179260A1 APPARATUS AND METHOD FOR MONITORING PERFORMANCE OF INTEGRATED CIRCUIT 审中-公开
标题翻译：装置和用于监控性能的集成电路
公开(公告)号：EP3179260A1
公开(公告)日：2017-06-14
申请号：EP15199266.6
申请日：2015-12-10
申请人： Stichting IMEC Nederland
发明人： STUIJT, Jan
IPC分类号： G01R31/30 , G01R31/317 , H02M3/00
CPC分类号： H03K5/19 , G01R31/2882 , G01R31/3016 , G01R31/31725 , G05F1/10 , H03K2005/00019
摘要： The present invention discloses an apparatus and method for monitoring performance of an integrated circuit. The apparatus (10) comprises: a delay line (30), which receives a pulse signal, wherein the delay line (30) has a controllable, variable length and propagates the pulse signal through a set length; a comparator (40), which receives the propagated pulse signal from the delay line (30) and a clock signal, said comparator (40) being arranged to determine whether the received signal is received early or late; and a feedback loop (50; 150), which receives input from the comparator (40) for dynamically increasing or decreasing the set length of the delay line (30) in dependence of the determination by the comparator (40); wherein said apparatus (10) determines a speed of the integrated circuit based on a determination by the comparator (40) that the signal from the delay line (30) closely matches the clock signal.
摘要翻译：本发明盘松动到用于集成电路的监视性能的装置和方法。的装置（10）包括：一个延时线（30），其接收的脉冲信号，worin延迟线（30）具有可控的，可变长度和传播通过一组长度脉冲信号; 一个比较器（40），其接收从延迟线（30）和时钟信号，所述比较器（40）的传播的脉冲信号被布置为确定是否矿所接收的信号被提前或延迟接收的; 和一反馈回路（50; 150），其从比较器（40），用于由所述比较动态增加或减少所述确定的相关性的延迟线（30）的设定长度接收输入（40）; worin所述装置（10）bestimmt基于由所述比较器（40）确定该集成电路的速度确实从延迟线（30）的信号中的时钟信号紧密地匹配。

8. 发明公开

EP2980803A4 DELAY CIRCUIT, ELECTRONIC CIRCUIT USING DELAY CIRCUIT AND ULTRASONIC IMAGING DEVICE 有权转让
标题翻译：延迟电路，具有延迟电路和超声成像装置的电子电路
公开(公告)号：EP2980803A4
公开(公告)日：2017-03-01
申请号：EP13879941
申请日：2013-03-28
申请人： HITACHI LTD
发明人： NAKAGAWA TATSUO
IPC分类号： G11C27/00 , A61B8/00 , G11C27/02 , H03H11/26 , H03H19/00 , H03K5/00 , H03K5/13
CPC分类号： H03K5/133 , A61B8/4494 , A61B8/54 , G01S7/52025 , G01S7/5208 , G01S15/8927 , G10K11/346 , G11C27/00 , G11C27/024 , H03H11/265 , H03H19/00 , H03K2005/00019

9. 发明公开

EP2526552A4 DUTY CYCLE CORRECTION CIRCUIT FOR MEMORY INTERFACES IN INTEGRATED CIRCUITS 审中-公开
标题翻译：占空比校正电路，用于集成电路存储器接口
公开(公告)号：EP2526552A4
公开(公告)日：2016-10-26
申请号：EP11735137
申请日：2011-01-19
申请人： ALTERA CORP
发明人： CHONG YAN , HUANG JOSEPH , NAGARAJAN PRADEEP , SUNG CHIAKANG
IPC分类号： G11C7/22 , G11C7/10 , H03K5/00 , H03K5/151 , H03K5/1534 , H03K5/156
CPC分类号： H03K5/1565 , H03K5/151 , H03K5/1534 , H03K2005/00019

10. 发明公开

EP2795794A1 APPARATUS AND SYSTEM FOR GENERATING A SIGNAL WITH PHASE ANGLE CONFIGURATION 审中-公开
标题翻译：设备和系统，用于生成与相位角配置的信号
公开(公告)号：EP2795794A1
公开(公告)日：2014-10-29
申请号：EP11877725.9
申请日：2011-12-23
申请人： Intel Corporation
发明人： SCHROM, Gerhard , RAGHURAMAN, Narayanan , PAILLET, Fabrice
IPC分类号： H03K5/13 , H03H11/26
CPC分类号： H02M1/14 , G06F1/26 , H02M2003/1586 , H03H7/325 , H03H11/265 , H03K3/0315 , H03K4/06 , H03K5/133 , H03K5/134 , H03K7/08 , H03K2005/00019 , H03K2005/00195 , H03L7/00
摘要： Described herein is an apparatus and system for generating a signal with phase angle configuration. The apparatus comprises an array of switch-resistors, each switch resistor to receive a control signal, wherein the array of switch-resistors to generate an output signal; and a circuit to configure phase angle of the output signal. The apparatus can be used for different package and inductor configurations. The apparatus provides flexibility to mitigate switching noise by adjusting phase angles, and provides the ability to enable and disable switch-resistors on the fly without ripples. The apparatus also saves power consumption by selectively turning off switch-resistors when phases are disabled. The output signal of the apparatus has smooth triangular waveforms for improving the quality of power supply generated using the output signal. Overall, the apparatus exhibits reduced sensitivity to process variations compared to traditional signal generators.

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