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1. 发明授权

EP3179260B1 APPARATUS AND METHOD FOR MONITORING PERFORMANCE OF INTEGRATED CIRCUIT 有权
公开(公告)号：EP3179260B1
公开(公告)日：2018-09-26
申请号：EP15199266.6
申请日：2015-12-10
申请人： Stichting IMEC Nederland
发明人： STUIJT, Jan
IPC分类号： G01R31/30 , G01R31/317 , H02M3/00 , G01R31/28 , G05F1/10 , H03K5/19 , H03K5/00
CPC分类号： H03K5/19 , G01R31/2882 , G01R31/3016 , G01R31/31725 , G05F1/10 , H03K2005/00019
摘要： The present invention discloses an apparatus and method for monitoring performance of an integrated circuit. The apparatus (10) comprises: a delay line (30), which receives a pulse signal, wherein the delay line (30) has a controllable, variable length and propagates the pulse signal through a set length; a comparator (40), which receives the propagated pulse signal from the delay line (30) and a clock signal, said comparator (40) being arranged to determine whether the received signal is received early or late; and a feedback loop (50; 150), which receives input from the comparator (40) for dynamically increasing or decreasing the set length of the delay line (30) in dependence of the determination by the comparator (40); wherein said apparatus (10) determines a speed of the integrated circuit based on a determination by the comparator (40) that the signal from the delay line (30) closely matches the clock signal.

2. 发明公开

EP2980803A1 DELAY CIRCUIT, ELECTRONIC CIRCUIT USING DELAY CIRCUIT AND ULTRASONIC IMAGING DEVICE 有权转让
标题翻译： VERZÖGERUNGSSCHALTUNG，ELEKTRONISCHE SCHALTUNG MIT EINERVERZÖGERUNGSSCHALTUNGUND ULTRASCHALLBILDGEBUNGSVORRICHTUNG
公开(公告)号：EP2980803A1
公开(公告)日：2016-02-03
申请号：EP13879941.6
申请日：2013-03-28
申请人： Hitachi, Ltd.
发明人： NAKAGAWA Tatsuo
IPC分类号： G11C27/00 , A61B8/00 , H03H11/26 , H03H19/00
CPC分类号： H03K5/133 , A61B8/4494 , A61B8/54 , G01S7/52025 , G01S7/5208 , G01S15/8927 , G10K11/346 , G11C27/00 , G11C27/024 , H03H11/265 , H03H19/00 , H03K2005/00019
摘要： A delay circuit and an ultrasonic imaging apparatus with the higher-accuracy delay time, the longer maximum delay time, and the lower power consumption are provided. An input line to which an analog input signal is input, a plurality of analog signal memory devices, an output line, a plurality of sampling switches that control connection/disconnection between the input line and the plurality of analog signal memory devices, a plurality of output switches that control connection/disconnection between the plurality of analog signal memory devices and the output line, and a clock generation part that generates sampling switch control signals for controlling the sampling switches and output switch control signals for controlling the output switches are provided, and phase of the sampling switch control signals may be shifted with respect to phase of the output switch control signals.
摘要翻译：提供具有更高精度的延迟时间，更长的最大延迟时间和更低的功耗的延迟电路和超声成像设备。输入模拟输入信号的输入线，多个模拟信号存储装置，输出线，控制输入线与多个模拟信号存储装置之间的连接/断开的多个采样开关，多个提供了控制多个模拟信号存储装置与输出线之间的连接/断开的输出开关，以及产生用于控制采样开关的采样开关控制信号和用于控制输出开关的输出开关控制信号的时钟产生部分，采样开关控制信号的相位可以相对于输出开关控制信号的相位移动。

3. 发明授权

EP0929901B1 MEMORY ARRAY, MEMORY CELL, AND SENSE AMPLIFIER TEST AND CHARACTERIZATION 失效
标题翻译：测试和表征存储矩阵，存储单元和读出放大器的
公开(公告)号：EP0929901B1
公开(公告)日：2001-11-28
申请号：EP97945392.5
申请日：1997-09-29
申请人： ADVANCED MICRO DEVICES INC.
发明人： WENDELL, Dennis, L.
IPC分类号： G11C29/00 , G06F11/24 , G11C8/00
CPC分类号： G11C29/026 , G11C7/065 , G11C7/1006 , G11C7/12 , G11C7/22 , G11C8/08 , G11C8/14 , G11C11/401 , G11C11/4087 , G11C11/41 , G11C11/412 , G11C11/418 , G11C16/04 , G11C17/14 , G11C29/02 , G11C29/021 , G11C29/025 , G11C29/028 , G11C29/18 , G11C29/32 , G11C29/50 , G11C29/50004 , G11C29/50012 , G11C29/50016 , G11C2029/5004 , G11C2029/5006 , H03K3/356156 , H03K5/13 , H03K2005/00019 , H03K2005/00071 , H03L7/08 , H03L7/0995
摘要： A memory array test and characterization capability is disclosed which allows DC characterization of the memory cells, the bit lines, and the sense amplifiers. A row decoder is provided which includes a static wordline select signal to disable self-resetting logic within the row decoder and allow the word line to remain active for a user-controlled length of time. An analog wordline drive capability allows the active wordline to be driven to a user-controllable analog level. Direct access to a pair of bitlines is provided by a multiplexer which is statically decoded to couple a pair of isolated terminals to the respective bitlines within the decoded column. This allows DC voltage levels to be impressed upon each of the two bitlines within the decoded column and/or the two bitline currents to be sensed. A separate power connection is provided for the memory array which allows operating the memory array at a different power supply voltage than the remainder of the circuit. By utilizing one or more of these features together, several tests of the memory array may be performed, including characterizing the DC transfer function of the memory cells, the standby power of the memory array, the static noise margin of the memory cells, the alpha particle susceptibility of the memory cells as a function of memory cell supply voltage, the offset voltage of bitline sense amplifiers, and others.

4. 发明公开

EP0929900A1 DATA RETENTION TEST FOR STATIC MEMORY CELL 失效
标题翻译：隐私测试静态CELL
公开(公告)号：EP0929900A1
公开(公告)日：1999-07-21
申请号：EP97945360.0
申请日：1997-09-29
申请人： ADVANCED MICRO DEVICES INC.
发明人： WENDELL, Dennis, L.
IPC分类号： G06F12 , G11C7 , G11C8 , G11C11 , G11C29 , H03K3 , H03K5 , H03L7
CPC分类号： G11C29/026 , G06F12/1054 , G11C7/065 , G11C7/1006 , G11C7/12 , G11C7/22 , G11C8/08 , G11C8/14 , G11C11/401 , G11C11/4087 , G11C11/41 , G11C11/412 , G11C11/418 , G11C16/04 , G11C17/14 , G11C29/02 , G11C29/021 , G11C29/025 , G11C29/028 , G11C29/18 , G11C29/32 , G11C29/50 , G11C29/50004 , G11C29/50012 , G11C29/50016 , G11C2029/5004 , G11C2029/5006 , H03K3/356156 , H03K5/13 , H03K2005/00019 , H03K2005/00071 , H03L7/08 , H03L7/0995
摘要： A manufacturing defect which causes a memory cell load device to be non-functional is frequently difficult to test. Such a defective memory cell can be written and subsequently read successfully even without the missing load device. But if the delay between the write and the subsequent read is long enough, the internal node of the memory cell leaks down to a degraded high level, and only then will the memory cell fail. The delay required to detect such a failure may easily reach tens of seconds, which is entirely inconsistent with the required economies of manufacturing test. A data retention circuit and method allows high speed test of a static memory cell to ensure that the load devices within the cell are actually present and functioning. An analog word line drive capability allows the active word line to be driven to a user-controllable analog level. This is accomplished by connecting the "VDD" and N-well of the final PMOS stage of the row decoder to an isolated terminal which is normally connected to VDD when assembled , but which is independently available prior to packaging. By lowering the analog word line voltage compared to the memory array power supply voltage, a written high level in a memory cell lacking a load device is not pulled high (because the load device in question is missing) and is already low enough to cause a subsequent read to immediately fail. Consequently, the memory array can be tested without requiring long delays between the write and read of each memory cell. Advantageously, the row and column support circuits and sensing circuits operate at the normal power supply levels for which they were designed and which may be independently margin tested.

5. 发明授权

EP3211626B1 PROCÉDÉ ET DISPOSITIF DE BROUILLAGE ÉLECTROMAGNÉTIQUE POUR CIRCUIT INTÉGRÉ 有权
公开(公告)号：EP3211626B1
公开(公告)日：2018-10-31
申请号：EP16181835.6
申请日：2016-07-29
申请人： STMicroelectronics (Rousset) SAS
发明人： ORDAS, Thomas , SARAFIANOS, Alexandre , CHESNAIS, Stéphane , MARINET, Fabrice
IPC分类号： G09C1/00 , H04L9/00 , G06K19/073 , H04K3/00
CPC分类号： H04L9/002 , G06F1/04 , G06F21/72 , G06K19/07336 , G09C1/00 , H01L23/528 , H03K3/84 , H03K5/01 , H03K2005/00019 , H04K3/40 , H04K3/825 , H04K3/94 , H04K2203/32 , H04L9/003 , H04L2209/08 , H04L2209/805

6. 发明公开

EP3337038A1 CIRCUITS FOR DELAY MISMATCH COMPENSATION AND RELATED METHODS 有权
公开(公告)号：EP3337038A1
公开(公告)日：2018-06-20
申请号：EP17197178.1
申请日：2017-10-18
申请人： MediaTek Inc.
发明人： Park, Henry Arnold , Ali, Tamer Mohammed
IPC分类号： H03K5/15 , H03K5/151 , G06F1/10 , H03K3/03
CPC分类号： H03K5/159 , G06F1/10 , H03K3/0315 , H03K5/1502 , H03K5/151 , H03K2005/00019
摘要： Circuits and methods for delay mismatch compensation are described. A circuit may comprise multiple data paths (204, 206, 214, 216) between a signal source, such as a driver (Inp, Inn), and a load (220). The paths may have different lengths, thus causing delay mismatches. An exemplary circuit (300) of the type described herein may comprise delay elements (209, 211) and at least one feedback circuit (302) designed to compensate for such delay mismatches. The circuit may operate in different phases, such as a compensation phase and a driving phase. In the compensation phase, rings oscillators including delay elements and the at least one feedback circuit may be formed. In this phase the delay may be adjusted to compensate for mismatches. In the driving phase, the signal source may be connected to the load (220).

7. 发明公开

EP3192172A2 AUTOMATIC CALIBRATION CIRCUITS FOR OPERATIONAL CALIBRATION OF CRITICAL-PATH TIME DELAYS IN ADAPTIVE CLOCK DISTRIBUTION SYSTEMS, AND RELATED METHODS AND SYSTEMS 审中-公开
标题翻译：用于自适应时钟配电系统中的临界路径时延的操作校准的自动校准电路及相关的方法和系统
公开(公告)号：EP3192172A2
公开(公告)日：2017-07-19
申请号：EP15760557.7
申请日：2015-08-24
申请人： Qualcomm Incorporated
发明人： BOWMAN, Keith, Alan , BRIDGES, Jeffrey, Todd , RAINA, Sarthak , KOLLA, Yeshwant, Nagaraj , JEONG, Jihoon , ATALLAH, Francois, Ibrahim , FLEDERBACH, William, Robert , FISCHER, Jeffrey, Herbert
IPC分类号： H03K5/156 , G06F1/10 , H03K5/134
CPC分类号： H03K5/13 , G06F1/10 , H03K5/134 , H03K5/156 , H03K2005/00019
摘要： Automatic calibration circuits for operational calibration of critical-path time delays in adaptive clock distribution systems, and related methods and systems, are disclosed. The adaptive clock distribution system includes a tunable-length delay circuit to delay distribution of a clock signal provided to a clocked circuit, to prevent timing margin degradation of the clocked circuit after a voltage droop occurs in a power supply supplying power to the clocked circuit. The adaptive clock distribution system also includes a dynamic variation monitor to reduce frequency of the delayed clock signal provided to the clocked circuit in response to the voltage droop in the power supply, so that the clocked circuit is not clocked beyond its performance limits during a voltage droop. An automatic calibration circuit is provided in the adaptive clock distribution system to calibrate the dynamic variation monitor during operation based on operational conditions and environmental conditions of the clocked circuit.
摘要翻译：用于自适应时钟分配系统中的关键路径时间延迟的操作校准的自动校准电路以及相关的方法和系统被公开。自适应时钟分配系统包括可调长度延迟电路，用于延迟提供给时钟电路的时钟信号的分布，以防止在向时钟电路供电的电源中发生电压下降之后时钟电路的时序裕度劣化。自适应时钟分配系统还包括动态变化监视器，以响应于电源中的电压下降而降低提供给时钟电路的延迟时钟信号的频率，使得时钟电路在电压期间不超过其性能极限下垂。在自适应时钟分配系统中提供自动校准电路，以根据时钟电路的操作条件和环境条件来校准操作期间的动态变化监测器。

8. 发明公开

EP3101779A1 VOLTAGE SOURCE DRIVER FOR A PARALLEL RESONANT MAGNETIC FIELD GENERATOR 有权
标题翻译： EANEN平行线SELBSTSCHWINGENDEN MAGNETFELDGATERATOR SPANNUNGSQUELLENTREIBER
公开(公告)号：EP3101779A1
公开(公告)日：2016-12-07
申请号：EP16171731.9
申请日：2016-05-27
申请人： Resonant Circuits Ltd
发明人： SOUTHERN, Paul , HATTERSLEY, Simon Richard
IPC分类号： H02J50/10 , H05B6/02
CPC分类号： H03K17/687 , A61N2/02 , H02J50/10 , H03K5/13 , H03K2005/00019 , H05B6/06 , H05B6/062 , H05B6/10 , H05B6/40 , H05B6/42
摘要： A magnetic field generator. In one embodiment, the magnetic field generator includes a drive circuit including a MOSFET gate driver having an output terminal; a drive capacitor having a first and second terminal, a tank circuit including a tank circuit capacitor having a first and second terminal and a field-producing coil having a first and second terminal, wherein the first terminal of the tank circuit capacitor and the first terminal of the field-producing coil comprise the first terminal of the tank circuit, wherein the second terminal of the tank circuit capacitor and the second terminal of the field-producing coil comprise the second terminal of the tank circuit, wherein the first terminal of the drive capacitor is in electrical communication with the output terminal of the MOSFET gate driver, and wherein the second terminal of the drive capacitor is in electrical communication with the first terminal of the tank circuit.
摘要翻译：磁场发生器。在一个实施例中，磁场发生器包括具有输出端的MOSFET栅极驱动器的驱动电路; 具有第一和第二端子的驱动电容器，包括具有第一和第二端子的储能电路电容器和具有第一和第二端子的励磁产生线圈的储能电路，其中所述储能电路电容器的第一端子和所述第一端子励磁产生线圈的第一端子包括储能电路的第一端子，其中储能电路电容器的第二端子和励磁线圈的第二端子包括储能电路的第二端子，其中驱动器的第一端子电容器与MOSFET栅极驱动器的输出端子电连通，并且其中驱动电容器的第二端子与储能电路的第一端子电连通。

9. 发明公开

EP2526552A2 DUTY CYCLE CORRECTION CIRCUIT FOR MEMORY INTERFACES IN INTEGRATED CIRCUITS 审中-公开
标题翻译：占空比校正电路，用于集成电路存储器接口
公开(公告)号：EP2526552A2
公开(公告)日：2012-11-28
申请号：EP11735137.9
申请日：2011-01-19
申请人： Altera Corporation
发明人： CHONG, Yan , HUANG, Joseph , NAGARAJAN, Pradeep , SUNG, Chiakang
IPC分类号： G11C7/22 , G11C7/10
CPC分类号： H03K5/1565 , H03K5/151 , H03K5/1534 , H03K2005/00019
摘要： Circuits and a method for correcting duty cycle distortions in an integrated circuit (IC) are disclosed. The IC includes a splitter circuit that is coupled to receive a clock signal. The clock signal is split into two different clock signals. One of the clock signals is an inverted version of the other. A delay circuit is coupled to each of the clock signals. Each of the delay circuits generates a delayed version of the corresponding clock signal. A corrector circuit is coupled to receive both the delayed versions of the clock signals. The corrector circuit generates a clock output signal with a corrected duty cycle.

10. 发明授权

EP0929898B1 MEMORY BLOCK SELECT USING MULTIPLE WORD LINES TO ADDRESS A SINGLE MEMORY CELL ROW 失效
标题翻译：存储块选使用多个字线的寻址单个存储单元LINE
公开(公告)号：EP0929898B1
公开(公告)日：2001-11-28
申请号：EP97945064.0
申请日：1997-09-29
申请人： ADVANCED MICRO DEVICES INC.
发明人： WENDELL, Dennis, Lee , HOLST, John, Christian
IPC分类号： G11C8/00
CPC分类号： G11C29/026 , G06F12/1054 , G11C7/065 , G11C7/1006 , G11C7/12 , G11C7/22 , G11C8/08 , G11C8/12 , G11C8/14 , G11C11/401 , G11C11/4087 , G11C11/41 , G11C11/412 , G11C11/418 , G11C16/04 , G11C17/14 , G11C29/02 , G11C29/021 , G11C29/025 , G11C29/028 , G11C29/18 , G11C29/32 , G11C29/50 , G11C29/50004 , G11C29/50012 , G11C29/50016 , G11C2029/5004 , G11C2029/5006 , H03K3/356156 , H03K5/13 , H03K2005/00019 , H03K2005/00071 , H03L7/08 , H03L7/0995 , Y02D10/13
摘要： A highly suitable power conservation technique involves extending multiple word lines over a memory array row and connecting a portion of the memory cells of the memory array row to each of the word lines. Power is supplied only to the portion of the memory cells that is accessed, eliminating the static power consumption of the non-accessed memory cells. By connecting multiple word lines to select a portion of a memory row, a column address of the memory is mapped into a row decode space. Multiple metal layers in a complex integrated circuit may be exploited to form cache block select lines using multiple word lines per cell row. A storage includes a plurality of storage cells arranged in an array of rows and columns, a plurality of bit lines connecting the array of storage cells into columns, and a plurality of word lines connecting the array of storage cells into rows. The plurality of word lines include multiple word lines for a single row of the plurality of rows so that multiple portions of the storage cells in the single row are addressed by corresponding multiple word lines.

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