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1. 发明公开

EP4450985A1 CLOCK SIGNAL MONITORING UNIT 审中-公开
公开(公告)号：EP4450985A1
公开(公告)日：2024-10-23
申请号：EP23168733.6
申请日：2023-04-19
申请人： NXP B.V.
发明人： Lentz, Andreas , Price, David Paul
IPC分类号： G01R31/317 , G06F1/10 , H03K5/19
CPC分类号： G01R31/31727 , G06F1/10 , H03K5/19 , H03K5/1536 , H03K5/1565
摘要： Clock signal monitoring unit (100), comprising:
- a first flip flop (10) and a second flip flop (11), the first flip flop (10) and the second flip flop (11) being cross-coupled, the first flip flop (10) being dockable by a clock signal (CLK) and the second flip flop (11) being clockable by an inverted clock signal (CLK), wherein outputs of the first and second flip flops (10, 11) are connected to a first XOR gate (20);
- a third flip flop (12) being dockable by the clock signal (CLK) and a fourth flip flop (13) being dockable by the inverted clock signal (CLK);
- an output of the first XOR gate (20) being connected to a delay element (21), the delay element (21) being adapted to delay the output of the first XOR gate (20) to a specified amount of time (T1), wherein the specified amount of time (T1) stands in a defined relationship to a frequency of the clock signal (CLK);
- an output of the delay element (21) being connected to the third flip flop (12) and to the fourth flip flop (13);
- an output of the third flip flop (12) and an inverted output of the fourth flip flop (13) being connected to the second XOR gate (14); and
- an output of the second XOR gate (14) being configured to provide a glitch detect signal (GD).

2. 发明公开

EP3365975A1 SIGNAL PROCESSING METHOD FOR HISTOGRAM GENERATION, AND CORRESPONDING DEVICE AND USE 有权
公开(公告)号：EP3365975A1
公开(公告)日：2018-08-29
申请号：EP16790911.8
申请日：2016-10-20
申请人： Universitat de Barcelona
发明人： DIEGUEZ BARRIENTOS, Angel , ALONSO CASANOVAS, Oscar , CANALS GIL, Joan , VILELLA FIGUERAS, Eva
IPC分类号： H03K5/1534 , H03K5/19
CPC分类号： G01J1/0238 , G01J1/46 , G01J2001/442 , G01J2001/4466 , H03K5/1534 , H03K5/19
摘要： Signal processing method for histogram generation, and corresponding device and use. The method generates the histogram from a plurality of event detectors that generate event signals as a response to external events, and are connected to a current injection module which is connected to a plurality of capacitors, wherein each histogram bin is univocally assigned to a capacitor. The method includes: during an event time interval corresponding to a bin, the event detectors generate event signals as a response to external events; the current injection module detects said event signals and, for each event signal, generates a corresponding current signal, which is injected in a capacitor assigned to said bin, and stored therein; repeating steps for each successive bin of said histogram; and reading the charge accumulated in each of said capacitors.

3. 发明公开

EP3301542A1 POWER SUPPLY VOLTAGE MONITORING AND HIGH-RESOLUTION ADAPTIVE CLOCK STRETCHING CIRCUIT 有权
标题翻译：电源电压监视和高分辨率自适应时钟拉伸电路
公开(公告)号：EP3301542A1
公开(公告)日：2018-04-04
申请号：EP17193595.0
申请日：2017-09-27
申请人： Mellanox Technologies, Ltd.
发明人： CARLSON, Andrew , RAMEY, Carl
IPC分类号： G06F1/32 , G01R31/317 , H03K5/135
CPC分类号： H03K5/06 , G01R31/31725 , G06F1/3206 , G06F1/324 , H03K5/135 , H03K5/19
摘要： An integrated circuit and method are described for compensating for voltage droop on an integrated circuit using a power supply voltage monitoring circuit and a high resolution adaptive clock stretching circuit. In some example embodiments, the method includes monitoring (602) power supply voltage on an integrated circuit, detecting (604) a voltage droop such as a dynamic loss of power supply in the integrated circuit, and stretching (606) a current clock cycle, according to the detected voltage droop, to provide more time for logic on the integrated circuit to complete before a next clock cycle.
摘要翻译：描述了使用电源电压监视电路和高分辨率自适应时钟展宽电路来补偿集成电路上的电压下降的集成电路和方法。在一些示例实施例中，该方法包括监测（602）集成电路上的电源电压，检测（604）诸如集成电路中的电源的动态损耗的电压下降，以及拉伸（606）当前时钟周期，根据检测到的电压下降，为集成电路上的逻辑提供更多时间以在下一个时钟周期之前完成。

4. 发明公开

EP3243267A1 FREQUENZUMRICHTER 审中-公开
标题翻译： FREQUENCY
公开(公告)号：EP3243267A1
公开(公告)日：2017-11-15
申请号：EP15816149.7
申请日：2015-12-17
申请人： Schmidhauser AG
发明人： BISIG, Thomas
IPC分类号： H02M5/45
CPC分类号： G06F11/1604 , G06F1/08 , H02M5/45 , H02M5/4585 , H03K5/19 , H03L7/1803 , H04L12/56 , H04L2012/5674
摘要： The invention relates to a frequency converter (1) having a control unit (2). The control unit (2) has: a serial control-unit interface (3); a control-unit clock generator (4) for generating a control-unit clock pulse, data being transmitted via the serial control-unit interface (3) in accordance with the control-unit clock pulse; and a control-unit processor (5) which is designed to determine at least one control variable in accordance with at least one actual value. The frequency converter (1) also has a power unit (6), said unit having a data connection to the control unit (2) and having: a number of power semiconductors (7); a power-unit clock generator (8) for generating an adjustable power-unit clock pulse; a serial power-unit interface (9), which can be coupled to the control-unit interface (3) in order to produce a data connection; a clock-generator adjusting unit (10), which has a signal connection to the power-unit interface (9) and is designed to adjust the power-unit clock pulse in accordance with signals received by the power unit (6) on the power-unit interface (9); a power-unit processor (11), which is designed to control the power semiconductors (7) in accordance with the control variable and the power-unit clock pulse; and at least one sensor unit (12), which is designed to determine the at least one actual value. The control unit (2) is designed to transmit the at least one control variable to the power unit (6) via the control-unit interface (3) and the power unit (6) is designed to transmit the at least one actual value to the control unit (2) via the power-unit interface (9).

5. 发明公开

EP3235134A1 PHASE SWITCHING PLL AND CALIBRATION METHOD 有权
标题翻译：相位切换PLL和校准方法
公开(公告)号：EP3235134A1
公开(公告)日：2017-10-25
申请号：EP15813337.1
申请日：2015-12-15
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： EK, Staffan , PÅHLSSON, Tony , SJÖLAND, Henrik , SUNDSTRÖM, Lars
IPC分类号： H03L7/08 , H03L7/081 , H03L7/085
CPC分类号： H01Q3/34 , H03K5/19 , H03L7/08 , H03L7/085 , H03L7/0891 , H03L7/093 , H03L7/099 , H03L2207/06
摘要： The phase-locked loop (PLL) presented herein controls the phase of the output of the PLL. To that end, the PLL includes an oscillator that generates an output signal at an output of the PLL responsive to a comparison between a reference signal input to the PLL and a feedback signal derived from the output signal. To control the phase of the output signal, a modulation signal is applied to one input of the oscillator, separate from the reference signal input, where the modulation signal comprises one or more pulses having a total area defined based on the desired phase shift. To maintain the desired phase shift at the output of the PLL, the PLL also sets a time relationship between the reference signal and the feedback signal based on the desired phase shift.
摘要翻译：这里给出的锁相环（PLL）控制PLL输出的相位。为此，PLL包括振荡器，其响应于输入到PLL的参考信号与从输出信号得出的反馈信号之间的比较，在PLL的输出处产生输出信号。为了控制输出信号的相位，调制信号被施加到振荡器的一个输入端，与参考信号输入端分开，其中调制信号包括具有基于期望的相移位移定义的总面积的一个或多个脉冲。为了在PLL的输出端维持期望的相移，PLL还基于期望的相移来设置参考信号与反馈信号之间的时间关系。

6. 发明授权

EP2445109B1 CLOCK DETECTION METHOD AND DEVICE 有权
标题翻译：时钟检测方法和装置
公开(公告)号：EP2445109B1
公开(公告)日：2015-03-18
申请号：EP10785717.9
申请日：2010-05-26
申请人： ZTE Corporation
发明人： XU, Jichao
IPC分类号： H03K5/19 , G06F1/04
CPC分类号： H03K5/19

7. 发明授权

EP2562934B1 Oscillator circuits 有权
标题翻译：振荡器电路
公开(公告)号：EP2562934B1
公开(公告)日：2014-09-10
申请号：EP12193350.1
申请日：2002-10-15
申请人： Fujitsu Semiconductor Limited
发明人： Ogawa, Yasushige , Kawamoto, Satoru
IPC分类号： H03K3/014 , H03K3/03
CPC分类号： G06F1/04 , G11C7/22 , G11C7/222 , G11C11/406 , G11C11/4074 , G11C2207/2227 , G11C2211/4067 , H03K3/012 , H03K3/014 , H03K3/0315 , H03K5/1252 , H03K5/19 , H03L3/00

8. 发明公开

EP2482455A3 Oscillation-stop detection circuit, semiconductor device, timepiece, and electronic device 审中-公开
标题翻译：电路，用于检测一个Oszillationsstopps，半导体装置及电子装置PM
公开(公告)号：EP2482455A3
公开(公告)日：2014-07-23
申请号：EP12152618.0
申请日：2012-01-26
申请人： Seiko Epson Corporation
发明人： Nakamiya, Shinji
IPC分类号： H03K5/19 , H03K5/153
CPC分类号： H03K5/19 , G04G19/10 , H03K5/153
摘要： An oscillation-stop detection circuit can be manufactured at low cost without requiring controlling difficult manufacturing process conditions. Inverter 30 outputs an oscillation state detection signal. N-channel transistor 26 is a transistor that discharges capacitor 20. A reference voltage generator 21 includes a depletion-mode P-channel transistor 22 of which the gate and source are connected together, and a N-channel transistor 23 of which the gate and drain are connected together, N-channel transistor 23 and N-channel transistor 26 rendering a current mirror.

9. 发明公开

EP2717469A2 Method and apparatus for detecting cut-off frequency of pulse signal 审中-公开
标题翻译： Verfahren und Vorrichtung zur Erkennung der Grenzfrequenz eines Impulssignals
公开(公告)号：EP2717469A2
公开(公告)日：2014-04-09
申请号：EP13181992.2
申请日：2013-08-28
申请人： LSIS Co., Ltd.
发明人： Park, Kang Hee
IPC分类号： H03K5/19 , H03K5/26 , G01R23/00 , G01R23/10
CPC分类号： H03K21/40 , G01R23/10 , G01R23/15 , H03K5/19 , H03K5/26 , H03K21/38
摘要： An apparatus (30) and method for detecting a cut-off frequency of a pulse signal (First Pulse Signal) is provided to detect a cut-off frequency of a pulse signal, in a case a frequency of an inputted pulse signal exceeds a maximum rated speed due to various reasons including noises generated by a system environment or an encoder, or system design error, whereby an appropriate action thereto can be taken, the apparatus (30) including an input processor (31) configured to generate a second pulse signal at a time when a rising edge and a falling edge of a first pulse signal appear, in a case the first pulse signal, which is a pulse signal of a monitoring object, is inputted, a counter (32) configured to count a clock signal relative to the second pulse signal generated by the input processor, a reset processor (33) configured to reset the counter at every predetermined (set) period, and a detector (34) configured to generate and output a cut-off frequency of a detection signal, in a case an output value of the counter exceeds a predetermined (set) threshold during the predetermined period.
摘要翻译：在输入的脉冲信号的频率超过最大值的情况下，提供用于检测脉冲信号（第一脉冲信号）的截止频率的装置（30）和方法以检测脉冲信号的截止频率由于各种原因引起的额定速度，包括由系统环境或编码器产生的噪声或系统设计错误，由此可以采取适当的动作，所述装置（30）包括输入处理器（31），其被配置为产生第二脉冲信号在第一脉冲信号的上升沿和下降沿出现的情况下，在作为监视对象的脉冲信号的第一脉冲信号被输入的情况下，配置为对时钟信号进行计数的计数器（32）相对于由输入处理器产生的第二脉冲信号，复位处理器（33）被配置为以每个预定（设置）周期复位计数器;以及检测器（34），被配置为产生和输出检测的截止频率信号，在一种情况下计数器的输出值在规定期间内超过规定（设定）阈值。

10. 发明授权

EP2351221B1 SYSTEM FOR DETECTING A RESET CONDITION IN AN ELECTRONIC CIRCUIT 有权转让
标题翻译：系统用于检测电子电路的复位状态
公开(公告)号：EP2351221B1
公开(公告)日：2013-06-19
申请号：EP09822946.1
申请日：2009-10-30
申请人： Certicom Corp.
发明人： FULLER, Jay Scott
IPC分类号： H03K19/007 , H03K17/22 , G06F1/24
CPC分类号： H03K17/20 , G06F1/24 , H03K5/19 , H03K17/223

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