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1. 发明公开

EP3358747A3 LAYOUTS FOR XOR LOGIC 审中-公开
公开(公告)号：EP3358747A3
公开(公告)日：2018-11-14
申请号：EP17179613.9
申请日：2010-04-19
申请人： Tela Innovations, Inc.
发明人： BECKER, Scott T.
IPC分类号： H03K19/21 , G06F17/50 , H03K19/20
CPC分类号： H03K19/20 , G06F17/5068 , H03K19/215
摘要： An exclusive-or circuit includes a pass gate controlled by a second input node. The pass gate is connected to pass through a version of a logic state present at a first input node to an output node when so controlled. A transmission gate is controlled by the first input node. The transmission gate is connected to pass through a version of the logic state present at the second input node to the output node when so controlled. Pullup logic is controlled by both the first and second input nodes. The pullup logic is connected to drive the output node low when both the first and second input nodes are high. An exclusive-nor circuit is defined similar to the exclusive-or circuit, except that the pullup logic is replaced by pulldown logic which is connected to drive the output node high when both the first and second input nodes are high.

2. 发明公开

EP3244449A1 INTEGRATED CIRCUIT WITH SPARE CELLS 审中-公开
标题翻译：集成电路与备用电池
公开(公告)号：EP3244449A1
公开(公告)日：2017-11-15
申请号：EP16169589.5
申请日：2016-05-13
申请人： NXP USA, Inc.
发明人： Stahl, Andreas , Bode, Hubert Martin , Hatirnaz, Ilhan
IPC分类号： H01L27/02 , H01L27/118 , H03K19/173 , H03K19/177
CPC分类号： H03K19/0013 , H01L21/3213 , H01L21/823871 , H01L23/53271 , H01L27/0207 , H01L27/11807 , H01L2027/11835 , H01L2027/11866 , H01L2027/11875 , H03K19/00315 , H03K19/00392 , H03K19/1735 , H03K19/17764 , H03K19/215
摘要： The disclosure relates to an integrated circuit (50) comprising: a first voltage terminal (VDD); a second voltage terminal (VSS); and a plurality of logic cells (52), comprising one or more field effect transistors having a p-type channel and one or more field effect transistors having an n-type channel. The plurality of logic cells comprises a regular subset of cells (54) and a spare subset of cells (56). Electrical connectors (57, 58, 59) are arranged to: connect the gates of the regular subset of cells (54) in order to provide a functional logic arrangement; connect the gates of the one or more field effect transistors having a p-type channel of the spare subset of cells (56) to the first voltage terminal (VDD); and connect the gates of the one or more field effect transistors having an n-type channel of the spare subset of cells (56) to the second voltage terminal (VSS).
摘要翻译：本公开涉及一种集成电路（50），包括：第一电压端子（VDD）;第二电压端子第二电压端子（VSS）; 和多个逻辑单元（52），其包括具有p型沟道的一个或多个场效应晶体管和具有n型沟道的一个或多个场效应晶体管。多个逻辑单元包括单元（54）的常规子集和单元（56）的备用子集。电连接器（57,58,59）被布置为：连接单元（54）的规则子集的栅极以提供功能逻辑布置; 将具有单元（56）的备用子集的p型沟道的一个或多个场效应晶体管的栅极连接到第一电压端（VDD）; 并且将具有单元（56）的备用子集的n型沟道的一个或多个场效应晶体管的栅极连接到第二电压端子（VSS）。

3. 发明授权

EP3029840B1 LAYOUTS FOR XOR AND XNOR LOGIC 有权
标题翻译：用于XOR和XOR逻辑的布局
公开(公告)号：EP3029840B1
公开(公告)日：2017-07-05
申请号：EP16150261.2
申请日：2010-04-19
申请人： Tela Innovations, Inc.
发明人： BECKER, Scott T.
IPC分类号： H03K19/21 , G06F17/50 , H03K19/20
CPC分类号： H03K19/20 , G06F17/5068 , H03K19/215

4. 发明公开

EP2575257A1 Logic circuit and data processing system including the same 审中-公开
标题翻译： Logikschaltung和Datenverarbeitungssystem damit
公开(公告)号：EP2575257A1
公开(公告)日：2013-04-03
申请号：EP12186396.3
申请日：2012-09-27
申请人： Elpida Memory, Inc.
发明人： Nakamura, Yuki , Dono, Chiaki , Schneider, Ronny
IPC分类号： H03K19/21
CPC分类号： H03K19/215 , H03K19/21
摘要： Disclosed herein is a logic circuit that includes a transistor T1 coupled between VPERI and a node n1, a transistor T2 coupled between VPERI and a node n2, a transistor T3 coupled between VSS and a node n3, a transistor T4 coupled between VSS and a node n4, transistors T5 and T7 coupled in series between the nodes n1 and n3, transistors T9 and T11 coupled in series between the nodes n1 and n3, transistors T6 and T8 coupled in series between the nodes n2 and n4, and transistors T10 and T12 coupled in series between the nodes n2 and n4. An output signal Y is output from a connection point of the transistors T5 and T7 and a connection point of the transistors T6 and T8.
摘要翻译：这里公开了一种逻辑电路，其包括耦合在VPERI和节点n1之间的晶体管T1，耦合在VPERI和节点n2之间的晶体管T2，耦合在VSS和节点n3之间的晶体管T3，耦合在VSS和节点之间的晶体管T4 n4，在节点n1和n3之间串联耦合的晶体管T5和T7，串联耦合在节点n1和n3之间的晶体管T9和T11，串联耦合在节点n2和n4之间的晶体管T6和T8以及晶体管T10和T12耦合在节点n2和n4之间串联。输出信号Y从晶体管T5和T7的连接点和晶体管T6和T8的连接点输出。

5. 发明公开

EP2293448A2 Method and apparatus for an N-nary logic circuit 审中-公开
标题翻译： Verfahren und Vorrichtungfüreinen N-Nary logischer Stromkreis
公开(公告)号：EP2293448A2
公开(公告)日：2011-03-09
申请号：EP10179489.9
申请日：1999-12-10
申请人： Apple Inc.
发明人： Blomgren, James S. , Potter, Terence M. , Horne, Stephen C. , Seningen, Michael R. , Petro, Anthony M.
IPC分类号： H03K19/094 , H03K19/00 , H03K19/096
CPC分类号： G06F1/08 , G06F5/015 , G06F7/02 , G06F7/026 , G06F7/483 , G06F7/49 , G06F7/508 , G06F7/5443 , G06F17/5045 , G06F2207/3824 , G11C7/1006 , G11C8/00 , G11C8/10 , G11C8/16 , G11C8/18 , G11C11/418 , G11C11/419 , G11C11/56 , G11C19/00 , H03K19/0002 , H03K19/00346 , H03K19/00361 , H03K19/00384 , H03K19/0813 , H03K19/0963 , H03K19/215
摘要： The present invention is a method and apparatus (106) for an N-NARY logic circuit that uses N-NARY signals (A0-A3, B0-B3). The present invention includes a shared logic tree circuit (107) that evaluates one or more N-NARY input signals and produces an N-NARY output signal (V0-V3). The present invention additionally includes a first N-NARY input signal (A0-A3) coupled to the shared logic tree circuit and a second N-NARY input signal (B0-B3) coupled to the shared logic tree circuit. The shared logic circuit evaluates the first and second N-NARY input signal and produces an N-NARY output signal (V0-V3) coupled, which additionally couples to the shared logic tree circuit. The present invention uses signals that include 1 of 2 N-NARY signals, 1 of 3 N-NARY signals, 1 of 4 N-NARY signals (A0-A3, B0-B3), 1 of 8 N-NARY signals, and the general 1 of N N-NARY signals. The present invention evaluates any given function that includes the AND/NAND, OR/NOR, or XOR/Equivalence functions.
摘要翻译：本发明是一种使用N-NARY信号（A0-A3，B0-B3）的N-NARY逻辑电路的方法和装置（106）。本发明包括对一个或多个N-NARY输入信号进行评估并产生N-NARY个输出信号（V0-V3）的共享逻辑树电路（107）。本发明还包括耦合到共享逻辑树电路的第一N-NARY输入信号（A0-A3）和耦合到共享逻辑树电路的第二N-NARY输入信号（B0-B3）。共享逻辑电路评估第一和第二N-NARY输入信号并产生耦合的N-NARY输出信号（V0-V3），其另外耦合到共享逻辑树电路。本发明使用包括2个N-NARY信号中的1个，3个N-NARY信号中的1个，4个N-NARY个信号（A0-A3，B0-B3）中的1个，8个N-NARY个信号的1个，以及一般N N-NARY信号1。本发明评估包括AND / NAND，OR / NOR或异或/等效函数的任何给定函数。

6. 发明授权

EP1642388B1 DISPOSITIF DE COMPARAISON DE DEUX MOTS DE N BITS CHACUN 有权
标题翻译：装置用于比较两个每个N位字
公开(公告)号：EP1642388B1
公开(公告)日：2006-12-13
申请号：EP04767593.9
申请日：2004-07-06
申请人： ATMEL NANTES SA
发明人： COLOMA, Bernard
IPC分类号： H03K19/21
CPC分类号： G06F7/026 , H03K19/215
摘要： The invention relates to a device for comparing two words, N and P, of n bits each. The inventive device consists of at least one comparator block comprising n basic comparator blocks which can each be used to compare bits Ni and Pi of digit place i of words N and P, whereby 0 = i = n-1. Moreover, each basic comparator block comprises: a first sub-block which can be used to generate a first signal indicating whether or not bits Ni and Pi are equal, said signal being generated at the output of the sub-block forming a first output (OUT_XORi) of the basic comparator block; a second sub-block which can be used to generate a second signal indicating which of bits Ni and Pi is greater, said signal being generated at the output of the second sub-block; and a third sub-block which enables the second signal to pass to a second output (SOUTi) of the basic comparator block if the first signal indicates that bits Ni and Pi are not equal and which, in the opposite case, enables the second signal to be blocked. The comparator block also comprises: means for generating a third signal at a first output (OUT_XOR4_b) of the comparator block, indicating that numbers N and P are equal if the n first signals indicate same; and first selective passage means which can be used selectively to connect the second output (SOUTi) of a basic comparator block to a second output (OUT_COMP4) of the comparator block, whereby said basic comparator block, from among the basic comparator blocks having a second signal at the output thereof, processes the most significant bits. According to the invention, the signal present at the second output of the comparator block indicates which of the numbers, N or P, is greater.

7. 发明公开

EP1631892A1 MONITORING AND CONTROLLING POWER CONSUMPTION 审中-公开
标题翻译：监测和控制功耗
公开(公告)号：EP1631892A1
公开(公告)日：2006-03-08
申请号：EP04733410.7
申请日：2004-05-17
申请人： Koninklijke Philips Electronics N.V.
发明人： PINEDA DE GYVEZ, Jose, D., J. , RIUS VAZQUEZ, Josep
IPC分类号： G06F1/32 , H03K19/00 , H03K19/21
CPC分类号： H03K19/0016 , H03K19/215
摘要： The present invention relates to an electronic circuit, apparatus and method for monitoring and controlling power consumption. Accordingly, there is provided an electronic circuit, apparatus and method that includes one or more sequential logic elements (12) that are capable of receiving a clock signal (CLK) and an input signal (I) and providing an output signal (O). The sequential logic element (12) further comprises circuitry (20) for monitoring the input and output signals (I, O), and providing a control signal (CS) in response to the input and output signals (I, O), wherein the IC’s power consumption is operatively controllable in response to the control signal.

8. 发明公开

EP1475697A1 Arithmetic circuit 失效
标题翻译： Arithmetischer Schaltkreis
公开(公告)号：EP1475697A1
公开(公告)日：2004-11-10
申请号：EP04017604.2
申请日：1997-02-05
申请人： FUJITSU LIMITED
发明人： Goto, Gensuke
IPC分类号： G06F7/50 , G06F7/52 , H03K19/21
CPC分类号： G06F7/5318 , G06F7/509 , G06F7/5338 , H03K19/215
摘要： A multiplier circuit has an encoder (205; 12) and a partial product bit generating circuit (14). The encoder (205; 12) receives a multiplier bit signal (bj) and is used to output a plurality of encode signals. The partial product bit generating circuit (14) receives the encoded signals along with a multiplicand bit signal (ai, /ai) from each digit place and is used to generate a partial product bit for each digit place. The partial product bit generating circuit (14) has a first selection circuit (201, 203) which is used to select a logically true signal from among the encode signals in accordance with a value of the multiplicand bit signal. Therefore, the circuit can be reduced in size by reducing the number of necessary elements without sacrificing its high speed capability.
摘要翻译：乘法器电路具有编码器（205; 12）和部分乘积位产生电路（14）。编码器（205; 12）接收乘法器位信号（bj）并用于输出多个编码信号。部分积位产生电路（14）从每个数字位置接收编码信号以及被乘数位信号（ai，/ ai），并用于为每个数字位置产生部分乘积位。部分乘积位产生电路（14）具有第一选择电路（201,203），其用于根据被乘数位信号的值从编码信号中选择逻辑真实信号。因此，可以通过减少必要元件的数量而不牺牲其高速能力来减小电路的尺寸。

9. 发明公开

EP1168365A3 Negative-voltage bias circuit 失效
标题翻译：电路，用于产生一负偏压
公开(公告)号：EP1168365A3
公开(公告)日：2004-09-29
申请号：EP01117838.1
申请日：1992-12-09
申请人： FUJITSU LIMITED
发明人： Akaogi, Takao , Kawashima, Hiromi , Takeguchi, Tetsuji , Hagiwara, Ryoji , Kasa, Yasushi , Itano, Kiyoshi , Kawamura, Shouichi , Ogawa, Yasushige c/o Fujitsu VLSI Ltd.,
IPC分类号： G11C16/06 , H03K19/21 , G11C5/14 , G11C16/30
CPC分类号： G11C29/82 , G05F3/205 , G11C5/145 , G11C16/0416 , G11C16/08 , G11C16/16 , G11C16/30 , H03K3/356147 , H03K3/356165 , H03K19/018521 , H03K19/215
摘要： A negative-voltage bias circuit is provided which comprises: a capacitor (550) having first and second terminals (550B, 550A) ; a first p-channel MIS field-effect transistor (551) whose drain is connected to a negative-voltage output terminal (554) and whose gate and source are connected to the first terminal (550B) of the capacitor (550); and a second p-channel MIS field-effect transistor (552) whose drain is connected to the source of the first p-channel MIS field effect transistor (551), whose gate is connected to the negative-voltage output terminal (554), and whose source is provided with a negative voltage (V BB ). The first p-channel MIS field-effect transistor (551) is a depletion-type p-channel MIS field-effect transistor. In operation of the circuit, application to the second terminal (550A) of a series of clock pulses (CLK) causes a potential of the negative-voltage output terminal (554) to tend towards the negative voltage (V BB ).

10. 发明授权

EP0961290B1 Flash memory with improved erasability and its circuitry 有权
标题翻译：闪存具有更好的可擦及其电路
公开(公告)号：EP0961290B1
公开(公告)日：2001-11-14
申请号：EP99115180.4
申请日：1992-12-09
申请人： FUJITSU LIMITED
发明人： Akaogi, Takao , Kawashima, Hiromi , Takeguchi, Tetsuji , Hagiwara, Ryoji , Kasa, Yasushi , Itano, Kiyoshi , Kawamura, Shouichi , Ogawa, Yasushige
IPC分类号： G11C16/06 , H03K19/21 , G11C5/14
CPC分类号： G11C29/82 , G05F3/205 , G11C5/145 , G11C16/0416 , G11C16/08 , G11C16/16 , G11C16/30 , H03K3/356147 , H03K3/356165 , H03K19/018521 , H03K19/215
摘要： A negative-voltage bias circuit is provided which comprises: a capacitor (550) having first and second terminals (550B, 550A) ; a first p-channel MIS field-effect transistor (551) whose drain is connected to a negative-voltage output terminal (554) and whose gate and source are connected to the first terminal (550B) of the capacitor (550); and a second p-channel MIS field-effect transistor (552) whose drain is connected to the source of the first p-channel MIS field effect transistor (551), whose gate is connected to the negative-voltage output terminal (554), and whose source is provided with a negative voltage (VBB). The first p-channel MIS field-effect transistor (551) is a depletion-type p-channel MIS field-effect transistor. In operation of the circuit, application to the second terminal (550A) of a series of clock pulses (CLK) causes a potential of the negative-voltage output terminal (554) to tend towards the negative voltage (VBB).

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