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1. 发明授权

EP3198609B1 VOLTAGE LEVEL SHIFTED SELF-CLOCKED WRITE ASSISTANCE 有权
公开(公告)号：EP3198609B1
公开(公告)日：2018-11-21
申请号：EP15770996.5
申请日：2015-09-09
申请人： Qualcomm Incorporated
发明人： HOFF, David Paul , KULKARNI, Amey , MARTZLOFF, Jason Philip , LILES, Stephen Edward
IPC分类号： G11C11/419 , G11C5/14 , H03K3/356 , G11C7/12 , G11C7/10
CPC分类号： G11C7/12 , G11C5/14 , G11C7/1084 , G11C7/1093 , G11C7/1096 , G11C11/419 , H03K3/356104 , H03K3/35613 , H03K3/356139 , H03K3/356165 , H03K3/356173
摘要： Systems and methods for generating voltage level shifted self-clocked write assistance include a circuit with self-clocked true and complement data input signals in a first voltage domain. First and second full voltage level shifters are configured to generate voltage level shifted self-clocked intermediate true and complement signals in a second voltage domain, based on the self-clocked true and complement data input signals in the first voltage domain. Tristating logic including first and second complementary metal oxide semiconductor (CMOS) circuits are configured to generate voltage level shifted self-clocked tristated true and complement output signals used for providing write assistance for a memory array in the second voltage domain, based on the voltage level shifted self-clocked intermediate true and complements signals.

2. 发明授权

EP1901430B1 High speed level shifter 有权
标题翻译：高速电平转换器
公开(公告)号：EP1901430B1
公开(公告)日：2013-06-05
申请号：EP07114839.9
申请日：2007-08-23
申请人： STMicroelectronics International N.V.
发明人： Srivastava, Ankit , Jandial, Sourav
IPC分类号： H03K19/0185 , H03K3/356
CPC分类号： H03K19/018528 , H03K3/012 , H03K3/356165 , H03K3/356182

3. 发明公开

EP1168362A2 Flash memory with improved erasability and its circuitry 失效
标题翻译：闪光灯BessereLöschbarkeit和Schaltungen dazu
公开(公告)号：EP1168362A2
公开(公告)日：2002-01-02
申请号：EP01121238.8
申请日：1992-12-09
申请人： FUJITSU LIMITED
发明人： Akaogi, Takao , Kawashima, Hiromi , Takeguchi, Tetsuji , Hagiwara, Ryoji , Kasa, Yasushi , Itano, Kiyoshi , Kawamura, Shouichi , Ogawa, Yasushige
IPC分类号： G11C16/06
CPC分类号： G11C29/82 , G05F3/205 , G11C5/145 , G11C16/0416 , G11C16/08 , G11C16/16 , G11C16/30 , H03K3/356147 , H03K3/356165 , H03K19/018521 , H03K19/215
摘要： A flash memory comprises a cell matrix, in which rewritable nonvolatile memory cells (591ij) are arranged at intersections between a plurality of word lines (WLi) and a plurality of bit lines (BLi), and also comprises row decoders (587) for applying specified voltage selectively to the word lines (WLi) during writing or reading. The flash memory further comprises: switch circuits (590i) that are located between the cell matrix and the row decoder (587) in association with the word lines, and that enter a cutoff state when the word lines are set to negative voltage and enter a conducting state on any other occasion; negative-voltage bias circuits (592) whose negative-voltage output terminals (554) are connected to the word lines (WLi), and that apply the voltage output of a negative power supply to the word lines in response to a clock pulse (CLK) ; and clock pulse control circuits (593, 594) for causing the clock pulse (CLK) to be supplied to the negative-voltage bias circuit when it is detected during erasing that the word lines (WLi) are selected. The word lines (WLi) are divided into a plurality of groups and the clock pulse control circuits (593, 594) are operable to cause the clock pulse (CLK) to be supplied to each of the negative-voltage bias circuits connected to the selected word lines in a group when any word lines in the group are selected.
摘要翻译：闪存包括单元矩阵，其中可重写非易失性存储单元（591ij）布置在多个字线（WLi）和多个位线（BLi）之间的交叉处，并且还包括用于施加的行解码器（587）在写入或读取期间选择性地将字线（WLi）指定电压。闪存还包括：与字线相关联地位于单元矩阵和行解码器（587）之间的开关电路（590i），并且当字线被设置为负电压并进入在任何其他场合进行国家; 其负电压输出端子（554）连接到字线（WLi）的负电压偏置电路（592），并且响应于时钟脉冲（CLK）将负电源的电压输出施加到字线）; 以及时钟脉冲控制电路（593,594），用于当擦除字线（WLi）被选择时检测到时钟脉冲（CLK）被提供给负电压偏置电路。字线（WLi）被分成多个组，时钟脉冲控制电路（593,594）可操作以使时钟脉冲（CLK）被提供给连接到所选择的每个负电压偏置电路选择组中的任何字线时，组中的字线。

4. 发明授权

EP0570597B1 FLASH MEMORY IMPROVED IN ERASING CHARACTERISTIC, AND CIRCUIT THEREFOR 失效
标题翻译：具有改善的耐火特性及其电路闪存
公开(公告)号：EP0570597B1
公开(公告)日：2001-03-21
申请号：EP92924898.7
申请日：1992-12-09
申请人： FUJITSU LIMITED
发明人： AKAOGI, Takao Fujitsu Limited 1015, Kamikodanaka , KAWASHIMA, Hiromi Fujitsu Limited , TAKEGUCHI, Tetsuji Fujitsu Limited , HAGIWARA, Ryoji Fujitsu Limited , KASA, Yasushi Fujitsu Limited 1015, Kamikodanaka , ITANO, Kiyoshi Fujitsu Limited 1015, Kamikodanaka , OGAWA, Yasushige Fujitsu VLSI Limited , KAWAMURA, Shouichi Fujitsu Limited
IPC分类号： G11C16/06 , H03K19/21 , G11C5/14
CPC分类号： G11C29/82 , G05F3/205 , G11C5/145 , G11C16/0416 , G11C16/08 , G11C16/16 , G11C16/30 , H03K3/356147 , H03K3/356165 , H03K19/018521 , H03K19/215
摘要： A negative-voltage bias circuit is provided which comprises: a capacitor (550) having first and second terminals (550B, 550A) ; a first p-channel MIS field-effect transistor (551) whose drain is connected to a negative-voltage output terminal (554) and whose gate and source are connected to the first terminal (550B) of the capacitor (550); and a second p-channel MIS field-effect transistor (552) whose drain is connected to the source of the first p-channel MIS field effect transistor (551), whose gate is connected to the negative-voltage output terminal (554), and whose source is provided with a negative voltage (VBB). The first p-channel MIS field-effect transistor (551) is a depletion-type p-channel MIS field-effect transistor. In operation of the circuit, application to the second terminal (550A) of a series of clock pulses (CLK) causes a potential of the negative-voltage output terminal (554) to tend towards the negative voltage (VBB).

5. 发明公开

EP0944094A2 Flash memory with improved erasability and its circuitry 失效
标题翻译： Flash-Speicher mit BessererLöschbarkeitund seine Schaltung
公开(公告)号：EP0944094A2
公开(公告)日：1999-09-22
申请号：EP99110956.2
申请日：1999-06-08
申请人： FUJITSU LIMITED
发明人： Akaogi, Takao, Fujitsu Limited , Kawashima, Hiromi, Fujitsu Limited , Takeguchi, Tetsuji, Fujitsu Limited , Hagiwara, Ryoji, Fujitsu Limited , Kasa, Yasushi, Fujitsu Limited , Itano, Kiyoshi, Fujitsu Limited , Kawamura, Shouichi, Fujitsu Limited , Ogawa, Yasushige, Fujitsu VLSI Limited
IPC分类号： G11C16/06
CPC分类号： G11C29/82 , G05F3/205 , G11C5/145 , G11C16/0416 , G11C16/08 , G11C16/16 , G11C16/30 , H03K3/356147 , H03K3/356165 , H03K19/018521 , H03K19/215
摘要： An internal power switching circuit for a semiconductor memory comprises: a first n-channel MIS transistor (704) one of whose drain and source electrodes is connected to a first power line (701) and the other of whose drain and source electrodes is connected to a second power line (702); a second p-channel MIS transistor (705) one of whose drain and source electrodes, and whose well are connected to a third power line (703) the voltage (Vpp) of which is higher than the voltage (Vcc) on said first power line (701), and the other of whose drain and source electrodes is connected to a node (n70); and a third p-channel MIS transistor (706) one of whose drain and source electrodes is connected to said node (n70), and the other of whose drain and source electrodes, and whose well are connected to said second power line (702) ; and a fourth n-channel MIS transistor (707) one of whose drain and source electrodes is connected to said third power line (703) and the other of whose drain and source electrodes is connected to said second power line (702).
Such an internal power switching circuit can operate at a high speed with simple circuitry.
摘要翻译：一种用于半导体存储器的内部功率开关电路包括：第一n沟道MIS晶体管（704），其漏极和源极之一连接到第一电力线（701），另一个漏极和源极连接到第二电力线（702）; 第二p沟道MIS晶体管（705），其漏极和源极之一并且其阱连接到第三电力线（703），其电压（Vpp）高于所述第一功率上的电压（Vcc）线（701），其另一个漏极和源极连接到节点（n70）; 以及第三p沟道MIS晶体管（706），其漏极和源极之一连接到所述节点（n70），并且漏极和源极中的另一个与阱连接到所述第二电力线（702） ; 以及第四n沟道MIS晶体管（707），其漏极和源极电极之一连接到所述第三电力线（703），并且其漏极和源极电极中的另一个连接到所述第二电力线（702）。这种内部功率开关电路可以通过简单的电路以高速运行。

6. 发明公开

EP3304736A1 VOLTAGE LEVEL SHIFTERS EMPLOYING PRECONDITIONING CIRCUITS, AND RELATED SYSTEMS AND METHODS 有权
标题翻译：采用预定电路的电压电平转换器及相关系统和方法
公开(公告)号：EP3304736A1
公开(公告)日：2018-04-11
申请号：EP16724812.9
申请日：2016-05-12
申请人： Qualcomm Incorporated
发明人： NADKARNI, Rahul, Krishnakumar , LILES, Stephen, Edward , GARG, Manish
IPC分类号： H03K3/012 , H03K3/356
CPC分类号： H03K19/018521 , H03K3/012 , H03K3/356165
摘要： Voltage level shifters employing preconditioning circuits are disclosed. Related systems and methods are also disclosed. In one aspect, voltage level shifter is configured to generate a voltage level shifted non-complement output signal and complement output signal corresponding to non-complement input signal and complement input signal, respectively. First pull-up circuit is configured to generate complement output signal in response to non-complement input signal transitioning to logic low voltage. First pull-down circuit is configured to generate non-complement output signal in response to complement input signal transitioning to logic high voltage. First preconditioning circuit is configured to receive non-complement and complement output signals and generate and provide shifted voltage signal to complement output in response to non-complement output signal transitioning to logic low voltage. This allows the complement output signal to transition to the shifted voltage more quickly.

7. 发明公开

EP3198609A1 VOLTAGE LEVEL SHIFTED SELF-CLOCKED WRITE ASSISTANCE 有权
标题翻译：电压电平移位自锁定写辅助
公开(公告)号：EP3198609A1
公开(公告)日：2017-08-02
申请号：EP15770996.5
申请日：2015-09-09
申请人： Qualcomm Incorporated
发明人： HOFF, David Paul , KULKARNI, Amey , MARTZLOFF, Jason Philip , LILES, Stephen Edward
IPC分类号： G11C11/419 , G11C7/12 , G11C5/14 , G11C7/10 , H03K19/017
CPC分类号： G11C7/12 , G11C5/14 , G11C7/1084 , G11C7/1093 , G11C7/1096 , G11C11/419 , H03K3/356104 , H03K3/35613 , H03K3/356139 , H03K3/356165 , H03K3/356173
摘要： Systems and methods for generating voltage level shifted self-clocked write assistance include a circuit with self-clocked true and complement data input signals in a first voltage domain. First and second full voltage level shifters are configured to generate voltage level shifted self-clocked intermediate true and complement signals in a second voltage domain, based on the self-clocked true and complement data input signals in the first voltage domain. Tristating logic including first and second complementary metal oxide semiconductor (CMOS) circuits are configured to generate voltage level shifted self-clocked tristated true and complement output signals used for providing write assistance for a memory array in the second voltage domain, based on the voltage level shifted self-clocked intermediate true and complements signals.
摘要翻译：用于产生电压电平移动的自时钟写入辅助的系统和方法包括在第一电压域中具有自时钟的真和补数据输入信号的电路。第一和第二全电压电平移位器被配置为基于第一电压域中的自时钟的真和补数据输入信号在第二电压域中产生电压电平移位的自时钟中间真和补数信号。包括第一互补金属氧化物半导体（CMOS）电路和第二互补金属氧化物半导体（CMOS）电路的三态逻辑被配置为基于电压电平产生用于为第二电压域中的存储器阵列提供写入辅助的电压电平偏移的自时钟三态真和互补输出信号移动自时钟中间真实和补充信号。

8. 发明公开

EP1184983A1 Interface latch for data level transfer 有权
标题翻译： SchnittstellenverriegelungfürDatenpegelübertragung
公开(公告)号：EP1184983A1
公开(公告)日：2002-03-06
申请号：EP00830595.5
申请日：2000-08-31
申请人： STMicroelectronics S.r.l.
发明人： Adduci, Francesco , Bona, Claudio , Fassina, Andrea
IPC分类号： H03K3/356 , H03K17/10 , H03K19/003 , H03K19/007
CPC分类号： H03K3/356113 , H03K3/356165 , H03K17/102 , H03K19/003 , H03K19/007
摘要： The invention comprises an interface for translating data of different voltages. It includes an input terminal (52) structured to accept an input from a circuit supplied by a power supply having a first voltage level, as well as an output terminal structured to provide an output from the interface. A first circuit portion is powered by a power supply having the first voltage level (SUPPLYLOW). A second circuit portion is powered by a power supply having a second voltage level (SUPPLYHIGH). The invention advantageously comprises a power supply detection circuit (M20, M21) structured to accept a detection signal (VCCOFF). This detection circuit is coupled to the first and second circuit portions and structured to maintain a correct output at the output terminal (62) even after the power supply having the first voltage level (SUPPLYLOW) no longer supplies the first voltage level to the interface.
摘要翻译：本发明包括用于转换不同电压的数据的接口。它包括一个输入端（52），其被构造为接受来自由具有第一电压电平的电源提供的电路的输入，以及被构造成提供来自该接口的输出的输出端。第一电路部分由具有第一电压电平（SUPPLYLOW）的电源供电。第二电路部分由具有第二电压电平（SUPPLYHIGH）的电源供电。本发明有利地包括被构造为接受检测信号（VCCOFF）的电源检测电路（M20，M21）。即使在具有第一电压电平（SUPPLYLOW）的电源不再向接口提供第一电压电平之后，该检测电路耦合到第一和第二电路部分并被构造为在输出端子（62）处保持正确的输出。

9. 发明公开

EP0961289A2 Flash memory with improved erasability and its circuitry 失效
标题翻译：具有改进的可擦除性和电路的闪存
公开(公告)号：EP0961289A2
公开(公告)日：1999-12-01
申请号：EP99115179.6
申请日：1992-12-09
申请人： FUJITSU LIMITED
发明人： Akaogi, Takao , Kawashima, Hiromi , Takeguchi, Tetsuji , Hagiwara, Ryoji , Kasa, Yasushi , Itano, Kiyoshi , Kawamura, Shouichi , Ogawa, Yasushige
IPC分类号： G11C16/06
CPC分类号： G11C29/82 , G05F3/205 , G11C5/145 , G11C16/0416 , G11C16/08 , G11C16/16 , G11C16/30 , H03K3/356147 , H03K3/356165 , H03K19/018521 , H03K19/215
摘要： A flash memory which includes a memory cell array (271) in which a plurality of nonvolatile memory cells that can be erased electrically are set in array and decoding units (273) that decode a plurality of signals and access said memory cell array (271), further comprises: drive units (274) each of which includes a first power terminal (275) and a second power terminal (276), inputs the output of the decoding unit (273), and selectively outputs a voltage applied to the first power terminal (275) or a voltage approximate to that voltage, and a voltage applied to the second power terminal or a voltage approximate to that voltage; the drive unit (274) assuming a first operation mode, in which a first voltage is applied to the first power terminal (275) and a second voltage that is lower than the first voltage is applied to the second power terminal (276), and a second operation mode, in which a third voltage is applied to the first power terminal (275) and a fourth voltage that is higher than the third voltage is applied to the second power terminal (276); and selecting an output voltage depending on whether the first or second operation mode is specified.
摘要翻译：一种闪速存储器，其包括：存储单元阵列（271），其中可以电擦除的多个非易失性存储单元被设置在阵列中，并且解码多个信号并访问所述存储单元阵列（271）的解码单元（273）还包括：各包括第一电源端子（275）和第二电源端子（276）的驱动单元（274），输入解码单元（273）的输出，并且选择性地输出施加到第一电源端子（275）或接近该电压的电压以及施加到第二电源端子的电压或接近该电压的电压; 驱动单元（274）呈现第一操作模式，其中向第一电源端子（275）施加第一电压并且向第二电源端子（276）施加低于第一电压的第二电压，以及以及第二操作模式，其中向所述第一电源端子（275）施加第三电压，并且向所述第二电源端子（276）施加高于所述第三电压的第四电压; 并根据是否指定第一或第二操作模式来选择输出电压。

10. 发明公开

EP0926825A2 Static latch circuit and static logic circuit 审中-公开
标题翻译： Statische Verriegelungsschaltung und statischer Logikschaltkreis
公开(公告)号：EP0926825A2
公开(公告)日：1999-06-30
申请号：EP98124596.2
申请日：1998-12-23
申请人： NEC CORPORATION
发明人： Kanno, Hiroshi
IPC分类号： H03K3/356 , H03K19/017
CPC分类号： H03K3/356165 , H03K19/0016
摘要： A static latch circuit and a static logic circuit can be easily designed without gate width and gate length optimization while using transistors with the smallest usable gate width to reduce power consumption. The resulting static latch circuit and static logic circuit can be used in applications where all gate lengths must be the same. The drive capacity of parts associated with the static holding function of the latch circuit and logic circuit is reduced by using a step-down circuit and step-up circuit to reduce the effective supply voltage during operation.
摘要翻译：可以容易地设计静态锁存电路和静态逻辑电路，而不需要栅极宽度和栅极长度优化，同时使用具有最小可用栅极宽度的晶体管来降低功耗。所产生的静态锁存电路和静态逻辑电路可用于所有栅极长度必须相同的应用中。通过使用降压电路和升压电路来减少与锁存电路和逻辑电路的静态保持功能相关的部件的驱动能力，以降低操作期间的有效电源电压。

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