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1. 发明公开

EP1168362A2 Flash memory with improved erasability and its circuitry 失效
标题翻译：闪光灯BessereLöschbarkeit和Schaltungen dazu
公开(公告)号：EP1168362A2
公开(公告)日：2002-01-02
申请号：EP01121238.8
申请日：1992-12-09
申请人： FUJITSU LIMITED
发明人： Akaogi, Takao , Kawashima, Hiromi , Takeguchi, Tetsuji , Hagiwara, Ryoji , Kasa, Yasushi , Itano, Kiyoshi , Kawamura, Shouichi , Ogawa, Yasushige
IPC分类号： G11C16/06
CPC分类号： G11C29/82 , G05F3/205 , G11C5/145 , G11C16/0416 , G11C16/08 , G11C16/16 , G11C16/30 , H03K3/356147 , H03K3/356165 , H03K19/018521 , H03K19/215
摘要： A flash memory comprises a cell matrix, in which rewritable nonvolatile memory cells (591ij) are arranged at intersections between a plurality of word lines (WLi) and a plurality of bit lines (BLi), and also comprises row decoders (587) for applying specified voltage selectively to the word lines (WLi) during writing or reading. The flash memory further comprises: switch circuits (590i) that are located between the cell matrix and the row decoder (587) in association with the word lines, and that enter a cutoff state when the word lines are set to negative voltage and enter a conducting state on any other occasion; negative-voltage bias circuits (592) whose negative-voltage output terminals (554) are connected to the word lines (WLi), and that apply the voltage output of a negative power supply to the word lines in response to a clock pulse (CLK) ; and clock pulse control circuits (593, 594) for causing the clock pulse (CLK) to be supplied to the negative-voltage bias circuit when it is detected during erasing that the word lines (WLi) are selected. The word lines (WLi) are divided into a plurality of groups and the clock pulse control circuits (593, 594) are operable to cause the clock pulse (CLK) to be supplied to each of the negative-voltage bias circuits connected to the selected word lines in a group when any word lines in the group are selected.
摘要翻译：闪存包括单元矩阵，其中可重写非易失性存储单元（591ij）布置在多个字线（WLi）和多个位线（BLi）之间的交叉处，并且还包括用于施加的行解码器（587）在写入或读取期间选择性地将字线（WLi）指定电压。闪存还包括：与字线相关联地位于单元矩阵和行解码器（587）之间的开关电路（590i），并且当字线被设置为负电压并进入在任何其他场合进行国家; 其负电压输出端子（554）连接到字线（WLi）的负电压偏置电路（592），并且响应于时钟脉冲（CLK）将负电源的电压输出施加到字线）; 以及时钟脉冲控制电路（593,594），用于当擦除字线（WLi）被选择时检测到时钟脉冲（CLK）被提供给负电压偏置电路。字线（WLi）被分成多个组，时钟脉冲控制电路（593,594）可操作以使时钟脉冲（CLK）被提供给连接到所选择的每个负电压偏置电路选择组中的任何字线时，组中的字线。

2. 发明公开

EP0841667A2 Flash-erasable semiconductor memory device having an improved reliability 失效
标题翻译： Flash-löschbareHalbleiterspeicheranordnung mit verbesserterZuverlässigkeit
公开(公告)号：EP0841667A2
公开(公告)日：1998-05-13
申请号：EP97119754.6
申请日：1992-11-20
申请人： FUJITSU LIMITED , FUJITSU VLSI LIMITED
发明人： Akaogi, Takao , Ogawa, Yasushige , Kajita, Tatsuya , Watanabe, Hisayoshi , Yamashita. Minoru
IPC分类号： G11C16/06
CPC分类号： H01L27/11526 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/846 , H01L27/105 , H01L27/115 , H01L27/11543
摘要： A flash-erasable semiconductor memory device comprises a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on said floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.
摘要翻译：闪存可擦除半导体存储器件包括存储单元阵列，其包括多个存储单元晶体管，每个存储单元晶体管具有用于存储信息的绝缘浮动栅极和设置在所述浮置栅极上的控制电极，其中闪存可擦除半导体存储器件包括写入控制电路提供写控制信号时，写信息。写入控制电路产生控制信号，使得漏极控制信号的前沿出现在栅极控制信号的前沿之后。此外，栅极控制电路关闭栅极控制信号，使得栅极控制信号的后沿出现在漏极控制信号的后沿之后。

3. 发明授权

EP0961290B1 Flash memory with improved erasability and its circuitry 失效
标题翻译：闪存具有更好的可擦及其电路
公开(公告)号：EP0961290B1
公开(公告)日：2001-11-14
申请号：EP99115180.4
申请日：1992-12-09
申请人： FUJITSU LIMITED
发明人： Akaogi, Takao , Kawashima, Hiromi , Takeguchi, Tetsuji , Hagiwara, Ryoji , Kasa, Yasushi , Itano, Kiyoshi , Kawamura, Shouichi , Ogawa, Yasushige
IPC分类号： G11C16/06 , H03K19/21 , G11C5/14
CPC分类号： G11C29/82 , G05F3/205 , G11C5/145 , G11C16/0416 , G11C16/08 , G11C16/16 , G11C16/30 , H03K3/356147 , H03K3/356165 , H03K19/018521 , H03K19/215
摘要： A negative-voltage bias circuit is provided which comprises: a capacitor (550) having first and second terminals (550B, 550A) ; a first p-channel MIS field-effect transistor (551) whose drain is connected to a negative-voltage output terminal (554) and whose gate and source are connected to the first terminal (550B) of the capacitor (550); and a second p-channel MIS field-effect transistor (552) whose drain is connected to the source of the first p-channel MIS field effect transistor (551), whose gate is connected to the negative-voltage output terminal (554), and whose source is provided with a negative voltage (VBB). The first p-channel MIS field-effect transistor (551) is a depletion-type p-channel MIS field-effect transistor. In operation of the circuit, application to the second terminal (550A) of a series of clock pulses (CLK) causes a potential of the negative-voltage output terminal (554) to tend towards the negative voltage (VBB).

4. 发明公开

EP0841667A3 Flash-erasable semiconductor memory device having an improved reliability 失效
标题翻译：具有改善的可靠性的Flash可擦除半导体存储装置
公开(公告)号：EP0841667A3
公开(公告)日：1999-06-16
申请号：EP97119754.6
申请日：1992-11-20
申请人： FUJITSU LIMITED , FUJITSU VLSI LIMITED
发明人： Akaogi, Takao , Ogawa, Yasushige , Kajita, Tatsuya , Watanabe, Hisayoshi , Yamashita. Minoru
IPC分类号： G11C16/06
CPC分类号： H01L27/11526 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/846 , H01L27/105 , H01L27/115 , H01L27/11543
摘要： A flash-erasable semiconductor memory device comprises a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on said floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.

5. 发明授权

EP1126473B1 Semiconductor memory device 失效
标题翻译：半导体存储装置
公开(公告)号：EP1126473B1
公开(公告)日：2004-02-18
申请号：EP01109362.2
申请日：1992-11-20
申请人： FUJITSU LIMITED , FUJITSU VLSI LIMITED
发明人： Akaogi, Takao , Ogawa, Yasushige
IPC分类号： G11C16/08 , G11C16/16 , G06F11/20
CPC分类号： H01L27/11526 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/846 , H01L27/105 , H01L27/115 , H01L27/11543

6. 发明公开

EP1126472A1 Flash-erasable semiconductor memory device 失效
标题翻译： LöschbareFlash-Halbleiterspeichervorrichtung
公开(公告)号：EP1126472A1
公开(公告)日：2001-08-22
申请号：EP01109361.4
申请日：1992-11-20
申请人： FUJITSU LIMITED , FUJITSU VLSI LIMITED
发明人： Akaogi, Takao , Ogawa, Yasushige
IPC分类号： G11C16/08 , G11C16/16 , G06F11/20
CPC分类号： H01L27/11526 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/846 , H01L27/105 , H01L27/115 , H01L27/11543
摘要： A flash-erasable semiconductor memory device comprising: a memory cell array including a plurality of memory cell transistors, each of said memory cell transistors comprising: an insulated floating gate provided on a semiconductor substrate with a separation therefrom for storing information in the form of electric charges; a gate insulation film provided on an upper major surface of said semiconductor substrate for separating said floating gate from said semiconductor substrate; a channel region defined in said semiconductor substrate in correspondence to said floating gate electrode; a source region and a drain region defined in said semiconductor substrate at both sides of said floating gate, said source region injecting carriers into said channel region such that said carriers are transported along said channel region while said drain region collecting carriers that have been injected into said channel region at said source region and transported through said channel region, and a control electrode provided on said floating gate with a separation therefrom by said capacitor insulation film for controlling an injection of carriers from said channel region to said floating gate via said gate insulation film; addressing means supplied with address data for selecting a memory cell transistor in said memory cell array; writing means for writing information into said selected memory cell transistor; reading means for reading information from said selected memory cell transistor; and erasing means for erasing information from a plurality of memory cell transistors included in said memory cell array simultaneously, said erasing means erasing information by removing electric charges from said floating gate electrodes of said memory cell transistors by causing to flow a tunneling current through said gate insulation film; said memory cell array comprising a first memory cell array that includes a plurality of bit lines and a second memory cell array that includes also a plurality of bit lines, said source region of said plurality of memory cell transistors in said first and second memory cell arrays being connected, when erasing information, commonly to said erasing means for simultaneous erasing; said addressing means comprising a first addressing unit supplied with said address data for selecting a bit line in said first memory cell array and a second addressing unit supplied with said address data for selecting a bit line in said second memory cell array; address control means supplied with said address data for enabling one of said first and second addressing units while disabling the other of said first and second addressing units in response to said address data; and overriding means supplied with a control signal for selectively enabling one of said first and second addressing units in response to a first state of said control signal and for selectively enabling the other of said first and second addressing units in response to a second state of said control signal.
摘要翻译：一种闪存可擦除半导体存储器件，包括：包括多个存储单元晶体管的存储单元阵列，每个所述存储单元晶体管包括：设置在半导体衬底上的绝缘浮置栅极，用于存储电子形式的信息收费; 栅极绝缘膜，设置在所述半导体衬底的上主表面上，用于将所述浮置栅极与所述半导体衬底分离; 对应于所述浮栅电极限定在所述半导体衬底中的沟道区; 在所述浮置栅极的两侧限定在所述半导体衬底中的源极区域和漏极区域，所述源极区域将载流子注入到所述沟道区域中，使得所述载流子沿着所述沟道区域传输，而所述漏极区域收集载流子被注入所述沟道区域在所述源极区域被传送通过所述沟道区域，以及控制电极，所述控制电极通过所述电容器绝缘膜与所述浮动栅极分开设置，用于控制载流子从所述沟道区域经由所述栅极绝缘体从所述沟道区域注入所述浮置栅极电影; 提供有用于选择所述存储单元阵列中的存储单元晶体管的地址数据的寻址装置; 用于将信息写入所述选择的存储单元晶体管的写入装置; 用于从所述选择的存储单元晶体管读取信息的读取装置; 以及用于同时从包括在所述存储单元阵列中的多个存储单元晶体管擦除信息的擦除装置，所述擦除装置通过使隧道电流流过所述栅极而从所述存储单元晶体管的所述浮置栅电极去除电荷来擦除信息，绝缘膜; 所述存储单元阵列包括包括多个位线的第一存储单元阵列和还包括多个位线的第二存储单元阵列，所述第一和第二存储单元阵列中的所述多个存储单元晶体管的所述源极区当擦除信息时，通常连接到用于同时擦除的所述擦除装置; 所述寻址装置包括提供有用于选择所述第一存储单元阵列中的位线的所述地址数据的第一寻址单元和提供有用于选择所述第二存储单元阵列中的位线的所述地址数据的第二寻址单元; 提供有所述地址数据的地址控制装置，用于启用所述第一和第二寻址单元之一，同时响应于所述地址数据禁用所述第一和第二寻址单元中的另一个; 以及提供有控制信号的覆盖装置，用于响应于所述控制信号的第一状态选择性地使得所述第一和第二寻址单元之一响应于所述第一和第二寻址单元中的另一个响应所述第一和第二寻址单元的第二状态控制信号。

7. 发明公开

EP0961289A2 Flash memory with improved erasability and its circuitry 失效
标题翻译：具有改进的可擦除性和电路的闪存
公开(公告)号：EP0961289A2
公开(公告)日：1999-12-01
申请号：EP99115179.6
申请日：1992-12-09
申请人： FUJITSU LIMITED
发明人： Akaogi, Takao , Kawashima, Hiromi , Takeguchi, Tetsuji , Hagiwara, Ryoji , Kasa, Yasushi , Itano, Kiyoshi , Kawamura, Shouichi , Ogawa, Yasushige
IPC分类号： G11C16/06
CPC分类号： G11C29/82 , G05F3/205 , G11C5/145 , G11C16/0416 , G11C16/08 , G11C16/16 , G11C16/30 , H03K3/356147 , H03K3/356165 , H03K19/018521 , H03K19/215
摘要： A flash memory which includes a memory cell array (271) in which a plurality of nonvolatile memory cells that can be erased electrically are set in array and decoding units (273) that decode a plurality of signals and access said memory cell array (271), further comprises: drive units (274) each of which includes a first power terminal (275) and a second power terminal (276), inputs the output of the decoding unit (273), and selectively outputs a voltage applied to the first power terminal (275) or a voltage approximate to that voltage, and a voltage applied to the second power terminal or a voltage approximate to that voltage; the drive unit (274) assuming a first operation mode, in which a first voltage is applied to the first power terminal (275) and a second voltage that is lower than the first voltage is applied to the second power terminal (276), and a second operation mode, in which a third voltage is applied to the first power terminal (275) and a fourth voltage that is higher than the third voltage is applied to the second power terminal (276); and selecting an output voltage depending on whether the first or second operation mode is specified.
摘要翻译：一种闪速存储器，其包括：存储单元阵列（271），其中可以电擦除的多个非易失性存储单元被设置在阵列中，并且解码多个信号并访问所述存储单元阵列（271）的解码单元（273）还包括：各包括第一电源端子（275）和第二电源端子（276）的驱动单元（274），输入解码单元（273）的输出，并且选择性地输出施加到第一电源端子（275）或接近该电压的电压以及施加到第二电源端子的电压或接近该电压的电压; 驱动单元（274）呈现第一操作模式，其中向第一电源端子（275）施加第一电压并且向第二电源端子（276）施加低于第一电压的第二电压，以及以及第二操作模式，其中向所述第一电源端子（275）施加第三电压，并且向所述第二电源端子（276）施加高于所述第三电压的第四电压; 并根据是否指定第一或第二操作模式来选择输出电压。

8. 发明公开

EP1168362A3 Flash memory with improved erasability and its circuitry 失效
标题翻译：闪存具有更好的可擦和电路
公开(公告)号：EP1168362A3
公开(公告)日：2004-09-29
申请号：EP01121238.8
申请日：1992-12-09
申请人： FUJITSU LIMITED
发明人： Akaogi, Takao , Kawashima, Hiromi , Takeguchi, Tetsuji , Hagiwara, Ryoji , Kasa, Yasushi , Itano, Kiyoshi , Kawamura, Shouichi , Ogawa, Yasushige
IPC分类号： G11C16/06 , H03K19/21 , G11C5/14
CPC分类号： G11C29/82 , G05F3/205 , G11C5/145 , G11C16/0416 , G11C16/08 , G11C16/16 , G11C16/30 , H03K3/356147 , H03K3/356165 , H03K19/018521 , H03K19/215
摘要： A flash memory comprises a cell matrix, in which rewritable nonvolatile memory cells (591ij) are arranged at intersections between a plurality of word lines (WLi) and a plurality of bit lines (BLi), and also comprises row decoders (587) for applying specified voltage selectively to the word lines (WLi) during writing or reading. The flash memory further comprises: switch circuits (590i) that are located between the cell matrix and the row decoder (587) in association with the word lines, and that enter a cutoff state when the word lines are set to negative voltage and enter a conducting state on any other occasion; negative-voltage bias circuits (592) whose negative-voltage output terminals (554) are connected to the word lines (WLi), and that apply the voltage output of a negative power supply to the word lines in response to a clock pulse (CLK) ; and clock pulse control circuits (593, 594) for causing the clock pulse (CLK) to be supplied to the negative-voltage bias circuit when it is detected during erasing that the word lines (WLi) are selected. The word lines (WLi) are divided into a plurality of groups and the clock pulse control circuits (593, 594) are operable to cause the clock pulse (CLK) to be supplied to each of the negative-voltage bias circuits connected to the selected word lines in a group when any word lines in the group are selected.

9. 发明授权

EP0961289B1 Flash memory with improved erasability and its circuitry 失效
标题翻译：闪存具有更好的可擦及其电路
公开(公告)号：EP0961289B1
公开(公告)日：2002-10-02
申请号：EP99115179.6
申请日：1992-12-09
申请人： FUJITSU LIMITED
发明人： Akaogi, Takao , Kawashima, Hiromi , Takeguchi, Tetsuji , Hagiwara, Ryoji , Kasa, Yasushi , Itano, Kiyoshi , Kawamura, Shouichi , Ogawa, Yasushige
IPC分类号： G11C16/06 , H03K19/21 , G11C5/14
CPC分类号： G11C29/82 , G05F3/205 , G11C5/145 , G11C16/0416 , G11C16/08 , G11C16/16 , G11C16/30 , H03K3/356147 , H03K3/356165 , H03K19/018521 , H03K19/215
摘要： A negative-voltage bias circuit is provided which comprises: a capacitor (550) having first and second terminals (550B, 550A) ; a first p-channel MIS field-effect transistor (551) whose drain is connected to a negative-voltage output terminal (554) and whose gate and source are connected to the first terminal (550B) of the capacitor (550); and a second p-channel MIS field-effect transistor (552) whose drain is connected to the source of the first p-channel MIS field effect transistor (551), whose gate is connected to the negative-voltage output terminal (554), and whose source is provided with a negative voltage (VBB). The first p-channel MIS field-effect transistor (551) is a depletion-type p-channel MIS field-effect transistor. In operation of the circuit, application to the second terminal (550A) of a series of clock pulses (CLK) causes a potential of the negative-voltage output terminal (554) to tend towards the negative voltage (VBB).

10. 发明授权

EP0841667B1 Flash-erasable semiconductor memory device having an improved reliability 失效
标题翻译：具有改善的可靠性的Flash可擦除半导体存储装置
公开(公告)号：EP0841667B1
公开(公告)日：2002-03-06
申请号：EP97119754.6
申请日：1992-11-20
申请人： FUJITSU LIMITED , FUJITSU VLSI LIMITED
发明人： Akaogi, Takao , Ogawa, Yasushige , Kajita, Tatsuya , Watanabe, Hisayoshi , Yamashita. Minoru
IPC分类号： G11C16/06
CPC分类号： H01L27/11526 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/846 , H01L27/105 , H01L27/115 , H01L27/11543

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