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1. 发明授权

EP2020085B1 FAULT TOLERANT ASYNCHRONOUS CIRCUITS 有权
标题翻译：容错的异步电路
公开(公告)号：EP2020085B1
公开(公告)日：2017-11-08
申请号：EP07761447.7
申请日：2007-04-27
申请人： Achronix Semiconductor Corp.
发明人： MANOHAR, Rajit , KELLY, Clinton W.
IPC分类号： H03K19/003 , H03K19/20 , H03K19/007 , G11C11/412
CPC分类号： G11C11/4125 , H03K19/00338 , H03K19/007 , H03K19/20

2. 发明授权

EP2816766B1 Communication apparatus with feedback 有权
标题翻译：与反馈通信设备
公开(公告)号：EP2816766B1
公开(公告)日：2017-01-25
申请号：EP14172680.2
申请日：2014-06-17
申请人： NXP B.V.
发明人： Deloge, Matthieu , Van Der Wel, Arnoud
IPC分类号： H04L25/02 , G06F13/38 , G06F13/40 , H03K5/01 , H03K19/003 , H03K19/0175 , H04L25/08
CPC分类号： G06F13/4072 , G06F13/385 , H03K19/00338 , H03K19/00369 , H04L25/028 , H04L25/0286 , H04L25/08

3. 发明公开

EP2020085A4 FAULT TOLERANT ASYNCHRONOUS CIRCUITS 有权
标题翻译： FEHLERTOLERANTE ASYNCHRONE SCHALTUNGEN
公开(公告)号：EP2020085A4
公开(公告)日：2011-04-27
申请号：EP07761447
申请日：2007-04-27
申请人： ACHRONIX SEMICONDUCTOR CORP
发明人： MANOHAR RAJIT , KELLY CLINTON W
IPC分类号： H03K19/003 , G11C11/412 , H03K19/007 , H03K19/20
CPC分类号： G11C11/4125 , H03K19/00338 , H03K19/007 , H03K19/20

4. 发明公开

EP2107679A2 Single-event-effect tolerant SOI-based logic device 审中-公开
标题翻译：单事件容忍性，SOI基准测试Gerät
公开(公告)号：EP2107679A2
公开(公告)日：2009-10-07
申请号：EP09163916.1
申请日：2005-02-04
申请人： Japan Aerospace Exploration Agency , High-Reliability Engineering & Components Corporation
发明人： Kuboyama, Satoshi , Shindou, Hiroyuki , Iide, Yoshiya , Makihara, Akiko
IPC分类号： H03K19/003 , H03K19/094
CPC分类号： H03K19/00338
摘要： A single-event-effect tolerant SOI-based logic device (13), in which a plurality of p-channel MOS transistors and a plurality of n-channel transistors (13N1, 13N2) are connected on an SOI-based substrate to constitute a logic device, wherein each of said first p-channel MOS transistor (13P1), said second p-channel MOS transistor (13P2), said first n-channel MOS transistor (13N1) and said second n-channel MOS transistor (13N2), is combined with an additional MOS transistor (13P3; 13P4; 13N3; 13N4) having a channel of the same conductive type as that thereof and a gate interconnected to a gate thereof, in such a manner that their channels are connected in series, so as to form a double structure.
摘要翻译：一种单事件效应容忍的SOI基逻辑器件（13），其中多个p沟道MOS晶体管和多个n沟道晶体管（13N1,13N2）连接在基于SOI的衬底上以构成所述第一p沟道MOS晶体管（13P1），所述第二p沟道MOS晶体管（13P2），所述第一n沟道MOS晶体管（13N1）和所述第二n沟道MOS晶体管（13N2）中的每一个，与具有与其相同导电类型的沟道的附加MOS晶体管（13P3; 13P4; 13N3; 13N4）和与其栅极互连的栅极组合，使得它们的沟道串联连接，从而形成双重结构。

5. 发明公开

EP1903440A2 Local controller for reconfigurable processing elements 审中-公开
标题翻译： Lokaler控制器fre rekonfigurierbare Verarbeitungselemente
公开(公告)号：EP1903440A2
公开(公告)日：2008-03-26
申请号：EP07112482.0
申请日：2007-07-13
申请人： Honeywell International Inc.
发明人： Ramos, Jeremy , Lafferty, James E. , Moseley, Nathan P. , Noah, Jason C. , Waltuch, Jason
IPC分类号： G06F11/00
CPC分类号： H03K19/007 , G06F11/00 , H03K19/00338
摘要： A reconfigurable computer is disclosed. The computer includes a controller and at least one reconfigurable processing element communicatively coupled to the controller. The controller is operable to read at least a first portion of a respective configuration of each of the plurality of reconfigurable processing elements and refresh at least a portion of the respective configuration of the reconfigurable processing element if the first portion of the configuration of the reconfigurable processing element has changed since the first portion was last checked.
摘要翻译：公开了可重新配置的计算机。计算机包括控制器和通信地耦合到控制器的至少一个可重新配置的处理元件。控制器可操作以读取多个可重配置处理元件中的每一个的相应配置的至少第一部分，并且如果可重构处理的配置的第一部分，则刷新可重构处理元件的相应配置的至少一部分元素自上次检查第一部分以来发生变化。

6. 发明公开

EP1720257A4 SOI STRUCTURE SINGLE EVENT TOLERANCE INVERTER, NAND ELEMENT, NOR ELEMENT, SEMICONDUCTOR MEMORY ELEMENT, AND DATA LATCH CIRCUIT 有权
标题翻译： SOI结构的单EVENT公差逆变器，NAND元件，NOR元件，半导体存储元件及数据锁存电路
公开(公告)号：EP1720257A4
公开(公告)日：2007-08-22
申请号：EP05709741
申请日：2005-02-04
申请人： JAPAN AEROSPACE EXPLORATION , HIGH RELIABILITY ENGINEERING &
发明人： KUBOYAMA SATOSHI , SHINDOU HIROYUKI , IIDE YOSHIYA , MAKIHARA AKIKO
IPC分类号： H03K19/003 , H03K19/094
CPC分类号： H03K19/00338
摘要： An inverter having high single event tolerance, an NAND element, an NOR element, a memory element, and a data latch circuit. The single event tolerance inverter (3I) has a double structure (3P1, 3P2, 3N1, 3N2) where a p-channel MOS transistor and an n-channel MOS transistor constituting the inverter are respectively further connected in series with transistors of the same conductivity type, respectively, and a node (A) between two p-channel MOS transistors is connected with a node (B) between two n-channel MOS transistors through a connecting line. A single event tolerance memory element and a data latch circuit (4) comprise such a single event tolerance inverter (3I).

7. 发明公开

EP1387494A1 CMOS circuits with protection for a single event upset 审中-公开
标题翻译： CMOS电离辐射与单保护电路从命中
公开(公告)号：EP1387494A1
公开(公告)日：2004-02-04
申请号：EP03251263.4
申请日：2003-03-03
申请人： National Space Development Agency of Japan
发明人： Matsuda, Sumio Nat.Space Develpmnt Agency of Japan , Kuboyama, S. Nat.Space Develpmnt Agency of Japan , Deguchi, Y. Nat.Space Develpmnt Agency of Japan
IPC分类号： H03K19/003
CPC分类号： G11C11/4125 , H01L27/0207 , H01L27/11 , H01L27/1104 , H03K3/0375 , H03K17/08142 , H03K19/00338 , Y10S257/903
摘要： A dual structure is introduced to the transistor in a flip-flop or a data input step controlled by a clock of a semiconductor logic circuit. The dual structure is formed by connecting a transistor with a MOS transistor having a channel of the same conductivity type in series with respect to the line of a source or drain and connecting their gates to each other, or by connecting an inverter with p-MOS transistors, one for VDD side and one for VSS side of the output step. The dual structure prevents single event phenomenon in a semiconductor logic circuit, such as inverter, SRAM and data latch circuit.

8. 发明公开

EP3311489A1 HIGH VOLTAGE TOLERANT CMOS DRIVER FOR LOW-VOLTAGE BI-DIRECTIONAL COMMUNICATION BUSES 有权
标题翻译：用于低压双向通信总线的高压容差CMOS驱动器
公开(公告)号：EP3311489A1
公开(公告)日：2018-04-25
申请号：EP15730764.6
申请日：2015-06-18
申请人： EUROPEAN SPACE AGENCY
发明人： JANSEN, Richard , LINDNER, Scott
IPC分类号： H03K19/003
CPC分类号： H03K19/00338 , G06F13/4022 , H03K19/00315 , H03K19/018507
摘要： This application relates to a bi-state driver circuit for switching an output terminal between a first predetermined voltage level and a high impedance state. The bi-state driver circuit comprises a first string of transistors connected between the output terminal and the first predetermined voltage level and comprising at least a first transistor arranged closer to the first predetermined voltage level and a second transistor arranged closer to the output terminal, a voltage divider circuit connected between the output terminal and a voltage level of a control signal attaining voltage levels between the first predetermined voltage level and a second predetermined voltage level, comprising at least one intermediate node having an intermediate voltage level between a voltage level of the output terminal and the voltage level of the control signal, and a second string of transistors connected between the intermediate node of the voltage divider circuit and the second predetermined voltage level, and comprising at least a third transistor. A control terminal of the second transistor is connected to the intermediate node. The first transistor is configured to be switched in accordance with the control signal. The third transistor is configured to be switched in accordance with the control signal, in a phase-locked relationship with the first transistor. The application further relates to a driver circuit for switching a first output terminal between a first output voltage level and a high impedance state, and for switching a second output terminal between a second output voltage level and the high impedance state. The application yet further relates to a method of controlling a bi-state driver circuit.

9. 发明公开

EP2685633A3 Layout method for soft-error hard electronics, and radiation hardened logic cell 审中-公开
标题翻译：用于软错误iimmune电子和辐射硬化逻辑单元排列方法
公开(公告)号：EP2685633A3
公开(公告)日：2014-05-07
申请号：EP13176436.7
申请日：2009-01-15
申请人： Robust Chip, Inc. , Lilja, Klas Olof
发明人： LILJA, Klas Olof
IPC分类号： H03K19/003
CPC分类号： G06F17/5022 , G06F17/5068 , G06F2217/12 , H03K19/0033 , H03K19/00338 , H03K19/20 , Y02P90/265
摘要： This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors. In particular, the method protects against cases where multiple nodes in circuit are affected by a single event. These events lead to multiple errors in the circuit, and while several methods exist to deal with single node errors, multiple node errors are very hard to deal with using any currently existing protection methods.
The method is particularly useful for CMOS based logic circuits in modem technologies (

10. 发明授权

EP2245740B1 LAYOUT METHOD FOR SOFT-ERROR HARD ELECTRONICS, AND RADIATION HARDENED LOGIC CELL 有权
标题翻译：软错误硬件电路的布局方法和辐射硬化逻辑单元
公开(公告)号：EP2245740B1
公开(公告)日：2014-03-12
申请号：EP09702623.1
申请日：2009-01-15
申请人： Robust Chip, Inc. , Lilja, Klas Olof
发明人： LILJA, Klas, Olof
IPC分类号： H03K19/173 , H03K19/01 , H03K19/003 , H03K19/20
CPC分类号： G06F17/5022 , G06F17/5068 , G06F2217/12 , H03K19/0033 , H03K19/00338 , H03K19/20 , Y02P90/265

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