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1. 发明公开

EP2885814A1 AN INTEGRATED CIRCUIT HAVING IMPROVED RADIATION IMMUNITY 有权
标题翻译：集成电路具有改进的辐射抗扰度
公开(公告)号：EP2885814A1
公开(公告)日：2015-06-24
申请号：EP13735551.7
申请日：2013-06-28
申请人： Xilinx, Inc.
发明人： HART, Michael, J. , KARP, James
IPC分类号： H01L27/02 , G11C5/00 , G11C11/412 , H01L21/8238 , H03K19/003 , H01L27/11
CPC分类号： G11C5/005 , G11C11/4125 , H01L21/823892 , H01L27/0207 , H01L27/0921 , H01L27/1104 , H03K19/00338
摘要： An integrated circuit having improved radiation immunity is described. The integrated circuit comprises a substrate (102); an n-well (108) formed on the substrate; a p-well (106) formed on the substrate; and a p-tap (202) formed in the p-well adjacent to the n-well, wherein the p-tap extends between circuit elements formed in the n-well and circuit elements formed in the p-well, and is coupled to a ground potential. A method of forming an integrated circuit having improved radiation immunity is also described.

2. 发明授权

EP2005588B1 RADIATION HARDENED DIFFERENTIAL OUTPUT BUFFER 有权
标题翻译：抗辐射差分输出缓冲
公开(公告)号：EP2005588B1
公开(公告)日：2011-09-14
申请号：EP07759329.1
申请日：2007-03-26
申请人： Honeywell International Inc.
发明人： ROPER, Weston
IPC分类号： H03K3/037 , H03K19/003
CPC分类号： H03K19/00338 , H04L25/0272 , H04L25/028
摘要： A radiation hardened differential output buffer (300) is partitioned into multiple stages (302, 304, 306, 308), each including at least one current source (310, 312) and a bridge circuit (314, 316, 318, 320). Each stage receives substantially the same inputs at substantially the same time, and provides substantially the same output (Outp, Outn). The outputs of each stage are connected together. As a result, if one of the stages is disrupted by SEE, the disrupted stage does not contribute enough current to the output of the differential output buffer (Outp, Outn) to disrupt the output signal.

3. 发明公开

EP2169827A1 Low voltage, high speed data latch 审中-公开
标题翻译： Latch-SchaltungenfürHochgeschwindigkeitsdaten mit niedriger Spannung
公开(公告)号：EP2169827A1
公开(公告)日：2010-03-31
申请号：EP09169846.4
申请日：2009-09-09
申请人： BAE SYSTEMS Information and Electronic Systems Integration, Inc.
发明人： Lawson, David C , Belzecky, Michael
IPC分类号： H03K3/037 , H03K3/356 , H03K19/003
CPC分类号： H03K3/0375 , H03K3/356113 , H03K3/356182 , H03K19/00338 , H03K19/00392
摘要： Tri-stating transistors which are controlled by the latch enable lines isolate holding transistors from the latch node during setting of the latch. The tri-stating transistors are connected to the holding transistors and the latch node which allows the node to float and assume a third state during setting of the latch when the latch is enabled.
摘要翻译：由锁存器使能线控制的三态晶体管在锁存器的设置期间将保持晶体管与锁存器节点隔离。三态晶体管连接到保持晶体管和锁存节点，当锁存器使能时，锁存节点允许节点浮动并在锁存器设置期间呈现第三状态。

4. 发明公开

EP2107679A3 Single-event-effect tolerant SOI-based logic device 审中-公开
标题翻译：单粒子效应宽容，基于SOI的逻辑设备
公开(公告)号：EP2107679A3
公开(公告)日：2010-01-20
申请号：EP09163916.1
申请日：2005-02-04
申请人： Japan Aerospace Exploration Agency , High-Reliability Engineering & Components Corporation
发明人： Kuboyama, Satoshi , Shindou, Hiroyuki , Iide, Yoshiya , Makihara, Akiko
IPC分类号： H03K19/003 , H03K19/094
CPC分类号： H03K19/00338
摘要： A single-event-effect tolerant SOI-based logic device (13), in which a plurality of p-channel MOS transistors and a plurality of n-channel transistors (13N1, 13N2) are connected on an SOI-based substrate to constitute a logic device, wherein each of said first p-channel MOS transistor (13P1), said second p-channel MOS transistor (13P2), said first n-channel MOS transistor (13N1) and said second n-channel MOS transistor (13N2), is combined with an additional MOS transistor (13P3; 13P4; 13N3; 13N4) having a channel of the same conductive type as that thereof and a gate interconnected to a gate thereof, in such a manner that their channels are connected in series, so as to form a double structure.

5. 发明公开

EP2107680A2 Single-event-effect tolerant SOI-based data latch device 有权
标题翻译：单事件效应容限，SOI-basierte Daten-Latch-Vorrichtung
公开(公告)号：EP2107680A2
公开(公告)日：2009-10-07
申请号：EP09163919.5
申请日：2005-02-04
申请人： Japan Aerospace Exploration Agency , High-Reliability Engineering & Components Corporation
发明人： Kuboyama, Satoshi , Shindou, Hiroyuki , Iide, Yoshiya , Makihara, Akiko
IPC分类号： H03K19/003 , H03K19/094
CPC分类号： H03K19/00338
摘要： A single-event-effect tolerant SOI-based data latch circuit which is formed on a substrate having an SOI structure and including a first inverter (4I5), a second inverter (4I4) and a clocked inverter (4I3), wherein:
said first inverter (4I5) has an output connected to an input of said second inverter(4I4);
said second inverter (4I4) has an output connected to an input of said first inverter (4I5); and
first complementary clock signals having logic values complementary to each other,
wherein at least one of said first and second inverters (4I5, 4I4) is a single-event-effect tolerant SOI-based inverter comprising a first p-channel MOS transistor (4P9; 4P7) and a first n-channel MOS transistor (4N10; 4N8), which are formed on a substrate having an SOI structure, and connected in series with respect to a source or drain line in this order in a direction from a node connected to the side of a first voltage source to a node connected to the side of a second voltage source, each of said first p-channel MOS transistor (4P9; 4P7) and said first n-channel MOS transistor (4N10; 4N8) being combined with a second MOS transistor (4P8; 4P10; 4N7; 4N9)
having a channel of a same conductive type as that thereof and a gate interconnected to a gate thereof, in such a manner that they are connected in series with respect to the source or drain line, and respective nodes between said first and second p-channel MOS transistors and between said first and second n-channel MOS transistors are connected together, so as to formed a double structure, and
at least one of said first and second inverters (4I5; 4I4) is a clocked inverter subject to on-off control based on second complementary clock signals opposite in phase relative to said first complementary clock signals.
摘要翻译：一种单事件效应容忍的基于SOI的数据锁存电路，其形成在具有SOI结构并包括第一反相器（4I5），第二反相器（4I4）和时钟反相器（4I3）的基板上，其中：所述第一反相器（4I5）具有连接到所述第二反相器（4I4）的输入端的输出端; 所述第二反相器（4I4）具有连接到所述第一反相器（4I5）的输入端的输出端。和具有彼此互补的逻辑值的第一互补时钟信号，其中所述第一和第二反相器（4I5,4I4）中的至少一个是单个事件效应容限的基于SOI的反相器，其包括第一p沟道MOS晶体管（4P9 ; 4P7）和第一n沟道MOS晶体管（4N10; 4N8），其形成在具有SOI结构的衬底上，并且相对于源极或漏极线依次从与节点连接的方向依次串联连接将第一电压源的一侧连接到连接到第二电压源侧的节点，所述第一p沟道MOS晶体管（4P9; 4P7）和所述第一n沟道MOS晶体管（4N10; 4N8）中的每一个被组合具有与其相同导电类型的沟道的第二MOS晶体管（4P8; 4P10; 4N7; 4N9）和与其栅极互连的栅极，使得它们相对于源串联连接漏极线和所述第一和第二之间的相应节点 d p沟道MOS晶体管，并且在所述第一和第二n沟道MOS晶体管之间连接在一起，以形成双重结构，并且所述第一和第二反相器（4I5; 4I4）是基于相对于所述第一互补时钟信号相位相反的第二互补时钟信号进行开 - 关控制的时钟反相器。

6. 发明公开

EP1956713A1 Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array 审中-公开
标题翻译：设备和方法，用于错误检测和校正在辐射固化现场可编程门阵列静态随机存取存储器
公开(公告)号：EP1956713A1
公开(公告)日：2008-08-13
申请号：EP08009052.5
申请日：2003-12-23
申请人： ACTEL CORPORATION
发明人： Plants, William C.
IPC分类号： H03K19/177 , H03K19/003 , G11C5/00
CPC分类号： G06F11/1008 , G11C5/005 , G11C11/4125 , H01L27/118 , H03K19/00338 , H03K19/1776 , H03K19/17764 , H03K19/1778
摘要： The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the routing resources. Error correction circuitry coupled to the configuration data lines analyzes and corrects any errors in the configuration data that may occur due to a single event upset (SEU). The present system also comprises a method for correcting errors in a programmable logic device having configuration data to program the programmable logic device. The method comprises a background reading of the configuration data. Next, the configuration data is analyzed for errors. Finally, the configuration data is then corrected and the configuration data is rewritten if errors are located.
摘要翻译：本系统包括具有逻辑模块和布线资源的逻辑模块联接在一起的耐辐射的可编程逻辑器件。提供配置数据的配置数据线控制逻辑模块和布线资源的编程。耦合到所述配置数据线纠错电路分析和配置数据中没有可能由于干扰（SEU）单一事件纠正任何错误。因此，本系统包括用于在具有配置数据到所述可编程逻辑装置进行编程的可编程逻辑器件校正误差的方法。该方法包括配置数据的背景读数。接下来，配置数据分析错误。最后，配置数据，然后校正，并且如果误差被定位的配置数据被重写。

7. 发明公开

EP1760888A3 Redundancy circuits hardened against single event upsets 审中-公开
标题翻译：冗余电路，硬化个别事件
公开(公告)号：EP1760888A3
公开(公告)日：2007-10-24
申请号：EP06119787.7
申请日：2006-08-30
申请人： Honeywell International Inc.
发明人： Fulkerson, David E.
IPC分类号： H03K19/003
CPC分类号： H03K19/00338 , H03K19/0075
摘要： A decision block is incorporated into a circuit design to provide hardening against single event upset and to store data. The decision block includes a storage element that stores data as long as inputs to the decision block remain constant. The decision black receives a first data input and second data input from redundant logic blocks or from logic blocks designed to provide complementary outputs. The decision block provides an output that is at a same logic level as the first data input if the two data inputs are at expected logjc levels during normal operating conditions (i.e., no disturbances). The decision block provides an output that is at a same logic level as a previous output of the decision block if the two data inputs are not at expected logic levels during normal operating conditions.

8. 发明公开

EP1787131A2 RADIATION-TOLERANT INRUSH LIMITER 无效
标题翻译：耐辐射限突
公开(公告)号：EP1787131A2
公开(公告)日：2007-05-23
申请号：EP05793890.4
申请日：2005-08-29
申请人： Summer, Steven E.
发明人： Summer, Steven E.
IPC分类号： G01R11/30
CPC分类号： H03K19/00338 , H03K17/165
摘要： A radiation-tolerant inrush limiter is provided. The inrush limiter does not incorporate radiation-hardened parts, but instead uses an ordinary (non-hardened) p-channel FET to provide switching functionality.

9. 发明公开

EP1159783A1 CIRCUIT LOGIQUE PROTEGE CONTRE DES PERTURBATIONS TRANSITOIRES 审中-公开
标题翻译：逻辑电路保护，防止TRANSIENTENSTÖRUNGEN
公开(公告)号：EP1159783A1
公开(公告)日：2001-12-05
申请号：EP00910904.2
申请日：2000-03-08
申请人： iRoC Technologies
发明人： NICOLAIDIS, Micha[l
IPC分类号： H03K19/003
CPC分类号： G06F11/1497 , G06F11/10 , H03K19/00338
摘要： The invention concerns a circuit protected against transitory perturbations, comprising a combinatorial logic circuit (10) having at least an output (A); a circuit (20) generating an error control code for said output, and a storage element (24) provided at said output, controlled by the circuit generating a control code to be transparent when the control code is correct, and to maintain its status when the control is incorrect.

10. 发明授权

EP2020085B1 FAULT TOLERANT ASYNCHRONOUS CIRCUITS 有权
标题翻译：容错的异步电路
公开(公告)号：EP2020085B1
公开(公告)日：2017-11-08
申请号：EP07761447.7
申请日：2007-04-27
申请人： Achronix Semiconductor Corp.
发明人： MANOHAR, Rajit , KELLY, Clinton W.
IPC分类号： H03K19/003 , H03K19/20 , H03K19/007 , G11C11/412
CPC分类号： G11C11/4125 , H03K19/00338 , H03K19/007 , H03K19/20

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