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    • 1. 发明公开
    • FIELD EFFECT TRANSISTOR
    • FELDEFFEKTTRANSISTOR
    • EP1635400A4
    • 2007-09-26
    • EP04734415
    • 2004-05-21
    • SUMITOMO ELECTRIC INDUSTRIES
    • FUJIKAWA KAZUHIROHARADA SHINMATSUNAMI HIROYUKIKIMOTO TSUNENOBU
    • H01L29/808H01L21/337H01L29/06H01L29/24
    • H01L29/66901H01L29/0634H01L29/1608H01L29/808
    • An electric-field moderating layer (12) and a p-type buffer layer (2) are formed on an SiC single crystal substrate (1). The electric-field moderating layer (12) is so formed between the p-type buffer layer (2) and the SiC single crystal substrate (1) that it is in contact with the SiC single crystal substrate (1). An n-type semiconductor layer (3) is formed on the p-type buffer layer (2). A p-type semiconductor layer (10) is formed on the n-type semiconductor layer (3). An n+-type source region layer (4) and an n+-type drain region layer (5) are formed at a certain distance from each other within the p-type semiconductor layer (10). A p+-type gate region layer (6) is formed in a portion of the p-type semiconductor layer (10) lying between the n+-type source region layer (4) and the n+-type drain region layer (5).
    • 在SiC单晶衬底(1)上形成电场缓和层(12)和p型缓冲层(2)。 在p型缓冲层(2)与SiC单晶衬底(1)之间形成电场缓和层(12),使其与SiC单晶衬底(1)接触。 在p型缓冲层(2)上形成n型半导体层(3)。 在n型半导体层(3)上形成p型半导体层(10)。 在p型半导体层(10)内以一定距离形成n +型源极区域层(4)和n +型漏极区域层(5)。 在位于n +型源极区域层(4)和n +型漏极区域层(5)之间的p型半导体层(10)的一部分上形成p +型栅极区域层(6)。