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1. 发明公开

EP3276654A1 NON-VOLATILE SRAM MEMORY CELL AND NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE 审中-公开
标题翻译：非易失性SRAM存储器单元和非易失性半导体存储器件
公开(公告)号：EP3276654A1
公开(公告)日：2018-01-31
申请号：EP16772411.1
申请日：2016-03-18
申请人： Floadia Corporation
发明人： SHINAGAWA Yutaka , TANIGUCHI Yasuhiro , KASAI Hideo , SAKURAI Ryotaro , KAWASHIMA Yasuhiko , TOYA Tatsuro , OKUYAMA Kosuke
IPC分类号： H01L21/8244 , G11C14/00 , H01L21/336 , H01L21/8247 , H01L27/11 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/1104 , G11C11/412 , G11C14/0063 , G11C16/0425 , H01L27/105 , H01L27/1116 , H01L27/11568 , H01L27/11573 , H01L29/788 , H01L29/792
摘要： A non-volatile SRAM memory cell and a non-volatile semiconductor memory device capable of programming SRAM data in a SRAM (15) to a non-volatile memory unit (16) through fast operation of the SRAM (15) are disclosed. A non-volatile semiconductor memory device (1) can achieve reduction in a voltage necessary for a programming operation to program SRAM data to the non-volatile memory unit (16). Thus, a first access transistor (21 a), a second access transistor (21 b), a first load transistor (22a), a second load transistor (22b), a first drive transistor (23a), and a second drive transistor (23b) included in the SRAM (15) connected with the non-volatile memory unit (16) can each include a gate insulating film having a thickness less than or equal to 4 nm, which achieves fast operation of the SRAM (15) at a lower power supply voltage.
摘要翻译：公开了一种能够通过SRAM（15）的快速操作将SRAM中的SRAM数据编程到非易失性存储器单元（16）的非易失性SRAM存储器单元和非易失性半导体存储器件。非易失性半导体存储器件（1）可以实现编程操作所需的电压的降低，以将SRAM数据编程到非易失性存储器单元（16）。因此，第一存取晶体管（21a），第二存取晶体管（21b），第一负载晶体管（22a），第二负载晶体管（22b），第一驱动晶体管（23a）和第二驱动晶体管（ 23b）包括在与非易失性存储单元（16）连接的SRAM（15）中的每一个都可以包括具有小于或等于4nm的厚度的栅极绝缘膜，其实现SRAM（15）在降低电源电压。

2. 发明公开

EP3262683A1 ARRAY OF NON-VOLATILE MEMORY CELLS WITH ROM CELLS 审中-公开
标题翻译：非易失性记忆细胞与ROM细胞阵列
公开(公告)号：EP3262683A1
公开(公告)日：2018-01-03
申请号：EP16706290.0
申请日：2016-02-05
申请人： Silicon Storage Technology Inc.
发明人： KIM, Jinho , TIWARI, Vipin , DO, Nhan , LIU, Xian , QIAN, Xiaozhou , BAI, Ning , YUE, Kai Man
IPC分类号： H01L27/112 , G11C16/04 , G11C17/12 , H01L27/115 , H01L29/423
CPC分类号： H01L27/11524 , H01L23/57 , H01L27/11226 , H01L27/11233 , H01L27/11253 , H01L27/11519 , H01L29/42328 , H01L29/788 , H01L29/7881
摘要： A memory device that includes a plurality of ROM cells each having spaced apart source and drain regions formed in a substrate with a channel region therebetween, a first gate disposed over and insulated from a first portion of the channel region, a second gate disposed over and insulated from a second portion of the channel region, and a conductive line extending over the plurality of ROM cells. The conductive line is electrically coupled to the drain regions of a first subgroup of the ROM cells, and is not electrically coupled to the drain regions of a second subgroup of the ROM cells. Alternately, a first subgroup of the ROM cells each includes a higher voltage threshold implant region in the channel region, whereas a second subgroup of the ROM cells each lack any higher voltage threshold implant region in the channel region.

3. 发明公开

EP3232465A1 MEMORY CELL AND NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE 审中-公开
标题翻译：存储器单元和非易失性半导体存储器件
公开(公告)号：EP3232465A1
公开(公告)日：2017-10-18
申请号：EP15851362.2
申请日：2015-10-06
申请人： Floadia Corporation
发明人： SHINAGAWA Yutaka , TANIGUCHI Yasuhiro , KASAI Hideo , SAKURAI Ryotaro , KAWASHIMA Yasuhiko , TOYA Tatsuro , OKUYAMA Kosuke
IPC分类号： H01L21/336 , G11C16/02 , G11C16/04 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/788 , G11C11/34 , G11C16/0425 , G11C16/0433 , G11C16/08 , H01L27/115 , H01L28/00 , H01L29/792 , H01L45/04
摘要： A voltage applied to a bit line (BL1) or a voltage applied to a source line (SL) is reduced to a value that allows a first select gate structure (5) or a second select gate structure (6) to block electrical connection between the bit line (BL1) and a channel layer (CH) or between the source line (SL) and the channel layer (CH), irrespective of a charge storage gate voltage needed to inject charge into a charge storage layer (EC) by a quantum tunneling effect. In accordance with the reduction in voltage(s) applied to the bit line (BL1) and the source line (SL), thickness of a first select gate insulating film (30) of the first select gate structure (5) and thickness of a second select gate insulating film (33) of the second select gate structure (6) are reduced. High-speed operation is achieved correspondingly. In accordance with the reduction in voltage(s) applied to the bit line (BL1) and the source line (SL), thickness of a gate insulating film of a field effect transistor in a peripheral circuit that controls a memory cell is reduced. The area of the peripheral circuit is reduced correspondingly.
摘要翻译：施加到位线（BL1）的电压或施加到源极线（SL）的电压降低到允许第一选择栅极结构（5）或第二选择栅极结构（6）阻止位线（BL1）和沟道层（CH）之间或源极线（SL）和沟道层（CH）之间的电荷存储栅极电压，而不考虑将电荷注入电荷存储层量子隧道效应。根据施加到位线（BL1）和源极线（SL）的电压的减少，第一选择栅极结构（5）的第一选择栅极绝缘膜（30）的厚度和减少第二选择栅极结构（6）的第二选择栅极绝缘膜（33）。高速运转也相应实现。根据施加到位线（BL1）和源极线（SL）的电压的减少，控制存储器单元的外围电路中的场效应晶体管的栅极绝缘膜的厚度减小。外围电路的面积相应减小。

4. 发明公开

EP3217422A1 FLASH MEMORY STRUCTURE AND FABRICATION METHOD THEREOF 审中-公开
标题翻译：闪存存储器结构及其制造方法
公开(公告)号：EP3217422A1
公开(公告)日：2017-09-13
申请号：EP17158826.2
申请日：2017-03-02
申请人： Semiconductor Manufacturing International Corporation (Shanghai) , Semiconductor Manufacturing International Corporation (Beijing)
发明人： ZOU, Lujun
IPC分类号： H01L21/28 , H01L21/768 , H01L29/66 , H01L27/11521 , H01L21/8234 , H01L21/8238 , H01L29/788
CPC分类号： H01L29/7881 , H01L21/02164 , H01L21/0217 , H01L21/0228 , H01L21/28141 , H01L21/28273 , H01L21/31144 , H01L21/76897 , H01L21/823468 , H01L21/823475 , H01L21/823864 , H01L21/823871 , H01L27/11521 , H01L29/66515 , H01L29/6653 , H01L29/6656 , H01L29/66825 , H01L29/788
摘要： A method is provided for fabricating a flash memory structure. The method includes providing a substrate; and forming a gate structure and a hard mask layer. The method also includes forming a sidewall structure on side walls of the gate structure and the hard mask layer; and forming an etching barrier layer covering the sidewall structure. In addition, the method includes forming a first dielectric layer; and removing the sidewall structure and the etching barrier layer higher than the first dielectric layer. Moreover, the method includes forming a sacrificial sidewall layer on the side wall of the hard mask layer and above the sidewall structure and the etching barrier layer; and forming a second dielectric layer on the first dielectric layer. Further, the method includes forming a contact hole penetrating through the second dielectric layer and the first dielectric layer; and forming a contact-hole plug in the contact hole.
摘要翻译：提供了一种用于制造闪存结构的方法。该方法包括提供衬底; 并形成栅极结构和硬掩模层。该方法还包括在栅极结构和硬掩模层的侧壁上形成侧壁结构; 以及形成覆盖侧壁结构的蚀刻阻挡层。另外，该方法包括形成第一介电层; 以及去除高于第一介电层的侧壁结构和蚀刻阻挡层。此外，该方法包括在硬掩模层的侧壁上以及侧壁结构和蚀刻阻挡层上方形成牺牲侧壁层; 以及在第一介电层上形成第二介电层。此外，该方法包括形成贯穿第二介电层和第一介电层的接触孔; 并在接触孔中形成接触孔塞。

5. 发明公开

EP2834843A4 MEMORY CELL THAT PREVENTS CHARGE LOSS 有权转让
标题翻译：小区防止电荷损失
公开(公告)号：EP2834843A4
公开(公告)日：2016-03-09
申请号：EP12887512
申请日：2012-10-31
申请人： HEWLETT PACKARD DEVELOPMENT CO
发明人： HO CHAW-SING , VILLAVELEZ REYNALDO , CAO XIN PING
IPC分类号： H01L27/115 , H01L21/28 , H01L21/8247 , H01L29/788
CPC分类号： H01L27/11521 , B41J2/1433 , H01L21/28273 , H01L27/11524 , H01L29/42324 , H01L29/513 , H01L29/518 , H01L29/788 , H01L29/7881

6. 发明公开

EP2948982A1 NON-VOLATILE MEMORY CELLS WITH ENHANCED CHANNEL REGION EFFECTIVE WIDTH, AND METHOD OF MAKING SAME 有权
标题翻译：其制造具有改进的有效途径区域的宽度和方法非易失性存储单元
公开(公告)号：EP2948982A1
公开(公告)日：2015-12-02
申请号：EP14711111.6
申请日：2014-03-03
申请人： Silicon Storage Technology Inc.
发明人： DO, Nhan , TRAN, Hieu, Van , SU, Chien, Sheng , TUNTASOOD, Prateep
IPC分类号： H01L27/115 , H01L29/66 , H01L29/788 , H01L29/423 , H01L21/762
CPC分类号： H01L21/76224 , H01L21/28273 , H01L27/11521 , H01L29/42328 , H01L29/42336 , H01L29/66825 , H01L29/788 , H01L29/7881
摘要： A memory device array with spaced apart parallel isolation regions formed in a semiconductor substrate, with an active region between each pair of adjacent isolation regions. Each isolation region includes a trench formed into the substrate surface and an insulation material formed in the trench. Portions of a top surface of the insulation material are recessed below the surface of the substrate. Each active region includes a column of memory cells each having spaced apart first and second regions with a channel region therebetween, a floating gate over a first channel region portion, and a select gate over a second channel region portion. The select gates are formed as continuous word lines extending perpendicular to the isolation regions and each forming the select gates for one row of the memory cells. Portions of each word line extend down into the trenches and disposed laterally adjacent to sidewalls of the trenches.
摘要翻译：一种存储器装置阵列与有源区在每对相邻隔离区域之间的半导体衬底形成，其中间隔开的平行的隔离区。每个隔离区域包括形成为在基板表面上和在该沟槽形成在绝缘材料的沟槽。绝缘材料的顶部表面的一些部分被凹陷的基板的表面的下方。每个有源区包括存储器单元每个具有间隔开的第一和第二区域与在它们之间，浮栅的沟道区上方的部分中的第一沟道区的列，并在部分选择栅上的第二沟道区。所述选择栅极被形成为连续的字线延伸垂直于所述隔离区，并且每个形成选择栅极对所述存储器单元的一行。每个字线的部分向下延伸到沟槽以及设置尾盘反弹邻近沟槽的侧壁上。

7. 发明公开

EP2648220A1 Floating gate memory device with trench isolation and method for manufacturing thereof 有权
标题翻译： Schwebegatespeicher-Bauelement mit Isolationsgraben und dessen Herstellung
公开(公告)号：EP2648220A1
公开(公告)日：2013-10-09
申请号：EP13175277.6
申请日：2006-06-30
申请人： Fujitsu Semiconductor Limited
发明人： EmaMA, Taiji , Mizutani, Kazuhiro
IPC分类号： H01L27/115 , H01L21/8247 , H01L21/762
CPC分类号： H01L29/788 , H01L21/762 , H01L21/76232 , H01L27/105 , H01L27/11526 , H01L27/11536 , H01L27/11546 , H01L27/11548 , H01L27/11575 , H01L29/42336 , H01L29/7881
摘要： A semiconductor device includes: a semiconductor substrate having first and second areas; an STI isolation region being made of an isolation trench formed in the semiconductor substrate and an insulating film burying the isolation trench and defining a plurality of active regions in the first and second areas; a first structure formed on an area from the active region in the first area to a nearby STI isolation region and having a first height; and a second structure formed on an area from the active region in the second area to a nearby STI isolation region and having a second height, wherein the surface of the said STI isolation region in the first area is lower than the surface of said STI isolation region in the second area.
摘要翻译：半导体器件包括：具有第一和第二区域的半导体衬底; STI隔离区域由形成在半导体衬底中的隔离沟槽和绝缘膜构成，绝缘膜掩埋隔离沟槽并且在第一和第二区域中限定多个有源区域; 形成在从所述第一区域中的有源区域到附近的STI隔离区域并具有第一高度的区域上的第一结构; 以及形成在从所述第二区域中的有源区域到附近的STI隔离区域并具有第二高度的区域上的第二结构，其中所述第一区域中的所述STI隔离区域的表面低于所述STI隔离物的表面区域在第二区域。

8. 发明公开

EP2645371A1 Cellule mémoire électronique à double grille et procédé de fabrication d'une telle cellule 审中-公开
标题翻译： Elektronische Speicherzelle mit Doppel-Gate，und Herstellungsverfahren einer solchen Speicherzelle
公开(公告)号：EP2645371A1
公开(公告)日：2013-10-02
申请号：EP13160576.8
申请日：2013-03-22
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
发明人： Charpin-Nicolle, Christelle
IPC分类号： G11C16/04 , H01L21/28 , H01L29/423
CPC分类号： H01L29/788 , G11C16/0425 , G11C16/0466 , H01L21/28273 , H01L21/28282 , H01L27/11568 , H01L29/42344 , H01L29/66833 , H01L29/7881
摘要： L'invention concerne une cellule mémoire électronique (100) comportant une première grille du transistor de sélection (106) surmontant une première partie (103 1 ) du canal (103) et un espaceur latéral (107) disposé contre un flanc latéral (108) de la grille du transistor de sélection (106), une partie de l'espaceur latéral (107) formant une grille du transistor mémoire (109) surmontant une seconde partie (103 2 ) du canal (103). La grille du transistor mémoire (109) comporte un empilement (110) de type ONO et une zone conductrice (112) incluant une face latérale (116) inclinée d'un angle α strictement compris entre 0 et 90° par rapport au plan du substrat (101).
摘要翻译：电池（100）具有与堆叠区域接触的下表面（114），使得区域分离通道（103）的一部分（103-2）和下表面。上表面（115）是平面的并平行于衬底平面。侧面（113,116）将下表面连接到上表面。一个侧面相对于基板的平面以相当于0和90度的角度倾斜，使得上表面的长度（L）严格地大于下表面的长度（L-MG）。长度被测量为在通道长度上的侧面之间的距离。还包括用于制造存储单元的方法的独立权利要求。

9. 发明公开

EP2589065A1 CHEMICALLY SENSITIVE SENSOR WITH LIGHTLY DOPED DRAINS 有权
标题翻译：化学敏感的传感器，轻巧的排水管
公开(公告)号：EP2589065A1
公开(公告)日：2013-05-08
申请号：EP11804218.3
申请日：2011-06-30
申请人： Life Technologies Corporation
发明人： FIFE, Keith, Glen
IPC分类号： H01L21/00
CPC分类号： H01L29/6659 , G01N27/414 , G01N27/4145 , H01L27/11517 , H01L29/788
摘要： A chemically sensitive sensor with a lightly doped region that affects an overlap capacitance between a gate and an electrode of the chemical sensitive sensor. The lightly doped region extends beneath and adjacent to a gate region of the chemical sensitive sensor. Modifying the gain of the chemically sensitive sensor is achieved by manipulating the lightly doped region under the electrodes.
摘要翻译：具有轻度掺杂区域的化学敏感传感器，其影响化学敏感传感器的栅极和电极之间的重叠电容。轻掺杂区域在化学敏感传感器的栅极区域下方并且邻近化学敏感传感器的栅极区域延伸。通过操作电极下方的轻掺杂区域来实现修改化学敏感传感器的增益。

10. 发明公开

EP1996199A4 RAPIDLY DISSOLVING SOLID ORAL DOSAGE FORM FOR DELIVERY OF COMPOSITION FOR INCREASING NITRIC OXIDE ACTIVITY 审中-公开
标题翻译： FAST-可溶性固体口服制剂做出成分以增加氮氧化物活动
公开(公告)号：EP1996199A4
公开(公告)日：2009-07-15
申请号：EP06775120
申请日：2006-08-16
申请人： H3 FORMULATIONS LTD
发明人： HEUER MARVIN A , CLEMENT KEN , CHAUDHURI SHAN
IPC分类号： A23L1/29 , A23K1/16 , A23L1/305 , A23L3/00 , A23P1/02 , A61K9/20 , A61K9/22 , A61K31/198 , A61K31/455 , A61K31/52
CPC分类号： A61K36/539 , A23L2/52 , A23L33/10 , A23L33/105 , A23L33/16 , A23L33/175 , A23L33/18 , A23V2002/00 , A61K9/0095 , A61K9/14 , A61K9/20 , A61K9/2072 , A61K31/122 , A61K31/185 , A61K31/197 , A61K31/198 , A61K31/205 , A61K31/385 , A61K31/4045 , A61K31/455 , A61K31/555 , A61K31/715 , A61K33/24 , A61K33/42 , A61K36/185 , A61K36/53 , A61K36/752 , A61K36/76 , A61K36/84 , A61K36/889 , H01L21/28273 , H01L29/42324 , H01L29/788 , H01L29/7884 , Y10S514/923 , A61K2300/00 , A23V2200/20 , A23V2250/0606 , A23V2250/7046 , A23V2200/326 , A23V2200/316 , A23V2250/06 , A23V2250/0644 , A23V2250/21
摘要： The present invention relates to a dietary supplement and method for a rapidly dissolving and disintegrating solid oral dosage form. Specifically, the present invention provides dietary supplements and methods for the delivery of dietary supplements comprising Arginine or derivatives thereof and Xanthinol Nicotinate or derivatives thereof. By way of oral administration to an individual of said solid oral dosage form, a method of rapidly increasing nitric oxide activity in an individual is also provided.

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