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1. 发明授权

EP3208846B1 SEMICONDUCTOR DEVICE 有权
公开(公告)号：EP3208846B1
公开(公告)日：2018-09-12
申请号：EP17156454.5
申请日：2003-07-24
申请人： Socionext Inc.
发明人： Watanabe, Kenichi
IPC分类号： H01L23/522 , H01L23/532 , H01L23/58
CPC分类号： H01L21/76877 , H01L21/76804 , H01L21/76843 , H01L23/481 , H01L23/485 , H01L23/522 , H01L23/5226 , H01L23/5227 , H01L23/528 , H01L23/5283 , H01L23/53204 , H01L23/53223 , H01L23/53228 , H01L23/53266 , H01L23/5329 , H01L23/53295 , H01L23/562 , H01L23/58 , H01L23/585 , H01L29/0607 , H01L29/0611 , H01L29/0619 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device comprises: insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a, wherein the groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Whereby, the defective filling of the buried conductor is prevented, and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced, so that the step cannot be influential on the upper interconnection layers and insulating layers. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented, and resultantly the semiconductor device can have high water resistance and high interconnection reliability.

2. 发明公开

EP2672517A4 SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME 有权
公开(公告)号：EP2672517A4
公开(公告)日：2014-08-13
申请号：EP12741475
申请日：2012-02-01
申请人： ROHM CO LTD
发明人： NAKANO YUKI , NAKAMURA RYOTA
IPC分类号： H01L29/78 , H01L21/336 , H01L29/06 , H01L29/12
CPC分类号： H01L29/063 , H01L21/046 , H01L27/088 , H01L29/045 , H01L29/0607 , H01L29/0623 , H01L29/0696 , H01L29/0878 , H01L29/1037 , H01L29/1095 , H01L29/1608 , H01L29/41766 , H01L29/4236 , H01L29/66068 , H01L29/66666 , H01L29/7813 , H01L29/7827
摘要： A semiconductor device according to the present invention includes a semiconductor layer made of a wide bandgap semiconductor having a gate trench provided with a sidewall and a bottom wall, a gate insulating film formed on the sidewall and the bottom wall of the gate trench, and a gate electrode embedded in the gate trench to be opposed to the semiconductor layer through the gate insulating film, while the semiconductor layer includes a first conductivity type source region formed to be exposed on the side of a front surface of the semiconductor layer for partially forming the sidewall of the gate trench, a second conductivity type body region formed on a side of the source region closer to a rear surface of the semiconductor layer to be in contact with the source region for partially forming the sidewall of the gate trench, a first conductivity type drift region formed on a side of the body region closer to the rear surface of the semiconductor layer to be in contact with the body region for forming the bottom wall of the gate trench, and a second conductivity type first breakdown voltage holding region selectively formed on an edge portion of the gate trench where the sidewall and the bottom wall intersect with each other in a partial region of the gate trench.

3. 发明公开

EP2447988A1 Power electronic device with edge passivation 有权
标题翻译： Randistivierung Leistungselektronikvorrichtung
公开(公告)号：EP2447988A1
公开(公告)日：2012-05-02
申请号：EP10014222.3
申请日：2010-11-02
申请人： Converteam Technology Ltd
发明人： Crane, Allan, David , Hinchley, David , Loddick, Sean Joseph
IPC分类号： H01L23/051 , H01L23/00 , H01L23/31
CPC分类号： H01L29/0607 , H01L23/051 , H01L23/3185 , H01L23/60 , H01L24/06 , H01L24/48 , H01L24/72 , H01L25/117 , H01L29/0619 , H01L29/0661 , H01L29/12 , H01L2224/04042 , H01L2224/06181 , H01L2224/4847 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/10156 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/30107 , H03K17/56 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention relates to a semiconductor device or power electronic device. The device includes a pair of pole pieces (36, 38), each having a profiled surface (40, 42). A semiconductor body or wafer (30), preferably of wide bandgap electronic material, is located between the pole pieces (36, 38) and includes contact metallisation regions (32, 34). The semiconductor body (30) produces an electric field that emerges from an edge region. Passivation means includes a first or radially inner part (44) in contact with the edge region of the semiconductor body (30) and which diffuses the electric field as it emerges from the edge region and a second or radially outer part (46). The second part (46) is in contact with the first part (44) and provides a substantially void-free interface with the profiled surface (40, 42) of each pole piece (36, 38). The device may be immersed in a dielectric liquid (50).
摘要翻译：本发明涉及一种半导体器件或功率电子器件。该装置包括一对极片（36,38），每个极片具有成型表面（40,42）。优选具有宽带隙电子材料的半导体本体或晶片（30）位于极片（36,38）之间并且包括接触金属化区域（32,34）。半导体本体（30）产生从边缘区域露出的电场。钝化装置包括与半导体本体（30）的边缘区域接触的第一或径向内部部分（44），并且当从所述边缘区域和第二或径向外部部分（46）露出时，所述电场扩散。第二部分（46）与第一部分（44）接触并且提供与每个极片（36,38）的成型表面（40,42）基本上无空隙的界面。该装置可以浸没在电介质液体（50）中。

4. 发明公开

EP1405347A4 LOW-VOLTAGE PUNCH-THROUGH BI-DIRECTIONAL TRANSIENT-VOLTAGE SUPPRESSION DEVICES HAVING SURFACE BREAKDOWN PROTECTION AND METHODS OF MAKING THE SAME 审中-公开
标题翻译：低电压PUNCH-BIDIREKTIONAL-TRANSIENTENSPANNUNGSUNTERDRÜCKUNGSEINRICHTUNGEN表面通过一种用于制造保护与方法
公开(公告)号：EP1405347A4
公开(公告)日：2009-08-19
申请号：EP02794642
申请日：2002-07-11
申请人： GEN SEMICONDUCTOR INC
发明人： EINTHOVEN WILLEM G , GINTY ANTHONY , WALSH AIDAN
IPC分类号： H01L29/861 , H01L21/329 , H01L27/02 , H01L27/108 , H01L29/06
CPC分类号： H01L29/0607 , H01L27/0259 , H01L29/66121 , H01L29/8618 , Y10S438/912 , Y10S438/965
摘要： A bi-directional transient voltage suppression device is provided. The device comprises: lower semiconductor layer of p+type conductivity (14); upper semiconductor layer of p+type conductivity (18); middle semiconductor layer of n type conductivity (16) adjacent to and disposed between the lower and upper layers such that lower and upper p-n junctions are formed; mesa trench (23) extending through the upper layer (18), through the middle layer (16) and through at least a portion of the lower layer (14), such that the mesa trench (23) defines an active area for the device; and an oxide layer (19) covering at least portions of the walls of the mesa trench (23) that correspond to the upper and lower junctions, such that the distance between the upper and lower junctions is increased at the walls. The integral of the net middle layer (16) doping concentration of this device, when taken over the distance between the junctions. A method of making such a device is also provided, which comprises: providing a p+type semiconductor substrate (12); epitaxially depositing a lower semiconductor layer of p+type conductivity (14); epitaxially depositing a middle semiconductor layer of n type conductivity (16) over the lower layer; epitaxially depositing an upper semiconductor layer of p+type conductivity (18) over the middle layer (16); heating the substrate (12), the lower epitaxial layer (14), the middle epitaxial layer (16) and the upper epitaxial layer (18); etching the mesa trench (23) that extends through the upper layer (18), through the middle layer (16) and through at least a portion of the lower layer (14), such that the mesa trench (23) defines an active area for the device; and thermally growing an oxide layer (19) on at least those portions of the walls of the mesa trench (23) that correspond to the upper and lower junctions of the device.

5. 发明公开

EP1978550A4 FIELD EFFECT TRANSISTOR, AND MULTILAYERED EPITAXIAL FILM FOR USE IN PREPARATION OF FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：场效应晶体管和多层外延用在场效应晶体管的制备
公开(公告)号：EP1978550A4
公开(公告)日：2009-07-22
申请号：EP06822252
申请日：2006-10-25
申请人： NEC CORP
发明人： INOUE TAKASHI , NAKAYAMA TATSUO , ANDO YUJI , MURASE YASUHIRO , OTA KAZUKI , MIYAMOTO HIRONOBU , YAMANOGUCHI KATSUMI , KURODA NAOTAKA , WAKEJIMA AKIO , OKAMOTO YASUHIRO
IPC分类号： H01L21/338 , H01L29/778 , H01L29/812
CPC分类号： H01L29/7783 , H01L29/0607 , H01L29/155 , H01L29/2003 , H01L29/205 , H01L29/42316 , H01L29/7787
摘要： In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer). To gate length Lg of a FET to be prepared, a sum a of layer thicknesses of an electron supply layer and a channel layer is selected so as to fulfill Lg/a ‰¥ 5, and in such a case, the layer thickness of the channel layer is selected in a range of not exceeding 5 times (about 500 A) as long as a de Broglie wavelength of two-dimensional electron gas accumulated in the channel layer in room temperature.

6. 发明公开

EP1959496A2 High-voltage vertical FET 审中-公开
标题翻译： Vertikaler Hochsponung-FET
公开(公告)号：EP1959496A2
公开(公告)日：2008-08-20
申请号：EP07253504.0
申请日：2007-09-04
申请人： Power Integrations, Inc.
发明人： Parthasarathy, Vijay , Grabowski, Wayne, Bryan
IPC分类号： H01L29/78 , H01L29/06 , H01L29/40 , H01L21/77
CPC分类号： H01L27/088 , H01L21/77 , H01L23/562 , H01L29/0607 , H01L29/0696 , H01L29/0878 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A transistor fabricated on a semiconductor die (21) includes a first section (30a) of transistor segments disposed in a first area of the semiconductor die, and a second section (30b) of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar (17) of a semiconductor material that extends in a vertical direction. First and second dielectric regions (15a,15b) are disposed on opposite sides of the pillar. First and second field plates (19a,19b) are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged.
摘要翻译：制造在半导体管芯（21）上的晶体管包括设置在半导体管芯的第一区域中的晶体管段的第一部分（30a）和设置在半导体管芯相邻的第二区域中的晶体管段的第二部分（30b）第一个区域。第一和第二部分中的每个晶体管段包括在垂直方向上延伸的半导体材料的柱（17）。第一和第二介质区域（15a，15b）设置在柱的相对侧上。第一和第二场板（19a，19b）分别设置在第一和第二电介质区域中。邻接第一和第二部分的晶体管段的外场板被分离或部分合并。

7. 发明公开

EP1405347A2 LOW-VOLTAGE PUNCH-THROUGH BI-DIRECTIONAL TRANSIENT-VOLTAGE SUPPRESSION DEVICES HAVING SURFACE BREAKDOWN PROTECTION AND METHODS OF MAKING THE SAME 审中-公开
标题翻译：低电压PUNCH-BIDIREKTIONAL-TRANSIENTENSPANNUNGSUNTERDRÜCKUNGSEINRICHTUNGEN表面通过一种用于制造保护与方法
公开(公告)号：EP1405347A2
公开(公告)日：2004-04-07
申请号：EP02794642.5
申请日：2002-07-11
申请人： GENERAL SEMICONDUCTOR, Inc.
发明人： EINTHOVEN, Willem, G. , GINTY, Anthony , WALSH, Aidan
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119 , H01L29/00 , H01L23/62
CPC分类号： H01L29/0607 , H01L27/0259 , H01L29/66121 , H01L29/8618 , Y10S438/912 , Y10S438/965
摘要： A bi-directional transient voltage suppression device is provided. The device comprises: lower semiconductor layer of p+type conductivity (14); upper semiconductor layer of p+type conductivity (18); middle semiconductor layer of n type conductivity (16) adjacent to and disposed between the lower and upper layers such that lower and upper p-n junctions are formed; mesa trench (23) extending through the upper layer (18), through the middle layer (16) and through at least a portion of the lower layer (14), such that the mesa trench (23) defines an active area for the device; and an oxide layer (19) covering at least portions of the walls of the mesa trench (23) that correspond to the upper and lower junctions, such that the distance between the upper and lower junctions is increased at the walls. The integral of the net middle layer (16) doping concentration of this device, when taken over the distance between the junctions. A method of making such a device is also provided, which comprises: providing a p+type semiconductor substrate (12); epitaxially depositing a lower semiconductor layer of p+type conductivity (14); epitaxially depositing a middle semiconductor layer of n type conductivity (16) over the lower layer; epitaxially depositing an upper semiconductor layer of p+type conductivity (18) over the middle layer (16); heating the substrate (12), the lower epitaxial layer (14), the middle epitaxial layer (16) and the upper epitaxial layer (18); etching the mesa trench (23) that extends through the upper layer (18), through the middle layer (16) and through at least a portion of the lower layer (14), such that the mesa trench (23) defines an active area for the device; and thermally growing an oxide layer (19) on at least those portions of the walls of the mesa trench (23) that correspond to the upper and lower junctions of the device.

8. 发明公开

EP3208846A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：EP3208846A1
公开(公告)日：2017-08-23
申请号：EP17156454.5
申请日：2003-07-24
申请人： Socionext Inc.
发明人： Watanabe, Kenichi
IPC分类号： H01L23/522 , H01L23/532 , H01L23/58
CPC分类号： H01L21/76877 , H01L21/76804 , H01L21/76843 , H01L23/481 , H01L23/485 , H01L23/522 , H01L23/5226 , H01L23/5227 , H01L23/528 , H01L23/5283 , H01L23/53204 , H01L23/53223 , H01L23/53228 , H01L23/53266 , H01L23/5329 , H01L23/53295 , H01L23/562 , H01L23/58 , H01L23/585 , H01L29/0607 , H01L29/0611 , H01L29/0619 , H01L2924/0002 , H01L2924/00
摘要： There is provided a semiconductor device comprising: a rectangular semiconductor substrate that includes four corners; a first interconnection formed above the rectangular semiconductor substrate; a guard ring that includes a plurality of first groove-shaped vias formed above the first interconnection; and a second interconnection formed above the plurality of first groove-shaped vias, wherein: the first interconnection includes copper; the first groove-shaped vias include copper; the second interconnection includes copper; the plurality of first groove-shaped vias are integral with the second interconnection; the plurality of first groove-shaped vias are connected to the first interconnection; and each of the plurality of first groove-shaped vias includes a first pattern bent twice each time at an inner angle of 135 degrees at each of the four corners in a plan view and bent totally at 90 degrees at each of the four corners in a plan view.
摘要翻译：提供了一种半导体器件，包括：包括四个角的矩形半导体衬底; 形成在矩形半导体衬底上方的第一互连; 保护环，其包括形成在第一互连上方的多个第一槽形通孔; 以及形成在所述多个第一槽形通孔上方的第二互连，其中：所述第一互连包括铜; 第一槽形通孔包括铜; 第二互连包括铜; 所述多个第一凹槽形通孔与所述第二互连形成整体; 多个第一槽形通孔连接到第一互连; 并且所述多个第一槽形通路中的每一个包括第一图案，所述第一图案在平面图中在每个角处以135度的内角每次弯曲两次，并且在所述四个角处的每一个处以90度完全弯曲平面图。

9. 发明授权

EP2526593B1 OPTO-ELECTRONIC DEVICE 有权转让
标题翻译： OPTOELEKTRONISCHE VORRICHTUNG
公开(公告)号：EP2526593B1
公开(公告)日：2017-04-05
申请号：EP11730725.6
申请日：2011-02-09
申请人： The Centre for Integrated Photonics Limited
发明人： DOSANJH, Sukhjiban , LEALMAN, Ian , BURNS, Gordon , ROBERTSON, Michael
IPC分类号： H01S5/22 , H01S5/227 , H01L33/14
CPC分类号： H01L29/0607 , B82Y20/00 , H01L33/145 , H01S5/2206 , H01S5/2224 , H01S5/2226 , H01S5/2227 , H01S5/2275 , H01S5/34306 , H01S5/34313 , H01S5/3434

10. 发明授权

EP2175487B8 Semiconductor device 有权转让
公开(公告)号：EP2175487B8
公开(公告)日：2015-05-06
申请号：EP10000804.4
申请日：2003-07-24
申请人： Fujitsu Semiconductor Limited
发明人： Watanabe, Kenichi
IPC分类号： H01L23/522 , H01L23/532 , H01L23/528
CPC分类号： H01L21/76877 , H01L21/76804 , H01L21/76843 , H01L23/481 , H01L23/485 , H01L23/522 , H01L23/5226 , H01L23/5227 , H01L23/528 , H01L23/5283 , H01L23/53204 , H01L23/53223 , H01L23/53228 , H01L23/53266 , H01L23/5329 , H01L23/53295 , H01L23/562 , H01L23/58 , H01L23/585 , H01L29/0607 , H01L29/0611 , H01L29/0619 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device comprises: insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a, wherein the groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Whereby, the defective filling of the buried conductor is prevented, and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced, so that the step cannot be influential on the upper interconnection layers and insulating layers. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented, and resultantly the semiconductor device can have high water resistance and high interconnection reliability.

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