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1. 发明公开

EP3316283A1 THROUGH SUBSTRATE VIA (TSV) AND METHOD THEREFOR 有权
标题翻译：通过基板通孔（TSV）及其方法
公开(公告)号：EP3316283A1
公开(公告)日：2018-05-02
申请号：EP17172306.7
申请日：2017-05-22
申请人： NXP USA, Inc.
发明人： ZHANG, Qing , LIU, Lianjun
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L21/76898 , H01L21/76828 , H01L21/7684 , H01L21/76844 , H01L21/76879 , H01L23/481 , H01L23/53228 , H01L23/5329
摘要： A through substrate via (TSV) and method of forming the same are provided. The method of making the TSV may include etching a via opening into the backside of semiconductor substrate, the via opening exposing a surface of a metal landing structure. A conductive layer is deposited over the backside of semiconductor substrate, sidewalls of the via opening, and exposed surface of the metal landing structure. The conductive layer is coated with a polymer material, filling the via opening. The polymer material is developed to remove the polymer material from the backside of semiconductor substrate, leaving the via opening filled with undeveloped polymer material. A planar backside surface of semiconductor substrate is formed by removing the conductive layer.
摘要翻译：提供贯穿基板通孔（TSV）及其形成方法。制造TSV的方法可以包括蚀刻通孔开口到半导体衬底的背侧中，通孔开口暴露金属着陆结构的表面。导电层沉积在半导体衬底的背面，通孔开口的侧壁和金属接合结构的暴露表面上。导电层涂覆有聚合物材料，填充通孔开口。显影聚合物材料以从半导体衬底的背面去除聚合物材料，使通孔开口填充未显影的聚合物材料。通过去除导电层形成半导体衬底的平面背侧表面。

2. 发明授权

EP2863430B1 Semiconductor device 有权转让
公开(公告)号：EP2863430B1
公开(公告)日：2017-04-12
申请号：EP15150440.4
申请日：2003-07-24
申请人： Socionext Inc.
发明人： Watanabe, Kenichi
IPC分类号： H01L23/522 , H01L23/532 , H01L23/58 , H01L23/528
CPC分类号： H01L21/76877 , H01L21/76804 , H01L21/76843 , H01L23/481 , H01L23/485 , H01L23/522 , H01L23/5226 , H01L23/5227 , H01L23/528 , H01L23/5283 , H01L23/53204 , H01L23/53223 , H01L23/53228 , H01L23/53266 , H01L23/5329 , H01L23/53295 , H01L23/562 , H01L23/58 , H01L23/585 , H01L29/0607 , H01L29/0611 , H01L29/0619 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device comprises: insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a, wherein the groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Whereby, the defective filling of the buried conductor is prevented, and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced, so that the step cannot be influential on the upper interconnection layers and insulating layers. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented, and resultantly the semiconductor device can have high water resistance and high interconnection reliability.

3. 发明公开

EP2863431A3 Semiconductor device 有权转让
公开(公告)号：EP2863431A3
公开(公告)日：2015-07-22
申请号：EP15150443.8
申请日：2003-07-24
申请人： Socionext Inc.
发明人： Watanabe, Kenichi
IPC分类号： H01L23/522 , H01L23/532 , H01L23/58 , H01L23/528
CPC分类号： H01L21/76877 , H01L21/76804 , H01L21/76843 , H01L23/481 , H01L23/485 , H01L23/522 , H01L23/5226 , H01L23/5227 , H01L23/528 , H01L23/5283 , H01L23/53204 , H01L23/53223 , H01L23/53228 , H01L23/53266 , H01L23/5329 , H01L23/53295 , H01L23/562 , H01L23/58 , H01L23/585 , H01L29/0607 , H01L29/0611 , H01L29/0619 , H01L2924/0002 , H01L2924/00
摘要： There is provided a semiconductor device comprising: a rectangular semiconductor substrate including a semiconductor circuit region and four corners; a first insulating film formed above the rectangular semiconductor substrate; a second insulating film formed above the first insulating film; a plurality of guard rings which surround the semiconductor circuit region; and a first conductive layer formed in the first insulating film. Each of the guard rings comprises a groove-shaped via formed in the second insulating film and connected to the first conductive layer. The groove-shaped via includes a pattern bent twice each time at an angle of larger than 90 degree at each of the four corners, and the pattern is bent totally at 90 degree at each of the four corners of the semiconductor substrate.

4. 发明公开

EP2863430A3 Semiconductor device 有权转让
公开(公告)号：EP2863430A3
公开(公告)日：2015-07-22
申请号：EP15150440.4
申请日：2003-07-24
申请人： Socionext Inc.
发明人： Watanabe, Kenichi
IPC分类号： H01L23/522 , H01L23/532 , H01L23/58 , H01L23/528
CPC分类号： H01L21/76877 , H01L21/76804 , H01L21/76843 , H01L23/481 , H01L23/485 , H01L23/522 , H01L23/5226 , H01L23/5227 , H01L23/528 , H01L23/5283 , H01L23/53204 , H01L23/53223 , H01L23/53228 , H01L23/53266 , H01L23/5329 , H01L23/53295 , H01L23/562 , H01L23/58 , H01L23/585 , H01L29/0607 , H01L29/0611 , H01L29/0619 , H01L2924/0002 , H01L2924/00
摘要： There is provided a semiconductor device comprising: a substrate; a first insulating film formed on the substrate; an aluminum layer formed above the first insulating film; a first guard ring which includes a first groove-shaped via-hole formed in the first insulating film and a first conductor formed in the first groove-shaped via-hole, the first conductor being connected to the substrate; and a second guard ring which includes a second groove-shaped via-hole formed in the first insulating film and a second conductor formed in the second groove-shaped via-hole, the second conductor being connected to the substrate. The second guard ring is surrounded by the first guard ring in a plan view, and the first guard ring is connected to the aluminum layer. Each of the first groove-shaped via-hole and the second groove-shaped via-hole includes a pattern bent twice each time at an inner angle of larger than 90 degree at each of four corners of the semiconductor device in a plan view.

5. 发明公开

EP2779244A2 Method of forming a HEMT semiconductor device and structure therefor 审中-公开
标题翻译：维尔法赫恩·赫斯特伦·恩·赫斯特·亨利·赫斯特伦（HEMT-Halbleiterbauelements und dessen Struktur）
公开(公告)号：EP2779244A2
公开(公告)日：2014-09-17
申请号：EP14158995.2
申请日：2014-03-11
申请人： Semiconductor Components Industries, LLC
发明人： Salih, Ali , Liu, Chin-Li , Grivna, Gordon
IPC分类号： H01L29/778 , H01L21/336
CPC分类号： H01L23/5226 , H01L21/6836 , H01L21/76898 , H01L21/78 , H01L23/4824 , H01L23/49827 , H01L23/53228 , H01L23/53242 , H01L23/5329 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/37 , H01L24/40 , H01L24/48 , H01L24/84 , H01L29/2003 , H01L29/66462 , H01L29/778 , H01L29/7787 , H01L2221/68327 , H01L2224/0345 , H01L2224/0346 , H01L2224/0347 , H01L2224/04034 , H01L2224/05111 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05639 , H01L2224/05647 , H01L2224/06181 , H01L2224/37012 , H01L2224/37013 , H01L2224/37124 , H01L2224/37147 , H01L2224/3716 , H01L2224/37187 , H01L2224/3719 , H01L2224/37639 , H01L2224/37644 , H01L2224/37647 , H01L2224/37655 , H01L2224/37664 , H01L2224/40499 , H01L2224/83801 , H01L2224/8385 , H01L2224/84801 , H01L2224/84815 , H01L2224/8485 , H01L2924/00014 , H01L2924/12032 , H01L2924/12042 , H01L2924/1305 , H01L2924/13063 , H01L2924/13064 , H01L2924/13091 , H01L2924/00 , H01L2924/01028 , H01L2924/014 , H01L2924/0105 , H01L2924/01047 , H01L2924/01082 , H01L2924/00012 , H01L2924/01029 , H01L2924/07811 , H01L2224/45099
摘要： In one embodiment, a method of forming a HEMT device may include plating a conductor or a plurality of conductors onto an insulator that overlies a plurality of current carrying electrodes of the HEMT device. The method may also include attaching a connector onto the conductor or attaching a plurality of connectors onto the plurality of conductors.
摘要翻译：在一个实施例中，形成HEMT器件的方法可以包括将导体或多个导体电镀到覆盖在HEMT器件的多个载流电极上的绝缘体上。该方法还可以包括将连接器附接到导体上或者将多个连接器附接到多个导体上。

6. 发明公开

EP2175486A3 Semiconductor device and method for fabricating the same 有权转让
标题翻译：半导体装置及其制造方法
公开(公告)号：EP2175486A3
公开(公告)日：2012-03-28
申请号：EP10000803.6
申请日：2003-07-24
申请人： Fujitsu Microelectronics Limited
发明人： Watanabe, Kenichi
IPC分类号： H01L23/522 , H01L23/532
CPC分类号： H01L21/76877 , H01L21/76804 , H01L21/76843 , H01L23/481 , H01L23/485 , H01L23/522 , H01L23/5226 , H01L23/5227 , H01L23/528 , H01L23/5283 , H01L23/53204 , H01L23/53223 , H01L23/53228 , H01L23/53266 , H01L23/5329 , H01L23/53295 , H01L23/562 , H01L23/58 , H01L23/585 , H01L29/0607 , H01L29/0611 , H01L29/0619 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device comprises: insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a, wherein the groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Whereby, the defective fil ling of the buried conductor is prevented, and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced, so that the step cannot be influential on the upper interconnection layers and insulating layers. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented, and resultantly the semiconductor device can have high water resistance and high interconnection reliability.
摘要翻译：该半导体器件包括：在衬底10上形成的绝缘膜40,42; 埋入绝缘膜40,42的至少一个表面侧的配线58; 绝缘膜60,62，形成在绝缘膜42上，并包括具有弯曲成直角图案的孔状通孔60和槽状通孔66a; 以及掩埋在孔状通孔60和槽状通孔66a中的掩埋导体70,72a，其中槽状通孔66a形成为具有小于孔的宽度的宽度从而防止了埋入导体的缺陷填充，并且可以防止层间绝缘膜的破裂。可以减少导体插头上的台阶，使得台阶不会影响上互连层和绝缘层。因此，可以防止与上互连层的接触不良以及形成膜时发生的问题，并且因此半导体器件可以具有高水阻和高互连可靠性。

7. 发明授权

EP1470580B1 Method for bilayer HDP CVD / PE CVD cap in advanced BEOL interconnect structures 有权
标题翻译：一种用于在先进BEOL互连结构的两层HDP-CVD和PE-CVD涂层法
公开(公告)号：EP1470580B1
公开(公告)日：2011-12-28
申请号：EP02784578.3
申请日：2002-11-22
申请人： International Business Machines Corporation , Infineon Technologies AG
发明人： CHEN, Tze-Chiang , ENGEL, Brett, H., c/o IBM United Kingdom Ltd., IP , FITZSIMMONS, John, A. , KANE, Terence , LUSTIG, Naftali, e. , MCDONALD, Ann,c/o IBM United Kingdom Ltd., IP Law , MCGAHAY, Vincent , SEO, Soon-Cheon , STAMPER, Anthony, K. , WANG, Yun, Yu , KALTALIOGLU, Erdem
IPC分类号： H01L21/768 , H01L23/532
CPC分类号： H01L21/76834 , H01L21/76801 , H01L21/76807 , H01L21/76832 , H01L23/5226 , H01L23/53228 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer (116, 123) is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and the second cap layer (117, 124) is formed of a dielectric material preferably deposited by a plasma-enhanced chemical vapor deposition (PE CVD) process. A method for forming the BEOL metallization structure is also disclosed. The invention is particularly useful in interconnect structures comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.

8. 发明公开

EP2059103A1 SEMICONDUCTOR DEVICE AND MULTILAYER WIRING BOARD 审中-公开
标题翻译： HALBLEITERANORDNUNG UND MEHRSCHICHTIGE LEITERPLATTE
公开(公告)号：EP2059103A1
公开(公告)日：2009-05-13
申请号：EP07806064.7
申请日：2007-08-24
申请人： National University Corporation Tohoku Unversity , Foundation for Advancement of International Science
发明人： OHMI, Tadahiro
IPC分类号： H05K3/46 , H01L21/312 , H01L21/768 , H01L23/12 , H01L23/522
CPC分类号： H01L23/5222 , H01L21/02115 , H01L21/0212 , H01L21/02167 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/02329 , H01L21/0234 , H01L21/3148 , H01L21/31633 , H01L21/3185 , H01L21/76802 , H01L21/7682 , H01L21/76826 , H01L21/76829 , H01L21/76831 , H01L21/76832 , H01L21/76883 , H01L23/3677 , H01L23/5283 , H01L23/53228 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H05K1/0203 , H05K1/024 , H05K3/467 , H05K3/4688 , H01L2924/00
摘要： A gas or an insulating material having a relative dielectric constant of not more than 2.5 on average is interposed between a first wiring layer and a second wiring layer included in a multilayer wiring structure. Between a wiring of the first wiring layer and a wiring of the second wiring layer, a conductive connector is arranged. Between a predetermined wiring of the first wiring layer and a predetermined wiring of the second wiring layer, an insulating heat conductor having a relative dielectric constant of not more than 5 is arranged.
摘要翻译：在多层布线结构中包括的第一布线层和第二布线层之间插入平均相对介电常数不大于2.5的气体或绝缘材料。在第一布线层的布线和第二布线层的布线之间布置导电连接器。在第一布线层的预定布线和第二布线层的预定布线之间布置有相对介电常数不大于5的绝缘导热体。

9. 发明公开

EP1278612A4 FLIP CHIP INTERCONNECTION STRUCTURE 有权
标题翻译：倒装连接结构
公开(公告)号：EP1278612A4
公开(公告)日：2008-04-16
申请号：EP01914779
申请日：2001-03-09
申请人： CHIPPAC INC
发明人： PENDSE RAJENDRA
IPC分类号： B23K20/00 , H01L21/60 , H01L21/603 , H05K3/32
CPC分类号： H01L23/522 , H01L21/76838 , H01L23/53228 , H01L23/53242 , H01L24/16 , H01L24/83 , H01L24/90 , H01L2224/1134 , H01L2224/13099 , H01L2224/13144 , H01L2224/13147 , H01L2224/1411 , H01L2224/1601 , H01L2224/16225 , H01L2224/16237 , H01L2224/16238 , H01L2224/17107 , H01L2224/81193 , H01L2224/81194 , H01L2224/81345 , H01L2224/81385 , H01L2224/83192 , H01L2224/838 , H01L2924/01006 , H01L2924/01029 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H05K3/325 , Y10T428/24917 , H01L2924/00 , H01L2924/3512
摘要： A flip chip structure (10) is formed by mechanically interlocking joining surfaces of a first (12) and a second (14) element. The first element (12), which may be a bump on an integrated circuit chip, includes a soft, deformable material with a low yield strength and high elongation to failure. The surface of the second element (14), which may for example be a substrate pad, is provided with asperities (16) into which the first element (12) deforms plastically under pressure to form the mechanical interlock.

10. 发明公开

EP1845554A2 A method to create super secondary grain growth in narrow trenches 审中-公开
标题翻译：维尔法赫恩·祖尔森
公开(公告)号：EP1845554A2
公开(公告)日：2007-10-17
申请号：EP06126251.5
申请日：2006-12-15
申请人： INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM ( IMEC)
发明人： Beyer, Gerald , Brongersma, Sywert H.
IPC分类号： H01L21/288 , H01L21/768
CPC分类号： H01L21/76877 , H01L21/2855 , H01L21/2885 , H01L21/76843 , H01L21/76867 , H01L21/76883 , H01L23/53228 , H01L23/53238
摘要： The present invention relates to a method for obtaining enlarged Cu grains in small trenches.
More specifically it related to a method for creating enlarged copper grains or inducing super secondary grain growth in electrochemically deposited copper in narrow trenches and/or vias to be used in semiconductor devices.
摘要翻译：本发明涉及一种在小沟槽中获得扩大的Cu晶粒的方法。更具体地说，它涉及一种用于在用于半导体器件的窄沟槽和/或通孔中的电化学沉积铜中产生扩大的铜晶粒或诱导超级二次晶粒生长的方法。

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