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1. 发明授权

EP0696062B1 CMOS semiconductor device and manufacturing method thereof 失效
标题翻译： CMOS半导体器件及其制造方法
公开(公告)号：EP0696062B1
公开(公告)日：2002-11-13
申请号：EP95304434.4
申请日：1995-06-23
申请人： Hitachi, Ltd.
发明人： Kawagoe, Hiroto , Shirasu, Tatsumi , Kiyota, Shogo , Suzuki, Norio , Yamada, Eiichi , Sugino, Yuji , Kitano, Manabu , Sakurai, Yoshihiko , Naganuma, Takashi , Arakawa, Hisashi
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L27/0925 , H01L21/823807

2. 发明公开

EP1033752A2 Dual work function CMOS device 审中-公开
标题翻译： Doppelte-Austrittsarbeit-CMOS-Bauelement
公开(公告)号：EP1033752A2
公开(公告)日：2000-09-06
申请号：EP00103621.9
申请日：2000-02-21
申请人： Infineon Technologies North America Corp.
发明人： Ilg, Matthias
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L27/0925 , H01L21/28061 , H01L21/823842
摘要： A method for forming a CMOS device. The method includes forming a gate oxide over a surface of a semiconductor substrate. A first doped layer is formed over the gate oxide. The first doped layer is lithographically patterned comprising selectively removing a portion of such first doped layer to expose a first portion of the gate oxide with the first doped layer remaining disposed over a second laterally positioned portion of the gate oxide. A second doped is deposited over the patterned first doped layer, such second doped layer having a dopant different from, for example a conductivity type opposite to, the dopant of the first doped layer. A portion of the second doped layer is deposited over the exposed first portion of the gate oxide and over the first doped layer to provide a pair of vertically positioned regions. A lower region comprises a portion of the first doped layer and an upper region comprising a portion of the second doped layer. The second doped layer is lithographically patterned to form a pair of laterally spaced gate electrodes for the transistors, one of such gates comprising the patterned first doped layer and the other one of the gates comprising the patterned pair of vertically positioned regions.
摘要翻译：一种用于形成CMOS器件的方法。该方法包括在半导体衬底的表面上形成栅极氧化物。在栅极氧化物上形成第一掺杂层。第一掺杂层被光刻图案化，包括选择性地去除这种第一掺杂层的一部分以暴露栅极氧化物的第一部分，其中第一掺杂层保留设置在栅极氧化物的第二横向定位部分上。第二掺杂沉积在图案化的第一掺杂层上，该第二掺杂层具有不同于例如与第一掺杂层的掺杂剂相反的导电类型的掺杂剂的掺杂剂。第二掺杂层的一部分沉积在栅极氧化物的暴露的第一部分上并在第一掺杂层上方，以提供一对垂直定位的区域。下部区域包括第一掺杂层的一部分和包含第二掺杂层的一部分的上部区域。第二掺杂层被光刻图案化以形成用于晶体管的一对横向隔开的栅电极，其中一个这样的栅极包括图案化的第一掺杂层，另一个栅极包括图案化的一对垂直定位区域。

3. 发明公开

EP0634795A3 An integrated device having MOS transistors which enable positive and negative voltage swings 失效
标题翻译：具有能够正负电压摆动的MOS晶体管的集成器件
公开(公告)号：EP0634795A3
公开(公告)日：1995-12-06
申请号：EP94305069.0
申请日：1994-07-11
申请人： XEROX CORPORATION
发明人： Mojaradi, Mohamad M. , Lerma, Jaime , Vo, Tuan , Buhler, Steven A.
IPC分类号： H01L27/02
CPC分类号： H01L27/0925 , H01L27/0251 , H03K17/302
摘要： A semiconductor circuit integrated with CMOS circuits for receiving a TTL input voltage and generating a large negative and positive voltage swing with respect to p-type or n-type substrate is disclosed. A PMOS negative and positive voltage swing circuit (50) can be integrated with CMOS circuits. The discrete transistor (12; Fig. 1) and the discrete resistor (14; Fig. 1) are replaced by two PMOS transistors (52) and (54). In this circuit the source (56) of the PMOS transistor (52) is connected to a positive voltage (+ V SS) , the gate (58) of the PMOS transistor (52) is connected to the input voltage (V₁)and the drain (60) of the PMOS transistor (52) is connected to the source (62) of the PMOS transistor (54). In order to have the transistor (54) function as an active resistor, its gate (64) is connected to its drain (66) and the drain (66) is connected to a negative voltage (-V DD ). By connecting the gate (64) of the PMOS transistor (54) to its drain (66), the PMOS transistor (54) acts as an active resistor. This invention is based on elimination of the electro-static discharge (ESD) protection circuit which is a requirement for any integrated circuit Eliminating the ESD protection circuit also eliminates the clamping feature of the ESD protection circuit and therefore the circuit can be driven to negative voltages for PMOS circuits and to positive voltages for NMOS circuits. This provides the possibility of connecting the drain of a a P-channel type metal oxide silicon field effect (PMOS) transistor, which is fabricated on a p-type substrate within an n-well, to a voltage below the the substrate voltage. Also, in a n-channel type metal oxide silicon field effect (NMOS) transistor which is fabricated on a n-type substrate within a P-well, the drain can be connected to voltages higher than the substrate voltage. Utilizing this feature of a MOS transistor provides a way to design an integrated circuit which can handle negative voltage swings as well as positive voltage swings.
摘要翻译：公开了与CMOS电路集成的用于接收TTL输入电压并且相对于p型或n型衬底产生大的负电压和正电压摆动的半导体电路。 PMOS负和正电压摆动电路（50）可以与CMOS电路集成。分立晶体管（12;图1）和分立电阻（14;图1）被两个PMOS晶体管（52）和（54）所取代。在该电路中，PMOS晶体管（52）的源极（56）连接到正电压（+ VSS），PMOS晶体管（52）的栅极（58）连接到输入电压（V 1），漏极 PMOS晶体管（52）的源极（60）连接到PMOS晶体管（54）的源极（62）。为了使晶体管（54）起有源电阻器的作用，其栅极（64）连接到其漏极（66），漏极（66）连接到负电压（-VDD）。通过将PMOS晶体管（54）的栅极（64）连接到其漏极（66），PMOS晶体管（54）充当有源电阻器。本发明基于取消对任何集成电路的要求的静电放电（ESD）保护电路。消除ESD保护电路也消除了ESD保护电路的钳位特性，因此电路可被驱动为负电压用于PMOS电路和用于NMOS电路的正电压。这提供了将在n阱内的p型衬底上制造的P沟道型金属氧化硅场效应（PMOS）晶体管的漏极连接至低于衬底电压的电压的可能性。而且，在P阱中的n型衬底上制造的n沟道型金属氧化物硅场效应（NMOS）晶体管中，漏极可以连接到高于衬底电压的电压。利用MOS晶体管的这一特性提供了一种设计可处理负电压摆动和正电压摆动的集成电路的方法。

4. 发明授权

EP0355951B1 Semiconductor device with memory cell region and a peripheral circuit and method of manufacturing the same 失效
标题翻译：具有用于存储单元和外围电路，以及它们的制造方法的一个区域的半导体器件。
公开(公告)号：EP0355951B1
公开(公告)日：1995-08-09
申请号：EP89305217.5
申请日：1989-05-23
申请人： SEIKO EPSON CORPORATION
发明人： Maruo, Yukata
IPC分类号： H01L27/115 , H01L21/82 , H01L29/08 , G11C17/00
CPC分类号： H01L27/0925 , H01L21/823456 , H01L27/105 , Y10S257/90

5. 发明公开

EP0614216A1 APPARATUS FOR FORMING OXIDE FILM, HEAT TREATMENT APPARATUS, SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREFOR 失效
标题翻译：设备用于生产层的氧化，装置热治疗和半导体器件的工艺用于生产。
公开(公告)号：EP0614216A1
公开(公告)日：1994-09-07
申请号：EP92924004.2
申请日：1992-11-24
申请人： OHMI, Tadahiro
发明人： OHMI, Tadahiro
IPC分类号： H01L21/316 , H01L21/00 , C23C16/44 , C30B33/00
CPC分类号： H01L21/67115 , C23C16/4404 , C23C16/452 , C23C16/455 , C30B33/005 , H01L21/02238 , H01L21/02255 , H01L21/31662 , H01L27/0925
摘要： A heat treatment apparatus which can perform active gas sintering, etc. for forming a reliable oxide film on the surface of a substrate in a furnace tube. In the apparatus, provided are at least a furnace tube (1) which has a closable opening part (11) for loading in and out an object (5) to be treated and has gas introducing inlets (12) for introducing gases inside, a heating means (4) for heating the inside of the furnace tube (1), gas introducing pipes (2) communicating with the gas introducing inlets (12) so as to pass gases through them, and a heating means (9) for heating the gas introducing pipes (2). At least the inner surfaces of the gas introducing pipes (2) are made of nickel or a material containing nickel.
摘要翻译：热处理装置，能够用于在炉管上形成可靠的氧化物薄膜上的基材的表面进行活性气体烧结等。在该装置中，提供了至少一个炉管（1），其具有用于进出目的的装载一个可封闭的开口部（11）（5）的待处理，并且具有气体导入口（12），用于内，气体导入用于加热炉管（1）的内部加热装置（4），气体导入管（2）与上述气体导入口（12），以便进行通信，通过它们来传递气体和加热装置（9），用于加热气体导入管（2）。至少气体导入配管（2）的内表面由镍或材料包含镍。

6. 发明授权

EP0414400B1 MOSFET depletion device 失效
标题翻译：耗尽型MOSFET的安排。
公开(公告)号：EP0414400B1
公开(公告)日：1994-03-02
申请号：EP90308605.6
申请日：1990-08-06
申请人： DELCO ELECTRONICS CORPORATION
发明人： Henderson, Mark F. , Schlais, John R.
IPC分类号： H01L29/62 , H01L29/784
CPC分类号： H01L27/0883 , H01L21/28035 , H01L21/823842 , H01L27/0925 , H01L29/4916 , H01L29/78

7. 发明公开

EP0452874A3 MOS semiconductor device 失效
标题翻译： MOS半导体器件
公开(公告)号：EP0452874A3
公开(公告)日：1992-03-04
申请号：EP91106041.6
申请日：1991-04-16
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Tsugaru, Kazunori, c/o Intellectual Property Div.
IPC分类号： H01L27/092 , H01L27/06
CPC分类号： H01L27/0925 , H01L27/0623
摘要： According to this invention, there is disclosed a MOS semiconductor device including a semiconductor substrate (1) of a first conductivity type, first and second buried diffusion layers (2-1, 2-2) of a second conductivity type selectively formed on the substrate (1), an epitaxial layer (3) of the first conductivity type formed on the substrate (1) and the first and second buried diffusion layers (2-1, 2-2), a first well region (4-1) of the second conductivity type formed in the epitaxial layer (3) to be in contact with the first buried diffusion layer (2-1), a second ring-like well region (4-2) of the second conductivity type formed in the epitaxial layer (3) to be in contact with the second buried diffusion layer (2-2), a MOS transistor (10) of the first conductivity type formed in a surface layer of the first well region (4-1), and a MOS transistor (16) of the second conductivity type formed in a surface layer of a portion surrounded by the second well region (4-2) of the epitaxial layer (3).

8. 发明公开

EP0337481A3 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：EP0337481A3
公开(公告)日：1991-05-29
申请号：EP89106711.8
申请日：1989-04-14
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kinugawa, Masaaki c/o Intellectual Property Div.
IPC分类号： H01L29/60 , H01L29/54 , H01L29/40 , H01L29/62
CPC分类号： H01L27/0925 , H01L29/4232 , H01L29/456
摘要： A semiconductor device includes a first polysilicon layer (17B) containing n-type impurity, a second polysilicon layer (17A) containing p-type impurity, and TiSi₂ layer (19). In the semiconductor device, the top surfaces of the first and second polysilicon layers (17B and 17A) are covered with an TiN layer (18) having a smaller diffusion coefficient of n-type impurity than the TiSi₂ layer (19) and the top surface of the TiN layer (18) is covered with the TiSi₂ layer (19).
摘要翻译：一种半导体器件包括含有n型杂质的第一多晶硅层（17B），含有p型杂质的第二多晶硅层（17A）和TiSi 2层（19）。在该半导体器件中，第一和第二多晶硅层（17B和17A）的顶表面被具有比TiSi 2层（19）小的n型杂质扩散系数的TiN层（18）覆盖，并且顶表面 TiN层（18）被TiSi 2层（19）覆盖。

9. 发明授权

EP0295391B1 High voltage MOS transistors 失效
标题翻译：高压MOS晶体管
公开(公告)号：EP0295391B1
公开(公告)日：1991-01-30
申请号：EP88106404.2
申请日：1988-04-21
申请人： POWER INTEGRATIONS, INC.
发明人： Eklund, Klas H.
IPC分类号： H01L29/78 , H01L29/08 , H01L27/08
CPC分类号： H01L29/0847 , H01L27/085 , H01L27/0925 , H01L29/0634 , H01L29/1045 , H01L29/105 , H01L29/1087 , H01L29/7832 , H01L29/7835
摘要： An insulated-gate, field-effect transistor and a double-sided, junction-gate field-effect transistor are connected in series on the same chip to form a high-voltage MOS transistor. An extended drain region is formed on top of a substrate of opposite conductivity-type material. A top layer of material having a conductivity-type opposite that of the extended drain and similar to that of the substrate is provided by ion-implantation through the same mask window as the extended drain region. This top layer covers only an intermediate portion of the extended drain which has ends contacting a silicon dioxide layer thereabove. The top layer is either connected to the substrate or left floating. Current flow through the extended drain region can be controlled by the substrate and the top layer, which act as gates providing field-effects for pinching off the extended drain region therebetween. A complementary pair of such high-voltage MOS transistors having opposite conductivity-type are provided on the same chip.

10. 发明公开

EP0168678A3 Integrated overvoltage protection circuit 失效
标题翻译：集成式过电压保护电路
公开(公告)号：EP0168678A3
公开(公告)日：1987-04-22
申请号：EP85107743
申请日：1985-06-24
申请人： International Business Machines Corporation
发明人： Cottrell, Peter Edwin , Craig, William James , Troutman, Ronald Roy
IPC分类号： H01L27/02 , H01L27/08
CPC分类号： H01L27/0251 , H01L21/761 , H01L27/0925
摘要： The overvoltage protection circuit, when used with CMOS circuits, protects them from overvoltage conditions while minimizing latch-up conditions in the structure. It consists of a well region (16) of an opposite conductivity to that of the substrate (10, 12) defining a pocket region (18) having a conductivity type which is similar to that of the substrate (10, 12). A first PN junction diode (34) is formed in a portion of the well region (16) and a second PN junction diode (32) is formed in the pocket region (18). The two diodes have opposite polarity and they both are connected to a signal line in such a way that one of the two diodes will be forward biased if the voltage on the signal line exceeds the bounds of the power supply voltages. The pocket region (18) is connected to a V ss terminal which is normally grounded and the well region (16) is connected to a power supply V oo . The doping concentration in the well region (16) is predetermined to have a gradient so that minority carriers injected from one of the diodes in the well region will be repulsed and prevented from moving into the substrate region where they would be majority carriers and they could cause latch-up in the structure or at the very least adversely affect the voltage level of the substrate. Instead the injected carriers recombine in the well region (16) or are collected by the adjacent isolated pocket region (18). When the second diode (32) is forward biased, the minority carriers are injected into the isolated pocket region (18) and are prevented from reaching the substrate (10) by the underlying well region (14). This prevents these carriers from affecting the operation of adjacent circuits.

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