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1. 发明公开

EP3176816A1 WELL IMPLANTATION PROCESS FOR FINFET DEVICE 有权转让
标题翻译： FINFET器件的良好注入工艺
公开(公告)号：EP3176816A1
公开(公告)日：2017-06-07
申请号：EP16199529.5
申请日：2016-11-18
申请人： Semiconductor Manufacturing International Corporation (Beijing) , Semiconductor Manufacturing International Corporation (Shanghai)
发明人： ZHOU, Fei
IPC分类号： H01L21/8238 , H01L29/66
CPC分类号： H01L21/823892 , H01L21/26513 , H01L21/823493 , H01L21/823821 , H01L21/823878 , H01L27/0925 , H01L27/0927 , H01L27/0928 , H01L29/66803
摘要： A method for manufacturing a semiconductor device includes providing a substrate, performing an N-type dopant implantation into a first region of the substrate to form an N-well, removing a portion of the substrate to form a first set of fins on the N-well and a second set of fins on a second region of the substrate adjacent the N-well, filling gap spaces between the fins to form an isolation region, and performing a P-type dopant implantation into the second region to form a P-well adjacent the N-well. The N-well and the P-well are formed separately at different times. The loss of the P-type dopant ions due to the diffusion of P-type dopant ions in the P-well into the isolation region can be eliminated, and the damage to the fins caused by N-type dopant ions can be avoided.
摘要翻译：一种用于制造半导体器件的方法包括提供衬底，在衬底的第一区域中执行N型掺杂剂注入以形成N阱，去除衬底的一部分以在N阱上形成第一组鳍片，以及邻近所述N阱的所述衬底的第二区域上的第二组鳍片，填充所述鳍片之间的间隙空间以形成隔离区域，以及向所述第二区域中执行P型掺杂剂注入以形成P阱毗邻N井。 N阱和P阱分别在不同的时间形成。由于P型掺杂剂离子在P阱中扩散到隔离区中而导致的P型掺杂剂离子的损失可以被消除，并且可以避免由N型掺杂剂离子引起的对鳍片的损伤。

2. 发明公开

EP0774786A3 CMOS semiconductor device 失效
标题翻译： CMOS-Halbleiter-Bauteil
公开(公告)号：EP0774786A3
公开(公告)日：1999-11-03
申请号：EP96118200.3
申请日：1996-11-13
申请人： NEC CORPORATION
发明人： Tsuboi, Toshihide
IPC分类号： H01L27/092 , H01L27/02 , G09G3/18
CPC分类号： G09G3/18 , H01L27/0251 , H01L27/0266 , H01L27/0925 , H01L2924/0002 , H01L2924/00
摘要： An improved layout of transistors near LCD drive terminals in a CMOS semiconductor device to reduce a chip size without damaging resistances against electrostatic destruction and latch-up. MOSFETs whose sources are connected to neither an electric source nor a ground are selectively arranged between two protective diffusion layers having different polarities, connected to a terminal.
摘要翻译：在CMOS半导体器件中的LCD驱动端子附近的晶体管的改进的布局，以减少芯片尺寸而不损害抗静电破坏和闭锁的电阻。源极不连接到电源和接地的MOSFET选择性地布置在具有不同极性的两个保护性扩散层之间，连接到端子。

3. 发明公开

EP0727098A1 HIGH-VOLTAGE LDD-MOSFET WITH INCREASED BREAKDOWN VOLTAGE AND METHOD OF FABRICATION 失效
标题翻译：具有增强的击穿电压和方法高压MOSFET LDD
公开(公告)号：EP0727098A1
公开(公告)日：1996-08-21
申请号：EP95930147.0
申请日：1995-08-10
申请人： NATIONAL SEMICONDUCTOR CORPORATION
发明人： BERGEMONT, Albert, M.
IPC分类号： H01L21 , H01L27 , H01L29
CPC分类号： H01L29/66659 , H01L27/0925 , H01L29/7839
摘要： In a high-voltage MOS transistor that utilizes a lightly-doped drain region to isolate a heavily-doped drain region from the substrate, the reverse bias which can be applied across the drain-to-substrate junction of the transistor is increased by reducing the width of the heavily-doped drain region.

4. 发明公开

EP0634795A2 An integrated device having MOS transistors which enable positive and negative voltage swings 失效
标题翻译： Integrierte Anordnung mit MOS-Transistoren，阴性和阴性Spannungsschwingungen erlauben。
公开(公告)号：EP0634795A2
公开(公告)日：1995-01-18
申请号：EP94305069.0
申请日：1994-07-11
申请人： XEROX CORPORATION
发明人： Mojaradi, Mohamad M. , Lerma, Jaime , Vo, Tuan , Buhler, Steven A.
IPC分类号： H01L27/02
CPC分类号： H01L27/0925 , H01L27/0251 , H03K17/302
摘要： A semiconductor circuit integrated with CMOS circuits for receiving a TTL input voltage and generating a large negative and positive voltage swing with respect to p-type or n-type substrate is disclosed. A PMOS negative and positive voltage swing circuit (50) can be integrated with CMOS circuits. The discrete transistor (12; Fig. 1) and the discrete resistor (14; Fig. 1) are replaced by two PMOS transistors (52) and (54). In this circuit the source (56) of the PMOS transistor (52) is connected to a positive voltage (+ V SS) , the gate (58) of the PMOS transistor (52) is connected to the input voltage (V₁)and the drain (60) of the PMOS transistor (52) is connected to the source (62) of the PMOS transistor (54). In order to have the transistor (54) function as an active resistor, its gate (64) is connected to its drain (66) and the drain (66) is connected to a negative voltage (-V DD ). By connecting the gate (64) of the PMOS transistor (54) to its drain (66), the PMOS transistor (54) acts as an active resistor. This invention is based on elimination of the electro-static discharge (ESD) protection circuit which is a requirement for any integrated circuit Eliminating the ESD protection circuit also eliminates the clamping feature of the ESD protection circuit and therefore the circuit can be driven to negative voltages for PMOS circuits and to positive voltages for NMOS circuits. This provides the possibility of connecting the drain of a a P-channel type metal oxide silicon field effect (PMOS) transistor, which is fabricated on a p-type substrate within an n-well, to a voltage below the the substrate voltage. Also, in a n-channel type metal oxide silicon field effect (NMOS) transistor which is fabricated on a n-type substrate within a P-well, the drain can be connected to voltages higher than the substrate voltage. Utilizing this feature of a MOS transistor provides a way to design an integrated circuit which can handle negative voltage swings as well as positive voltage swings.
摘要翻译：与CMOS电路集成的半导体电路包含作为输出晶体管的p沟道型MOSFET。输出晶体管的漏极连接到地电位以下的电压源，源极连接到地电位以上的电压源。

5. 发明公开

EP0614216A4 APPARATUS FOR FORMING OXIDE FILM, HEAT TREATMENT APPARATUS, SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREFOR. 失效
标题翻译：设备用于生产层的氧化，装置热治疗和半导体器件的工艺用于生产。
公开(公告)号：EP0614216A4
公开(公告)日：1994-11-30
申请号：EP92924004
申请日：1992-11-24
申请人： OHMI TADAHIRO
发明人： OHMI TADAHIRO
IPC分类号： C23C16/44 , C23C16/452 , C23C16/455 , C30B33/00 , H01L21/00 , H01L21/316 , H01L27/092
CPC分类号： H01L21/67115 , C23C16/4404 , C23C16/452 , C23C16/455 , C30B33/005 , H01L21/02238 , H01L21/02255 , H01L21/31662 , H01L27/0925
摘要： A heat treatment apparatus which can perform active gas sintering, etc. for forming a reliable oxide film on the surface of a substrate in a furnace tube. In the apparatus, provided are at least a furnace tube (1) which has a closable opening part (11) for loading in and out an object (5) to be treated and has gas introducing inlets (12) for introducing gases inside, a heating means (4) for heating the inside of the furnace tube (1), gas introducing pipes (2) communicating with the gas introducing inlets (12) so as to pass gases through them, and a heating means (9) for heating the gas introducing pipes (2). At least the inner surfaces of the gas introducing pipes (2) are made of nickel or a material containing nickel.

6. 发明授权

EP0321738B1 MOS transistor with enhanced isolation capabilities 失效
标题翻译： MOS晶体管具有增加的隔热能力。
公开(公告)号：EP0321738B1
公开(公告)日：1994-09-07
申请号：EP88119785.9
申请日：1988-11-28
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Tigelaar, Howard L. , Paterson, James L.
IPC分类号： H01L29/06 , H01L21/76 , H01L27/088
CPC分类号： H01L21/765 , H01L27/0925

7. 发明公开

EP0445323A1 Field effect semiconductor device having current paths formed in conductive layer of semiconductor substrate 失效
标题翻译： Feldeffekt-Halbleitervorrichtung mit einem Stromverlauf in eienr leitenden Schicht des Halbleitersubstrates。
公开(公告)号：EP0445323A1
公开(公告)日：1991-09-11
申请号：EP90104279.6
申请日：1990-03-06
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Shirai, Koji, c/o Intellectual Property Division
IPC分类号： H01L21/82 , H01L21/76 , H01L27/092 , H01L29/08 , H01L21/74
CPC分类号： H01L27/0925 , H01L21/761 , H01L21/823878
摘要： A pot-like hole with a bottom is formed by etching part of one major surface of a semiconductor substrate (1) of a first conductivity type. A buried layer (9) is formed on the surface of the pot-like hole. A semiconductor layer (10) of a second conductivity type is formed to fill a space inside the buried layer (9), and is electrically isolated from the semiconductor substrate (1) of the first conductivity type by the buried layer (9). A first FET (Field Effect Transistor) (Q1), having a channel with current paths extending through the semiconductor substrate (1), is formed on one major surface of the semiconductor substrate (1) of the first conductivity type. A second FET (Q2) having a channel with current paths extending through the semiconductor layer (10) of the second conductivity type is formed on the semiconductor layer (10) of the second conductivity type which is located on the buried layer (9).
摘要翻译：通过蚀刻第一导电类型的半导体衬底（1）的一个主表面的一部分形成具有底部的盆形孔。在锅形孔的表面上形成掩埋层（9）。形成第二导电类型的半导体层（10）以填充掩埋层（9）内部的空间，并且通过掩埋层（9）与第一导电类型的半导体衬底（1）电隔离。在第一导电类型的半导体衬底（1）的一个主表面上形成具有延伸穿过半导体衬底（1）的电流通道的沟道的第一FET（场效应晶体管）（Q1）。在位于掩埋层（9）上的第二导电类型的半导体层（10）上形成第二FET（Q2），其具有通过延伸穿过第二导电类型的半导体层（10）的电流通路的沟道。

8. 发明公开

EP0414400A2 MOSFET depletion device 失效
标题翻译： MOSFET-Verarmungsanordnung。
公开(公告)号：EP0414400A2
公开(公告)日：1991-02-27
申请号：EP90308605.6
申请日：1990-08-06
申请人： DELCO ELECTRONICS CORPORATION
发明人： Henderson, Mark F. , Schlais, John R.
IPC分类号： H01L29/62 , H01L29/784
CPC分类号： H01L27/0883 , H01L21/28035 , H01L21/823842 , H01L27/0925 , H01L29/4916 , H01L29/78
摘要： A p-channel depletion device (10) in a MOSFET is formed and preferably comprises a silicon substrate (12), an N-well region (14), P+ source (16) and drain (18) regions, and a polysilicon gate (20) which has been appropriately doped to be of a P- conductivity type. The resulting structure performs analogously to a depletion device formed in accordance with conventional methods wherein a depletion mask and implant are utilized, and is characterized by having a threshold voltage of approximately +250 millivolts.
摘要翻译：形成MOSFET中的p沟道耗尽器件（10），并且优选地包括硅衬底（12），N阱区域（14），P +源极（16）和漏极（18）区域以及多晶硅栅极 20），其被适当地掺杂为具有P-导电型。所得到的结构类似于根据常规方法形成的耗尽装置，其中利用了耗尽掩模和植入物，并且其特征在于具有大约+250毫伏的阈值电压。

9. 发明公开

EP0355951A2 Semiconductor device with memory cell region and a peripheral circuit and method of manufacturing the same 失效
标题翻译：具有用于存储单元和外围电路，以及它们的制造方法的一个区域的半导体器件。
公开(公告)号：EP0355951A2
公开(公告)日：1990-02-28
申请号：EP89305217.5
申请日：1989-05-23
申请人： SEIKO EPSON CORPORATION
发明人： Maruo, Yukata
IPC分类号： H01L27/115 , H01L21/82 , H01L29/08 , G11C17/00
CPC分类号： H01L27/0925 , H01L21/823456 , H01L27/105 , Y10S257/90
摘要： A semi-conductor memory comprises a memory cell region and a peripheral circuit. The memory cell region includes a plurality of memory transistors (Qn, Qm) of a first conductivity type and a plurality of select transistors (Qn, Qw) of the first conductivity type. The peripheral circuit includes transistors (Qn) of the first conductivity type and also transistors (Qp) of a second conductivity type. The transistors of the first conductivity type each have a first off-set region (21, 121) defined by a low concentration impurity region having a substantially flat surface, the first off-set region being formed in a substrate (10, 110) adjacent to a first gate electrode (20, 120). The transistors of the second conductivity type each have a thick insulating film (15) provided adjacent to a second gate electrode (16) with a part thereof buried in the substrate, and a second off-set region (17) defined by a low concentration impurity region provided in a portion of the substrate under the thick insulating film.
摘要翻译：的半导体存储器包括存储单元区域和外围电路。存储单元区包括一第一导电型的存储晶体管（QN，QM）和第一导电类型的选择晶体管的多个（QN，QW）的复数。外围电路包括第二导电类型的第一导电类型的晶体管（QN），因此晶体管（QP）。第一导电类型的晶体管的每个具有第一偏置的区域（21，121）由具有基本上平坦表面的低浓度杂质区域所定义的，第一脏区域在一个基板（10，110）相邻而形成到第一栅电极（20，120）。第二导电类型的晶体管的每个具有（15）相邻设置的第二栅极电极（16）其一部分埋在基材由低浓度所定义的厚的绝缘片，以及一个第二偏置的区域（17）厚的绝缘电影下在基板的一部分上设置杂质区域。

10. 发明公开

EP0346632A2 Integrated trench-transistor structure and fabrication process 失效
标题翻译： Integrierte Grabentransistorstruktur und Herstellungsverfahren。
公开(公告)号：EP0346632A2
公开(公告)日：1989-12-20
申请号：EP89108839.5
申请日：1989-05-17
申请人： International Business Machines Corporation
发明人： Davari, Bijan , Hwang, Wei , Lu, Nicky C.
IPC分类号： H01L27/08 , H01L21/82
CPC分类号： H01L29/7827 , H01L21/823885 , H01L27/0925 , H01L29/4236 , H01L29/66666
摘要： An integrated, self-aligned trench-transistor structure including trench CMOS devices and vertical "strapping transistors" wherein the shallow trench transistors and the strapping trench-transistors are built on top of buried source junctions. A p- epitaxial layer (12) is grown on a substrate (10) and contains an n-well (14), and n+ source (16) and p+ source regions (18). Shallow trenches (20, 22) are disposed in the epitaxial layer (12) and contain n+ polysilicon or metal, such as tungsten, to provide the trench CMOS gates. A gate contact region (24) connects the trenches (20, 22) and the n+ polysilicon or metal in the trenches. The n+ polysilicon or metal in the trenches are isolated by a thin layer (26) of silicon dioxide on the trench walls of the gates. The p+ drain region (28), along with the filled trench gate element and the p+ source region (18), form a vertical p-channel (PMOS) trench-transistor. The n+ drain region (30), along with filled trench gate element and the n+ source (16) form a vertical n-channel (NMOS) transistor. The PMOS and NMOS trench transistors are isolated by shallow trench isolation regions (34) and an oxide layer (38).
摘要翻译：包括沟槽CMOS器件和垂直“捆扎晶体管”的集成的自对准沟槽晶体管结构，其中浅沟槽晶体管和捆扎沟槽晶体管构建在掩埋源极结的顶部。在衬底（10）上生长p-外延层（12）并且包含n阱（14），以及n +源极（16）和p +源极区域（18）。浅沟槽（20,22）设置在外延层（12）中并且包含n +多晶硅或诸如钨的金属，以提供沟槽CMOS栅极。栅极接触区域（24）连接沟槽（20,22）和沟槽中的n +多晶硅或金属。沟槽中的n +多晶硅或金属被栅极的沟槽壁上的二氧化硅薄层（26）隔离。 p +漏极区（28）与填充沟槽栅极元件和p +源极区（18）一起形成垂直p沟道（PMOS）沟槽晶体管。 n +漏极区（30）以及填充的沟槽栅极元件和n +源极（16）形成垂直的n沟道（NMOS）晶体管。 PMOS和NMOS沟槽晶体管由浅沟槽隔离区（34）和氧化物层（38）隔离。

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