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1. 发明公开

EP0774786A2 CMOS semiconductor device 失效
标题翻译： CMOS半导体器件
公开(公告)号：EP0774786A2
公开(公告)日：1997-05-21
申请号：EP96118200.3
申请日：1996-11-13
申请人： NEC CORPORATION
发明人： Tsuboi, Toshihide
IPC分类号： H01L27/092 , H01L27/02 , G09G3/18
CPC分类号： G09G3/18 , H01L27/0251 , H01L27/0266 , H01L27/0925 , H01L2924/0002 , H01L2924/00
摘要： An improved layout of transistors near LCD drive terminals in a CMOS semiconductor device to reduce a chip size without damaging resistances against electrostatic destruction and latch-up. MOSFETs whose sources are connected to neither an electric source nor a ground are selectively arranged between two protective diffusion layers having different polarities, connected to a terminal.

2. 发明授权

EP0376285B1 Microcomputer having electrically erasable and programmable nonvolatile memory 失效
标题翻译：有电可擦除和可编程的非易失性存储器的微型计算机。
公开(公告)号：EP0376285B1
公开(公告)日：1994-03-09
申请号：EP89124030.1
申请日：1989-12-27
申请人： NEC CORPORATION
发明人： Tsuboi, Toshihide
IPC分类号： G11C16/06
CPC分类号： G11C16/30 , G11C16/08 , G11C16/32 , G11C2216/20

3. 发明公开

EP0376285A2 Microcomputer having electrically erasable and programmable nonvolatile memory 失效
标题翻译： Mikrorechner mit einem elektrischlöschbarenund programmierbarennichtflüchtigenSpeicher。
公开(公告)号：EP0376285A2
公开(公告)日：1990-07-04
申请号：EP89124030.1
申请日：1989-12-27
申请人： NEC CORPORATION
发明人： Tsuboi, Toshihide
IPC分类号： G11C16/06
CPC分类号： G11C16/30 , G11C16/08 , G11C16/32 , G11C2216/20
摘要： The invention describes a microcomputer comprising an electrically erasable and programmable nonvolatile memory, a central processing unit executing a program and issuing a data write request and a data read request to said nonvolatile memory, and a control circuit coupled to said nonvolatile memory and said central processing unit, said control circuit including timer means for counting a time to generate an operation end signal, first means responsive to said data write request for performing a data write process in which data stored in a selected memory cell of said nonvolatile memory is first erased and new data is then written into said selected memory cell, second means responsive to said operation end signal for terminating said data write process, third means responsive to said data read request issued during said data write process for suspending said data write process, for reading out data from a selected memory cell and thereafter for resuming the suspended data write process, and fourth means for suspending a time count operation of said timer means during a period relative to a suspended period of said data write process.
摘要翻译：本发明描述了一种包括电可擦除和可编程非易失性存储器的微型计算机，执行程序并向所述非易失性存储器发出数据写入请求和数据读取请求的中央处理单元，以及耦合到所述非易失性存储器和所述中央处理的控制电路所述控制电路包括用于对产生操作结束信号的时间进行计数的定时器装置，第一装置响应于所述数据写请求执行数据写入处理，其中存储在所述非易失性存储器的选定存储单元中的数据首先被擦除，然后将新数据写入所述选择的存储单元，第二装置响应于所述操作结束信号终止所述数据写入处理，第三装置响应于在所述数据写入过程期间发出的暂停所述数据写入处理的所述数据读取请求，用于读出来自所选择的存储器单元的数据，然后用于恢复暂停的数据写入过程 ss和第四装置，用于在相对于所述数据写入处理的暂停时段期间暂停所述定时器装置的时间计数操作。

4. 发明公开

EP0774786A3 CMOS semiconductor device 失效
标题翻译： CMOS-Halbleiter-Bauteil
公开(公告)号：EP0774786A3
公开(公告)日：1999-11-03
申请号：EP96118200.3
申请日：1996-11-13
申请人： NEC CORPORATION
发明人： Tsuboi, Toshihide
IPC分类号： H01L27/092 , H01L27/02 , G09G3/18
CPC分类号： G09G3/18 , H01L27/0251 , H01L27/0266 , H01L27/0925 , H01L2924/0002 , H01L2924/00
摘要： An improved layout of transistors near LCD drive terminals in a CMOS semiconductor device to reduce a chip size without damaging resistances against electrostatic destruction and latch-up. MOSFETs whose sources are connected to neither an electric source nor a ground are selectively arranged between two protective diffusion layers having different polarities, connected to a terminal.
摘要翻译：在CMOS半导体器件中的LCD驱动端子附近的晶体管的改进的布局，以减少芯片尺寸而不损害抗静电破坏和闭锁的电阻。源极不连接到电源和接地的MOSFET选择性地布置在具有不同极性的两个保护性扩散层之间，连接到端子。

5. 发明公开

EP0410492A3 Non-volatile semiconductor memory device having an improved testing mode of operation and method of forming checkerwise test pattern in memory cell array 失效
标题翻译：具有改进的测试操作模式的非易失性半导体存储器件以及在存储器单元阵列中形成检查模式的方法
公开(公告)号：EP0410492A3
公开(公告)日：1991-12-18
申请号：EP90114519.3
申请日：1990-07-27
申请人： NEC CORPORATION
发明人： Tsuboi, Toshihide , Funahashi, Norio
IPC分类号： G11C29/00
CPC分类号： G11C29/34
摘要： An EEPROM device comprises a memory cell array (3) having a plurality of non-volatile memory cells (3-1 to 3-256) respectively disposed at locations de fined by word lines (W0 to W31) and bit lines (BL0 to BL7) and memorizing pieces of data information in a rewriteable manner, respectively, a row address decoder circuit (1) responsive to an address signal indicative of a row address for selectively activating one of the word lines, a column address decoder circuit (2) responsive to an address signal indicative of a column address for selecting one of the bit lines, and a data control unit (4 to 9) selectively carrying out erasing, write-in and read-out operations on one of the non-volatile memory cells, in which tle row address decoder circuit is further operative to concurrently activate every second word line in the presence of the row address signal indicative of a first state and to concurrently activate another group of the word lines in the presence of the row address signal indicative of a second state in a testing mode of operation, and in which the data control unit carries out the erase and write-in operations on a plurality of the non-volatile memory cells coupled to the word lines to be activated in the testing mode of operation.

6. 发明公开

EP0410492A2 Non-volatile semiconductor memory device having an improved testing mode of operation and method of forming checkerwise test pattern in memory cell array 失效
标题翻译：与测试模式和在存储单元矩阵形成的Schachbrettprüfmustern方法，一种非易失性半导体存储器件。
公开(公告)号：EP0410492A2
公开(公告)日：1991-01-30
申请号：EP90114519.3
申请日：1990-07-27
申请人： NEC CORPORATION
发明人： Tsuboi, Toshihide , Funahashi, Norio
IPC分类号： G11C29/00
CPC分类号： G11C29/34
摘要： An EEPROM device comprises a memory cell array (3) having a plurality of non-volatile memory cells (3-1 to 3-256) respectively disposed at locations de fined by word lines (W0 to W31) and bit lines (BL0 to BL7) and memorizing pieces of data information in a rewriteable manner, respectively, a row address decoder circuit (1) responsive to an address signal indicative of a row address for selectively activating one of the word lines, a column address decoder circuit (2) responsive to an address signal indicative of a column address for selecting one of the bit lines, and a data control unit (4 to 9) selectively carrying out erasing, write-in and read-out operations on one of the non-volatile memory cells, in which tle row address decoder circuit is further operative to concurrently activate every second word line in the presence of the row address signal indicative of a first state and to concurrently activate another group of the word lines in the presence of the row address signal indicative of a second state in a testing mode of operation, and in which the data control unit carries out the erase and write-in operations on a plurality of the non-volatile memory cells coupled to the word lines to be activated in the testing mode of operation.
摘要翻译：分别向EEPROM器件包括：（3），其具有位置处布置的非易失性存储器单元（3-1至3-256）的多个A存储单元阵列通过字线（W0至W31）和位线（BL0至BL7 DE罚款）和记忆的数据信息段在一个可重写的方式，分别，行地址解码器电路（1）在指示的行地址，用于选择性激活所述字线中的一个，列地址解码器电路（2），响应地址信号以响应向地址信号指示的列地址选择位线中的一个，并且数据控制单元（4〜9）选择地执行擦除，写入和读出操作的非易失性存储器单元中的一个，在哪一个TLE行地址解码器电路可操作以进一步同时激活的行地址信号的存在每一第二字线指示第一状态，并且，以同时激活另一组字线中的行地址信号INDI的存在在操作的测试模式的第二状态的cative，并且其中所述数据控制单元执行在耦合到所述字线的非易失性存储器单元的多个擦除和写入操作在测试模式下被激活的操作。

7. 发明公开

EP0376285A3 Microcomputer having electrically erasable and programmable nonvolatile memory 失效
标题翻译：具有电可擦除和可编程非易失性存储器的微型计算机
公开(公告)号：EP0376285A3
公开(公告)日：1990-09-05
申请号：EP89124030.1
申请日：1989-12-27
申请人： NEC CORPORATION
发明人： Tsuboi, Toshihide
IPC分类号： G11C16/06
CPC分类号： G11C16/30 , G11C16/08 , G11C16/32 , G11C2216/20
摘要： The invention describes a microcomputer comprising an electrically erasable and programmable nonvolatile memory, a central processing unit executing a program and issuing a data write request and a data read request to said nonvolatile memory, and a control circuit coupled to said nonvolatile memory and said central processing unit, said control circuit including timer means for counting a time to generate an operation end signal, first means responsive to said data write request for performing a data write process in which data stored in a selected memory cell of said nonvolatile memory is first erased and new data is then written into said selected memory cell, second means responsive to said operation end signal for terminating said data write process, third means responsive to said data read request issued during said data write process for suspending said data write process, for reading out data from a selected memory cell and thereafter for resuming the suspended data write process, and fourth means for suspending a time count operation of said timer means during a period relative to a suspended period of said data write process.

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