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1. 发明公开

EP0346632A2 Integrated trench-transistor structure and fabrication process 失效
标题翻译： Integrierte Grabentransistorstruktur und Herstellungsverfahren。
公开(公告)号：EP0346632A2
公开(公告)日：1989-12-20
申请号：EP89108839.5
申请日：1989-05-17
申请人： International Business Machines Corporation
发明人： Davari, Bijan , Hwang, Wei , Lu, Nicky C.
IPC分类号： H01L27/08 , H01L21/82
CPC分类号： H01L29/7827 , H01L21/823885 , H01L27/0925 , H01L29/4236 , H01L29/66666
摘要： An integrated, self-aligned trench-transistor structure including trench CMOS devices and vertical "strapping transistors" wherein the shallow trench transistors and the strapping trench-transistors are built on top of buried source junctions. A p- epitaxial layer (12) is grown on a substrate (10) and contains an n-well (14), and n+ source (16) and p+ source regions (18). Shallow trenches (20, 22) are disposed in the epitaxial layer (12) and contain n+ polysilicon or metal, such as tungsten, to provide the trench CMOS gates. A gate contact region (24) connects the trenches (20, 22) and the n+ polysilicon or metal in the trenches. The n+ polysilicon or metal in the trenches are isolated by a thin layer (26) of silicon dioxide on the trench walls of the gates. The p+ drain region (28), along with the filled trench gate element and the p+ source region (18), form a vertical p-channel (PMOS) trench-transistor. The n+ drain region (30), along with filled trench gate element and the n+ source (16) form a vertical n-channel (NMOS) transistor. The PMOS and NMOS trench transistors are isolated by shallow trench isolation regions (34) and an oxide layer (38).
摘要翻译：包括沟槽CMOS器件和垂直“捆扎晶体管”的集成的自对准沟槽晶体管结构，其中浅沟槽晶体管和捆扎沟槽晶体管构建在掩埋源极结的顶部。在衬底（10）上生长p-外延层（12）并且包含n阱（14），以及n +源极（16）和p +源极区域（18）。浅沟槽（20,22）设置在外延层（12）中并且包含n +多晶硅或诸如钨的金属，以提供沟槽CMOS栅极。栅极接触区域（24）连接沟槽（20,22）和沟槽中的n +多晶硅或金属。沟槽中的n +多晶硅或金属被栅极的沟槽壁上的二氧化硅薄层（26）隔离。 p +漏极区（28）与填充沟槽栅极元件和p +源极区（18）一起形成垂直p沟道（PMOS）沟槽晶体管。 n +漏极区（30）以及填充的沟槽栅极元件和n +源极（16）形成垂直的n沟道（NMOS）晶体管。 PMOS和NMOS沟槽晶体管由浅沟槽隔离区（34）和氧化物层（38）隔离。

2. 发明公开

EP0346632A3 Integrated trench-transistor structure and fabrication process 失效
标题翻译：一体化晶体管结构和制造工艺
公开(公告)号：EP0346632A3
公开(公告)日：1991-06-05
申请号：EP89108839.5
申请日：1989-05-17
申请人： International Business Machines Corporation
发明人： Davari, Bijan , Hwang, Wei , Lu, Nicky C.
IPC分类号： H01L27/08 , H01L21/82
CPC分类号： H01L29/7827 , H01L21/823885 , H01L27/0925 , H01L29/4236 , H01L29/66666
摘要： An integrated, self-aligned trench-transistor structure including trench CMOS devices and vertical "strapping transistors" wherein the shallow trench transistors and the strapping trench-transistors are built on top of buried source junctions. A p- epitaxial layer (12) is grown on a substrate (10) and contains an n-well (14), and n+ source (16) and p+ source regions (18). Shallow trenches (20, 22) are disposed in the epitaxial layer (12) and contain n+ polysilicon or metal, such as tungsten, to provide the trench CMOS gates. A gate contact region (24) connects the trenches (20, 22) and the n+ polysilicon or metal in the trenches. The n+ polysilicon or metal in the trenches are isolated by a thin layer (26) of silicon dioxide on the trench walls of the gates. The p+ drain region (28), along with the filled trench gate element and the p+ source region (18), form a vertical p-channel (PMOS) trench-transistor. The n+ drain region (30), along with filled trench gate element and the n+ source (16) form a vertical n-channel (NMOS) transistor. The PMOS and NMOS trench transistors are isolated by shallow trench isolation regions (34) and an oxide layer (38).

3. 发明授权

EP0300157B1 Vertical transistor capacitor memory cell structure and fabrication method therefor 失效
标题翻译：垂直晶体管电容器存储单元结构及其制造方法
公开(公告)号：EP0300157B1
公开(公告)日：1993-05-05
申请号：EP88108135.0
申请日：1988-05-20
申请人： International Business Machines Corporation
发明人： Hwang, Wei , Lu, Nicky C.
IPC分类号： H01L21/82 , H01L27/108
CPC分类号： H01L27/10864 , H01L29/66181 , H01L29/945

4. 发明公开

EP0354348A2 CMOS-transistor and one-capacitor dram cell and fabrication process therefor 失效
标题翻译： DRAM-Zelle aus einem CMOS-Transistor und einem Einkondensator und deren Herstellungsverfahren。
公开(公告)号：EP0354348A2
公开(公告)日：1990-02-14
申请号：EP89112325.9
申请日：1989-07-06
申请人： International Business Machines Corporation
发明人： Dhong, Sang H. , Henkels, Walter H. , Lu, Nicky C.
IPC分类号： G11C11/404 , G11C11/24
CPC分类号： G11C11/404 , H01L27/0688 , H01L27/108
摘要： A complementary MOS one-capacitor dynamic RAM cell (e.g. 38) operates with a non-boosted wordline without a threshold loss problem. It includes one storage capacitor (30) and n- and p-type transfer devices (10, 12) connected to the storage capacitor which function as two complementary transistor devices having gates controlled by complementary signals on the RAM wordlines (26, 28).
摘要翻译：互补MOS单电容器动态RAM单元（例如38）利用没有阈值损失问题的非升压字线操作。它包括一个存储电容器（30）和连接到存储电容器的n型和p型转移装置（10,12），其作为具有由RAM字线（26,28）上的互补信号控制的门的两个互补晶体管器件。

5. 发明公开

EP0300157A2 Vertical transistor capacitor memory cell structure and fabrication method therefor 失效
标题翻译： Vertikale晶体管/Kapazitätspeicherzellen-Struktur und Herstellungsverfahrendafür。
公开(公告)号：EP0300157A2
公开(公告)日：1989-01-25
申请号：EP88108135.0
申请日：1988-05-20
申请人： International Business Machines Corporation
发明人： Hwang, Wei , Lu, Nicky C.
IPC分类号： H01L21/82 , H01L27/108
CPC分类号： H01L27/10864 , H01L29/66181 , H01L29/945
摘要： A semiconductor memory cell structure incorporating a vertical access transistor over a trench storage capacitor including a semiconductor wafer having a semiconductor substrate (16) and an epitaxial layer (36) disposed thereon. A relatively deep polysilicon filled trench (26) is disposed in the epitaxial layer and substrate structure, the deep trench (26) having a composite oxide/nitride insulation layer (24) over its vertical and horizontal surfaces to provide a storage capacitor insulator. A relatively shallow trench is disposed in the epitaxial layer (36) over the deep trench (26) region, the shallow trench having an oxide insulation layer (46) on its vertical and horizontal surfaces thereof. A neck structure (34) of epitaxial polysilicon material extends from the top surface of the polysilicon filled deep trench (26) to the bottom surface of the shallow trench. Impurities are disposed in the epitaxial layer (36) on either side of the shallow trench to form semiconductor device drain (40) junctions and polysilicon material (48) is disposed in the shallow trench and over the epitaxial layer (36) to form semiconductor device transfer gate and wordline regions respectively.
摘要翻译：一种半导体存储单元结构，其包括在包括半导体衬底（16）和设置在其上的外延层（36）的半导体晶片的沟槽存储电容器上的垂直存取晶体管。在外延层和衬底结构中设置相对深的多晶硅填充沟槽（26），深沟槽（26）在其垂直和水平表面上具有复合氧化物/氮化物绝缘层（24），以提供存储电容器绝缘体。在深沟槽（26）区域上的外延层（36）中设置相对浅的沟槽，浅沟槽在其垂直和水平表面上具有氧化物绝缘层（46）。外延多晶硅材料的颈部结构（34）从多晶硅填充的深沟槽（26）的顶表面延伸到浅沟槽的底表面。杂质布置在浅沟槽的任一侧上的外延层（36）中以形成半导体器件漏极（40）结，多晶硅材料（48）设置在浅沟槽中并且在外延层（36）上方形成半导体器件传输门和字线区域。

6. 发明授权

EP0346632B1 Integrated trench-transistor structure and fabrication process 失效
标题翻译：集成严重晶体管结构及其制造方法
公开(公告)号：EP0346632B1
公开(公告)日：1996-01-03
申请号：EP89108839.5
申请日：1989-05-17
申请人： International Business Machines Corporation
发明人： Davari, Bijan , Hwang, Wei , Lu, Nicky C.
IPC分类号： H01L27/08
CPC分类号： H01L29/7827 , H01L21/823885 , H01L27/0925 , H01L29/4236 , H01L29/66666

7. 发明公开

EP0354348A3 CMOS-transistor and one-capacitor dram cell and fabrication process therefor 失效
标题翻译： CMOS晶体管和单电容器DRAM单元及其制造工艺
公开(公告)号：EP0354348A3
公开(公告)日：1991-06-05
申请号：EP89112325.9
申请日：1989-07-06
申请人： International Business Machines Corporation
发明人： Dhong, Sang H. , Henkels, Walter H. , Lu, Nicky C.
IPC分类号： G11C11/404 , G11C11/24
CPC分类号： G11C11/404 , H01L27/0688 , H01L27/108
摘要： A complementary MOS one-capacitor dynamic RAM cell (e.g. 38) operates with a non-boosted wordline without a threshold loss problem. It includes one storage capacitor (30) and n- and p-type transfer devices (10, 12) connected to the storage capacitor which function as two complementary transistor devices having gates controlled by complementary signals on the RAM wordlines (26, 28).

8. 发明公开

EP0300157A3 Vertical transistor capacitor memory cell structure and fabrication method therefor 失效
标题翻译：垂直晶体管电容器存储单元结构及其制造方法
公开(公告)号：EP0300157A3
公开(公告)日：1989-09-13
申请号：EP88108135.0
申请日：1988-05-20
申请人： International Business Machines Corporation
发明人： Hwang, Wei , Lu, Nicky C.
IPC分类号： H01L21/82 , H01L27/108
CPC分类号： H01L27/10864 , H01L29/66181 , H01L29/945
摘要： A semiconductor memory cell structure incorporating a vertical access transistor over a trench storage capacitor including a semiconductor wafer having a semiconductor substrate (16) and an epitaxial layer (36) disposed thereon. A relatively deep polysilicon filled trench (26) is disposed in the epitaxial layer and substrate structure, the deep trench (26) having a composite oxide/nitride insulation layer (24) over its vertical and horizontal surfaces to provide a storage capacitor insulator. A relatively shallow trench is disposed in the epitaxial layer (36) over the deep trench (26) region, the shallow trench having an oxide insulation layer (46) on its vertical and horizontal surfaces thereof. A neck structure (34) of epitaxial polysilicon material extends from the top surface of the polysilicon filled deep trench (26) to the bottom surface of the shallow trench. Impurities are disposed in the epitaxial layer (36) on either side of the shallow trench to form semiconductor device drain (40) junctions and polysilicon material (48) is disposed in the shallow trench and over the epitaxial layer (36) to form semiconductor device transfer gate and wordline regions respectively.

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