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1. 发明公开

EP0355951A2 Semiconductor device with memory cell region and a peripheral circuit and method of manufacturing the same 失效
标题翻译：具有用于存储单元和外围电路，以及它们的制造方法的一个区域的半导体器件。
公开(公告)号：EP0355951A2
公开(公告)日：1990-02-28
申请号：EP89305217.5
申请日：1989-05-23
申请人： SEIKO EPSON CORPORATION
发明人： Maruo, Yukata
IPC分类号： H01L27/115 , H01L21/82 , H01L29/08 , G11C17/00
CPC分类号： H01L27/0925 , H01L21/823456 , H01L27/105 , Y10S257/90
摘要： A semi-conductor memory comprises a memory cell region and a peripheral circuit. The memory cell region includes a plurality of memory transistors (Qn, Qm) of a first conductivity type and a plurality of select transistors (Qn, Qw) of the first conductivity type. The peripheral circuit includes transistors (Qn) of the first conductivity type and also transistors (Qp) of a second conductivity type. The transistors of the first conductivity type each have a first off-set region (21, 121) defined by a low concentration impurity region having a substantially flat surface, the first off-set region being formed in a substrate (10, 110) adjacent to a first gate electrode (20, 120). The transistors of the second conductivity type each have a thick insulating film (15) provided adjacent to a second gate electrode (16) with a part thereof buried in the substrate, and a second off-set region (17) defined by a low concentration impurity region provided in a portion of the substrate under the thick insulating film.
摘要翻译：的半导体存储器包括存储单元区域和外围电路。存储单元区包括一第一导电型的存储晶体管（QN，QM）和第一导电类型的选择晶体管的多个（QN，QW）的复数。外围电路包括第二导电类型的第一导电类型的晶体管（QN），因此晶体管（QP）。第一导电类型的晶体管的每个具有第一偏置的区域（21，121）由具有基本上平坦表面的低浓度杂质区域所定义的，第一脏区域在一个基板（10，110）相邻而形成到第一栅电极（20，120）。第二导电类型的晶体管的每个具有（15）相邻设置的第二栅极电极（16）其一部分埋在基材由低浓度所定义的厚的绝缘片，以及一个第二偏置的区域（17）厚的绝缘电影下在基板的一部分上设置杂质区域。

2. 发明公开

EP0355951A3 Semiconductor device with memory cell region and a peripheral circuit and method of manufacturing the same 失效
标题翻译：具有存储单元区域的半导体器件和外围电路及其制造方法
公开(公告)号：EP0355951A3
公开(公告)日：1992-02-19
申请号：EP89305217.5
申请日：1989-05-23
申请人： SEIKO EPSON CORPORATION
发明人： Maruo, Yukata
IPC分类号： H01L27/115 , H01L21/82 , H01L29/08 , G11C17/00
CPC分类号： H01L27/0925 , H01L21/823456 , H01L27/105 , Y10S257/90
摘要： A semi-conductor memory comprises a memory cell region and a peripheral circuit. The memory cell region includes a plurality of memory transistors (Qn, Qm) of a first conductivity type and a plurality of select transistors (Qn, Qw) of the first conductivity type. The peripheral circuit includes transistors (Qn) of the first conductivity type and also transistors (Qp) of a second conductivity type. The transistors of the first conductivity type each have a first off-set region (21, 121) defined by a low concentration impurity region having a substantially flat surface, the first off-set region being formed in a substrate (10, 110) adjacent to a first gate electrode (20, 120). The transistors of the second conductivity type each have a thick insulating film (15) provided adjacent to a second gate electrode (16) with a part thereof buried in the substrate, and a second off-set region (17) defined by a low concentration impurity region provided in a portion of the substrate under the thick insulating film.

3. 发明授权

EP0355951B1 Semiconductor device with memory cell region and a peripheral circuit and method of manufacturing the same 失效
标题翻译：具有用于存储单元和外围电路，以及它们的制造方法的一个区域的半导体器件。
公开(公告)号：EP0355951B1
公开(公告)日：1995-08-09
申请号：EP89305217.5
申请日：1989-05-23
申请人： SEIKO EPSON CORPORATION
发明人： Maruo, Yukata
IPC分类号： H01L27/115 , H01L21/82 , H01L29/08 , G11C17/00
CPC分类号： H01L27/0925 , H01L21/823456 , H01L27/105 , Y10S257/90

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