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1. 发明公开

EP3325264A1 SUBSTRAT FÜR ELEKTRISCHE SCHALTKREISE UND VERFAHREN ZUR HERSTELLUNG EINES DERARTIGEN SUBSTRATES 审中-公开
公开(公告)号：EP3325264A1
公开(公告)日：2018-05-30
申请号：EP16741600.7
申请日：2016-07-18
申请人： Rogers Germany GmbH
发明人： MEYER, Andreas , SCHMIDT, Karsten
IPC分类号： B32B5/12 , B32B5/20 , B32B7/12 , B32B9/00 , B32B9/04 , B32B9/06 , B32B29/08
CPC分类号： B32B9/005 , B32B5/12 , B32B5/20 , B32B7/12 , B32B9/041 , B32B9/06 , B32B15/043 , B32B15/12 , B32B15/20 , B32B29/002 , B32B29/08 , B32B2255/06 , B32B2255/205 , B32B2255/26 , B32B2255/28 , B32B2264/107 , B32B2307/202 , B32B2307/206 , B32B2307/54 , B32B2457/08 , B32B2605/00 , C25D11/005 , C25D11/04 , C25D11/08 , C25D17/12 , H01L23/3735 , H05K1/0201 , H05K1/0313 , H05K1/053 , H05K3/4688 , H05K2201/0116 , H05K2201/0338 , H05K2203/0315 , H05K2203/11 , H05K2203/1126
摘要： The invention relates to a substrate (1, 10) for electrical circuits, comprising at least one metal layer (2, 3, 14) and a paper ceramic layer (11), which is joined face to face with the at least one metal layer (2, 3, 14) and has a top side and bottom side (11a, 11b), wherein the paper ceramic layer (11) has a large number of cavities in the form of pores. Especially advantageously, the at least one metal layer (2, 3, 14) is connected to the paper ceramic layer (11) by means of at least one glue layer (6, 6a, 6b), which is produced by applying at least one glue (6a', 6a'', 6b', 6b'') to the metal layer (2, 3, 14) and/or to the paper ceramic layer (11), wherein the cavities in the form of pores in the paper ceramic layer (11) are filled at least at the surface by means of the applied glue (6a', 6a'', 6b', 6b'').

2. 发明公开

EP3125285A4 PAD-ARRAY STRUCTURE ON SUBSTRATE FOR MOUNTING IC CHIP ON SUBSTRATE, AND OPTICAL MODULE HAVING SAID PAD-ARRAY STRUCTURE 审中-公开
公开(公告)号：EP3125285A4
公开(公告)日：2017-11-29
申请号：EP15769376
申请日：2015-03-18
申请人： PHOTONICS ELECTRONICS TECHNOLOGY RES ASS
发明人： AKAGAWA TAKESHI , YASHIKI KENICHIRO
IPC分类号： H01L23/12 , H05K1/02 , H05K3/34
CPC分类号： H05K1/111 , G02B6/122 , G02B6/4232 , H01L23/49844 , H01L2224/16225 , H05K1/0219 , H05K1/0243 , H05K1/0245 , H05K1/0251 , H05K1/181 , H05K3/4688 , H05K2201/10121 , H05K2201/10734 , Y02P70/611
摘要： A pad-array arrangement structure on a substrate for mounting an IC chip on the substrate, wherein a structure with which it is possible to maximally avoid an increase in the number of wiring layers on the substrate is obtained by devising the pad arrangement in an IC pad-array region. A embodiment of the present invention provides a pad-array structure on a substrate for mounting an IC chip on the substrate. The present invention is characterized in that: a plurality of ground pads arrayed equidistantly in a first row, and a plurality of signal pads arrayed equidistantly in a second row on the inside of and parallel to the first row, are provided on a first circumferential edge in the pad-array region; each of the signal pads passes between two adjacent ground pads in the first row and is connected to an external circuit on the substrate; and electrical signals are input to and output from the external circuit.

3. 发明授权

EP2609796B1 MEHREBENENLEITERPLATTE FÜR HOCHFREQUENZ-ANWENDUNGEN 有权转让
标题翻译：用于高频应用的多频率板
公开(公告)号：EP2609796B1
公开(公告)日：2017-11-08
申请号：EP11802260.7
申请日：2011-08-17
申请人： Conti Temic Microelectronic GmbH
发明人： MÖLLER, Ulrich , SCHÄFER, Maik
IPC分类号： H05K1/16 , H05K1/02 , H05K3/46
CPC分类号： H05K1/162 , H05K1/0231 , H05K1/0234 , H05K1/0251 , H05K3/4688

4. 发明公开

EP3196934A1 MULTIMODULE INTERCONNECT STRUCTURE AND PROCESS 审中-公开
标题翻译：多机器人互连结构与过程
公开(公告)号：EP3196934A1
公开(公告)日：2017-07-26
申请号：EP17156114.5
申请日：1999-08-26
申请人： General Electric Company
发明人： WOJNAROWSKI, Robert John , FILLION, Raymond Albert , WOLFGANG, Daum , KOLC, Ronald Frank , KUK, Donald William
IPC分类号： H01L23/538 , H01L21/48 , H01L21/58 , H01L25/065
CPC分类号： H01L23/5389 , H01L23/3107 , H01L23/3135 , H01L23/5383 , H01L23/5385 , H01L24/20 , H01L24/24 , H01L24/25 , H01L24/81 , H01L24/82 , H01L24/83 , H01L24/92 , H01L24/97 , H01L25/0655 , H01L2224/02377 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/24137 , H01L2224/24227 , H01L2224/291 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2224/81801 , H01L2224/82039 , H01L2224/8319 , H01L2224/8385 , H01L2224/83851 , H01L2224/9202 , H01L2224/97 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/10329 , H01L2924/12042 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15192 , H01L2924/15787 , H01L2924/181 , H05K3/323 , H05K3/3436 , H05K3/4688 , Y10T29/49121 , Y10T29/49126 , Y10T29/49144 , H01L2924/00014 , H01L2224/81 , H01L2224/83 , H01L2224/82 , H01L2924/00
摘要： A circuit design is logically partitioned into a plurality of blocks. As a first hierarchial assembly level, the blocks are fabricated as individual submodules (20, 21) each including at least one electronic component (22, 24) with component connection pads (26, 28, 30, 32) on a top surface (34, 36), and a first interconnect structure (50) including at least one interconnect layer (56, 58) bonded to the top surfaces (34, 36), and interconnecting selected ones of the component connection pads (26, 28, 30, 32). Submodule connection pads (76) are provided on upper surfaces (78) of the submodules (20, 21). As a second hierarchial assembly level, a second interconnect structure (186) is bonded to the upper surfaces (78) and interconnects selected ones of the submodule connection pads (76).
摘要翻译：电路设计在逻辑上被划分成多个块。作为第一分级组装级别，所述块被制造为单独的子模块（20,21），每个子模块包括至少一个电子组件（22,24），所述电子组件具有在顶表面（34）上的组件连接垫（26,28,30,32），所述第一互连结构（50）包括结合到所述顶表面（34,36）的至少一个互连层（56,58），并且将所选择的所述部件连接垫（26,28,30,32） 32）。子模块连接垫（76）设置在子模块（20,21）的上表面（78）上。作为第二分级组装层次，第二互连结构（186）结合到上表面（78）并互连选定的子模块连接垫（76）。

5. 发明公开

EP3125285A1 PAD-ARRAY STRUCTURE ON SUBSTRATE FOR MOUNTING IC CHIP ON SUBSTRATE, AND OPTICAL MODULE HAVING SAID PAD-ARRAY STRUCTURE 有权
标题翻译： PAD阵列结构上安装IC芯片上的基板，以及光学模块，该焊盘阵列结构的基底
公开(公告)号：EP3125285A1
公开(公告)日：2017-02-01
申请号：EP15769376.3
申请日：2015-03-18
申请人： Photonics Electronics Technology Research Association
发明人： AKAGAWA, Takeshi , YASHIKI, Kenichiro
IPC分类号： H01L23/12 , H05K1/02 , H05K3/34
CPC分类号： H05K1/111 , G02B6/122 , G02B6/4232 , H01L23/49844 , H01L2224/16225 , H05K1/0219 , H05K1/0243 , H05K1/0245 , H05K1/0251 , H05K1/181 , H05K3/4688 , H05K2201/10121 , H05K2201/10734 , Y02P70/611
摘要： A pad-array arrangement structure on a substrate for mounting an IC chip on the substrate, wherein a structure with which it is possible to maximally avoid an increase in the number of wiring layers on the substrate is obtained by devising the pad arrangement in an IC pad-array region.
A embodiment of the present invention provides a pad-array structure on a substrate for mounting an IC chip on the substrate. The present invention is characterized in that: a plurality of ground pads arrayed equidistantly in a first row, and a plurality of signal pads arrayed equidistantly in a second row on the inside of and parallel to the first row, are provided on a first circumferential edge in the pad-array region; each of the signal pads passes between two adjacent ground pads in the first row and is connected to an external circuit on the substrate; and electrical signals are input to and output from the external circuit.
摘要翻译：上的基片A垫阵列布置结构，用于安装在基底上的IC芯片，worin的结构与它能够最大限度地避免增加布线层的数目在基板是通过在IC制定的焊盘布置在获得垫阵列区域。本发明的实施例提供用于在衬底上的IC芯片的安装在基片的焊盘阵列结构。本发明的特征在于：被设置在第一周向边缘的在第一行等距离排列接地用焊盘多个，并且在第二行等距排列在内侧并平行于第一行的信号焊盘复数，在焊盘阵列区域; 各信号焊盘的第一行中的两个相邻接地焊盘之间穿过，并在在基片上的外部电路连接到; 和电气信号被输入到和输出从外部电路。

6. 发明公开

EP2981417A1 LAYERED STRUCTURE WITH CONDUCTIVE POLYMER FOR RECOGNITION OF MANIPULATION AND PROCESS FOR THE PRODUCTION THEREOF 有权
标题翻译：与导电聚合物进行操纵的检测和方法及其制造层结构
公开(公告)号：EP2981417A1
公开(公告)日：2016-02-10
申请号：EP14714942.1
申请日：2014-03-31
申请人： Heraeus Deutschland GmbH & Co. KG
发明人： PUTTKAMMER, Frank
IPC分类号： B42D15/00 , B42D25/00
CPC分类号： G06K19/07345 , B32B27/00 , B41M1/10 , B41M1/12 , B41M3/006 , B41M3/14 , B42D25/00 , B42D25/29 , B42D25/373 , B42D2033/10 , B42D2033/22 , B42D2033/30 , B42D2033/32 , B42D2033/46 , G06K7/10118 , G06Q30/0185 , H05K1/0268 , H05K1/0275 , H05K1/0293 , H05K1/0298 , H05K1/0333 , H05K1/0386 , H05K1/095 , H05K1/115 , H05K3/0064 , H05K3/4053 , H05K3/4644 , H05K3/4688 , H05K2201/0329 , H05K2201/0391
摘要： The invention relates to a layered structure (10) comprising the following layers: a) a first substrate layer (2), wherein the first substrate layer (2) has a first surface (4) and a second surface (6) and is configured as a dielectric; b) a first electrically conductive layer (8) which overlaps at least in part the first substrate layer (2) at least on the first surface (4) of the first substrate layer (2), wherein the first electrically conductive layer (8) comprises an electrically conductive polymer, wherein the first electrically conductive layer (8) has at least one first part region (18) and at least one further part region (20), wherein the at least one first part region (18) has a higher bonding strength to the substrate layer (2) than to the at least one further part region (20).
摘要翻译：本发明涉及一种层状结构（10）包括以下层：a）第一基片层（2），worin第一基板层（2）具有第一表面（4）和第二表面（6），并且被配置作为电介质; b）第一导电层（8），该部分至少重叠第一基板层（2）至少第一表面（4）上的第一基板层（2），worin第一导电层（8）导电性聚合物的步骤包括，worin第一导电层（8）具有至少一个第一部分区域（18）和至少一个另外的部分区域（20），其中，所述至少一个第一部分区域（18）具有更高的接合强度于基板层（2），而不是所述至少一个部分进一步区域（20）。

7. 发明公开

EP2813132A1 MULTILAYER ELECTRONICS ASSEMBLY AND METHOD FOR EMBEDDING ELECTRICAL CIRCUIT COMPONENTS WITHIN A THREE DIMENSIONAL MODULE 有权
标题翻译：多层电子系统和方法嵌入电路元件在三维模块
公开(公告)号：EP2813132A1
公开(公告)日：2014-12-17
申请号：EP13746884.9
申请日：2013-02-06
申请人： Crane Electronics, Inc.
发明人： PARKER, Ernest, Clyde , LAURIELLO, Philip, Joseph
IPC分类号： H05K3/46 , H05K1/18 , H01L23/12
CPC分类号： H05K1/186 , H01L23/49827 , H01L2224/24 , H01L2224/29239 , H01L2224/32225 , H01L2224/33181 , H01L2224/8384 , H01L2924/13091 , H05K3/4046 , H05K3/4632 , H05K3/4638 , H05K3/4688 , H05K2201/015 , H05K2201/10166 , H05K2203/068 , H05K2203/1178 , H05K2203/167 , H01L2924/00
摘要： A multilayer electronics assembly and associated method of manufacture are provided. The multilayer electronics assembly includes a plurality of stacked substrate layers. Each of the substrate layers is fusion bonded to at least an adjacent one of the plurality of substrate layers. A first discrete electrical circuit component is bonded to a first layer of the plurality of layers. A bonding material is interposed between the discrete electrical circuit component and the first layer. The bonding material has a reflow temperature at which the bonding material becomes flowable that is higher than a fusion bonding temperature of the substrate layers.

8. 发明公开

EP2680111A4 SUBSTRATE WITH TRANSPARENT ELECTRODE, METHOD FOR PRODUCING SAME, AND TOUCH PANEL 审中-公开
标题翻译：带有透明电极，用于生产和触摸屏衬底
公开(公告)号：EP2680111A4
公开(公告)日：2014-02-26
申请号：EP11875385
申请日：2011-11-11
申请人： KANEKA CORP
发明人： UEDA HIROAKI , FUJIMOTO TAKAHISA , KONDO KOZO , YAMAMOTO KENJI
IPC分类号： G06F3/041 , B32B7/02 , B32B9/00 , G02B1/11 , G06F3/044
CPC分类号： H05K1/0306 , C23C14/08 , G02B1/116 , G06F3/041 , G06F3/044 , G06F2203/04103 , H05K1/0274 , H05K3/4688
摘要： The substrate (100) with a transparent electrode includes a first dielectric material layer (21) mainly composed of SiO x , a second dielectric material layer (22) mainly composed of a metal oxide, a third dielectric material layer (23) mainly composed of SiO y , and a transparent electrode layer (4), in this order on at least one of the surfaces of a transparent film substrate (1). The transparent electrode layer (4) is patterned to have an electrode layer-formed part (4a) and an electrode layer non-formed part (4b). The transparent electrode layer (4) is a layer mainly composed of an indium-tin composite oxide and having a thickness of 20 nm to 35 nm. The refractive index n 1 of the first dielectric material layer, the refractive index n 2 of the second dielectric material layer, and the refractive index n 3 of the third dielectric material layer satisfy the relationship of n 3

10. 发明公开

EP2609796A1 MEHREBENENLEITERPLATTE FÜR HOCHFREQUENZ-ANWENDUNGEN 有权转让
标题翻译： MEHREBENENLEITERPLATTEFÜRHOCHFREQUENZ-ANWENDUNGEN
公开(公告)号：EP2609796A1
公开(公告)日：2013-07-03
申请号：EP11802260.7
申请日：2011-08-17
申请人： Conti Temic Microelectronic GmbH
发明人： MÖLLER, Ulrich , SCHÄFER, Maik
IPC分类号： H05K1/16 , H05K1/02 , H05K3/46
CPC分类号： H05K1/162 , H05K1/0231 , H05K1/0234 , H05K1/0251 , H05K3/4688
摘要： The invention relates to a multi-level circuit board for high-frequency applications, comprising at least one first substrate (PCB1) made of a first material suitable for high frequency and at least one second substrate (PCB2,3) made of a second material having higher dielectric losses than the first material. At least one signal line structure (S1, C1) is provided on the first substrate (PCB1), at least one ground layer (M2) connected to electric ground potential is provided on a side of at least one second substrate (PCB2, PCB3), and electrical vias (V) through the substrates (PCB1,2,3) are provided. A capacitance for discharging high-frequency power to ground potential is formed by the at least one second substrate (PCB2, PCB3) to the ground layer (M2, M4), preferably by two substrates made of the second material to a metallization surface lying therebetween, in that a metallization surface (C3) having a size corresponding to the desired capacitance is formed on the side of the second substrate (PCB2.4) opposite the ground layer (M2, M4) and the metallization surface (C3) is connected to the signal line structure (C1) by means of a via (V(C1-C3)).
摘要翻译：本发明涉及一种用于高频应用的多电平电路板，其具有由适合于高频的第一材料制成的至少一个第一载体衬底（PCB1）和至少一个第二载体衬底（PCB2,3），其由第二材料，其第二材料具有比第一材料更高的介电损耗。在第一载体基板（PCB1）上提供至少一个信号线结构（S1，C1），并且在至少一个第二载体基板（PCB2）的一侧上设置至少一个连接到地电位的接地层（M2），PCB3）和延伸穿过载体基板（PCB1,2,3）的电气通孔（V）。通过至少一个第二载体衬底（PCB2，PCB3）朝向接地层（M2，M4）形成用于去除高频电力到接地电位的电容，优选地通过由第二材料制成的两个载体衬底朝向金属化表面其中具有对应于期望电容的尺寸的金属化表面（C3）形成在与接地层（M2，M4）和金属化表面（M2）相对的第二载体衬底（PCB2,4）的一侧上 C3）通过通孔（V（C1-C3））连接到信号线结构（C1）。

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