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1. 发明授权

EP1665340B1 FORMATION OF A SILICON GERMANIUM-ON-INSULATOR STRUCTURE BY OXIDATION OF A BURIED POROUS SILICON LAYER 有权
标题翻译：形成硅 - 锗ON-绝缘体结构BY氧化掩埋多孔硅层的
公开(公告)号：EP1665340B1
公开(公告)日：2007-08-01
申请号：EP04809708.3
申请日：2004-09-10
申请人： International Business Machines Corporation
发明人： BEDELL, Stephen, W. , CHOE, Kwang Su , FOGEL, Keith, F. , SADANA, Devendra, K.
IPC分类号： H01L21/762
CPC分类号： H01L21/76227 , C22F1/10 , H01L21/02378 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02667 , H01L21/76245 , H01L29/78603
摘要： A simple and direct method of forming a SiGe-on-insulator that relies on the oxidation of a porous silicon layer (or region) that is created beneath a Ge-containing layer is provided. The method includes the steps of providing a structure comprising a Si-containing substrate having a hole-rich region formed therein and a Ge-containing layer atop the Si-containing substrate; converting the hole-rich region into a porous region; and annealing the structure including the porous region to provide a substantially relaxed SiGe-on-insulator material.

2. 发明公开

EP1716593A1 VERF LLUNG VON ISOLATIONSGR BEN UNTER NUTZUNG VON CMOS- STANDARDPROZESSEN ZUR REALISIERUNG DIELEKTRISCH ISOLIERTER GEBIETE AUF EINER SOI SCHEIBE 审中-公开
标题翻译：灌装ISOLATIONSGR BEN在使用标准CMOS资源的供应流程，实现介质隔离区上的磁盘SOI
公开(公告)号：EP1716593A1
公开(公告)日：2006-11-02
申请号：EP05714947.8
申请日：2005-02-05
申请人： X-FAB Semiconductor Foundries AG
发明人： FREYWALD, Karlheinz
IPC分类号： H01L21/762 , H01L21/764
CPC分类号： H01L21/76224 , H01L21/76227 , H01L21/764
摘要： The method is used for dielectrical separation of areas having different potentials from component structures, whereby a hollow cavity (11), which is created by filling the insulation trench therein with an insulator in order to create a hermetically tight closure of the hollow cavity below the level of the semiconductor disk surface (4b,3a,3b), is formed and planarization is carried out on the filling of the trench following on from the hollow cavity (11).A series of CMOS method steps are carried out after the trench has been produced. SiO2 layers (7, 7', 7a) which become thicker in the direction of the upper edges of the trench are produced according to a first CVD method; the SiO2-layer sections are subsequently fully removed from the upper area of the trench until a defined depth is obtained, in order to determine a later closure point (12) of the hollow cavity (11). The hollow cavity (11) is then closed. The trench is filled by deposing a second SiO2-layer (10) with the aid of a low-pressure CVD method until a tip of an indention (13) in the second oxide layer comes to rest above the level of the surface (4b, 3a, 3b). Later planarization prevents the hollow cavity from being opened.

3. 发明授权

EP0237684B1 Production of integrated-circuit devices incorporating a diffusion stop for oxygen 失效
标题翻译：一种用于制造使用层集成电路的对氧的扩散方法
公开(公告)号：EP0237684B1
公开(公告)日：2000-09-06
申请号：EP86310234.9
申请日：1986-12-31
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Yen, Yung-Chau
IPC分类号： H01L21/314 , H01L21/32 , H01L21/76
CPC分类号： H01L21/76897 , H01L21/28273 , H01L21/3144 , H01L21/32 , H01L21/321 , H01L21/76227 , H01L29/66181

4. 发明公开

EP0507596A3 A method for forming planarized shallow trench isolation in an integrated circuit and a structure formed thereby 失效
标题翻译：一种在集成电路中形成平面化的浅层分离的方法及其形成的结构
公开(公告)号：EP0507596A3
公开(公告)日：1995-09-06
申请号：EP92302941.7
申请日：1992-04-03
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Liou, Fu-Tai , Chen, Fusen E.
IPC分类号： H01L21/76
CPC分类号： H01L21/76227
摘要： A method for forming isolation structures in an integrated circuit, and the structures so formed, are disclosed. After definition of active regions of the surface is accomplished by provision of masking layers, recesses are etched into the exposed locations, to a depth on the order of the final thickness of the insulating isolation structure. Sidewall spacers of silicon dioxide, or another insulating amorphous material, are disposed along the sidewalls of the recesses, with silicon at the bottom of the recesses exposed. Selective epitaxial growth of silicon then forms a layer of silicon within the recesses, preferably to a thickness on the order of half of the depth of the recess. The epitaxial silicon is thermally oxidized, filling the recesses with thermal silicon dioxide, having a top surface which is substantially coplanar with the active regions of the surface. According to an alternative embodiment, the formation of the sidewall spacers may be done in such a manner that narrower recesses remain filled with the material of the sidewall spacers.

5. 发明授权

EP1978548B1 PROCESS FOR PRODUCING SILICEOUS FILM 有权转让
标题翻译：用于生产硅石基薄膜
公开(公告)号：EP1978548B1
公开(公告)日：2013-09-11
申请号：EP07713624.0
申请日：2007-01-17
申请人： AZ Electronic Materials (Japan) K.K. , AZ Electronic Materials USA Corp.
发明人： ISHIKAWA, Tomonori , NAKAGUMA, Teruno
IPC分类号： H01L21/316 , H01L21/762 , H01L21/312 , C23C16/56
CPC分类号： H01L21/76227 , C23C16/56 , H01L21/02164 , H01L21/02222 , H01L21/02282 , H01L21/02304 , H01L21/02337 , H01L21/3125 , H01L21/316

6. 发明公开

EP1897132A1 METHOD FOR FABRICATING SHALLOW TRENCHES 审中-公开
标题翻译：的生产方法浅沟槽
公开(公告)号：EP1897132A1
公开(公告)日：2008-03-12
申请号：EP05789067.5
申请日：2005-06-28
申请人： The Regents of the University of California
发明人： XIE, Ya-Hong
IPC分类号： H01L21/76
CPC分类号： H01L21/76227 , H01L21/76237 , H01L21/76245
摘要： A method of forming shallow trenches used, for example, in shallow trench isolation includes the steps of providing a p-type silicon substrate, forming a layer in the p-type silicon substrate, wherein the layer includes p-type silicon interposed between n-type silicon. The p-type silicon layer interposed between the n-type silicon is then subject to an anodization process to form porous silicon. The porous silicon regions are then oxidized. The porosity of the silicon layer may be controlled to create an isolation region that is either substantially flush with, above, or below an upper surface of the n-type top layer. For example, by adjusting the anodization time, a retrograde cross-sectional profile of the shallow trench can be obtained that leads to improved isolation between adjacent devices.

7. 发明公开

EP1641958A2 METHODS OF FORMING A PHOSPHORUS DOPED SILICON DIOXIDE LAYER 有权
标题翻译：法形成的荧光体掺杂的二氧化硅的
公开(公告)号：EP1641958A2
公开(公告)日：2006-04-05
申请号：EP04777377.5
申请日：2004-06-30
申请人： MICRON TECHNOLOGY, INC.
发明人： VAARTSTRA, Brian, A.
IPC分类号： C23C16/40
CPC分类号： C23C16/45531 , C23C16/045 , C23C16/401 , C23C16/402 , H01L21/02129 , H01L21/02216 , H01L21/02271 , H01L21/0228 , H01L21/31625 , H01L21/76227
摘要： This invention includes methods of forming a phosphorus doped silicon dioxide comprising layers, and methods of forming trench isolation in the fabrication of integrated circuitry. In one implementation, a method of forming a phosphorus doped silicon dioxide comprising layer includes positioning a substrate within a deposition chamber. First and second vapor phase reactants are introduced in alternate and temporally separated pulses to the substrate within the chamber in a plurality of deposition cycles under conditions effective to deposit a phosphorus doped silicon dioxide comprising layer on the substrate. One of the first and second vapor phase reactants is PO(OR)3 where R is hydrocarbyl, and an other of the first and second vapor phase reactants is Si(OR)3OH where R is hydrocarbyl.

8. 发明授权

EP0054659B1 Method for forming dielectric isolation regions in a monocrystalline silicon substrate 失效
标题翻译：在单晶硅基板中形成介电分离区的方法
公开(公告)号：EP0054659B1
公开(公告)日：1984-07-18
申请号：EP81108546.3
申请日：1981-10-20
申请人： International Business Machines Corporation
发明人： Riseman, Jacob
IPC分类号： H01L21/76
CPC分类号： H01L21/76227

9. 发明公开

EP0035690A2 Semiconductor device using component insulation and method of manufacturing the same 失效
标题翻译：一种半导体器件，包括它们的制备绝缘组件和方法。
公开(公告)号：EP0035690A2
公开(公告)日：1981-09-16
申请号：EP81101328.3
申请日：1981-02-24
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Nozawa, Hiroshi
IPC分类号： H01L21/76 , H01L21/31
CPC分类号： H01L21/76227 , H01L21/033 , H01L21/32105
摘要： A method for element isolation utilizing insulating materials (6) in a semiconductor substrate (1) is proposed. This method is characterized in that an oxidizable material layer (3) of polycrystalline silicon or the like is formed, the oxidizable material layer (3) disposed at the element-isolationforming regions is oxidized using an oxidation mask (4), the oxidation mask (4) is removed and, if necessary at least part of the unoxidized oxidizable material (3) below the mask (4) is removed. Predetermined processes such as oxidation and diffusion are performed thereafter to form semiconductor elements such as MOS transistors and bipolar transistors with high packaging density and reliability.
摘要翻译：一种用于元件隔离绝缘利用在半导体衬底（1）材料（6）方法被提议。这种方法是在多晶硅等的可氧化材料层（3）那样被形成，可氧化材料层（3）设置在所述元件isolatingforming区域特点是使用氧化掩模（4），所述氧化掩模（氧化 4）被移除，并且如果掩模（4）所示的未氧化的可氧化材料（3）的必要的至少一部分被去除。预定的处理：诸如氧化和扩散是其后进行，以形成半导体元件：如MOS晶体管和具有高封装密度和可靠性双极晶体管。

10. 发明公开

EP1897132A4 METHOD FOR FABRICATING SHALLOW TRENCHES 审中-公开
标题翻译：的生产方法浅沟槽
公开(公告)号：EP1897132A4
公开(公告)日：2014-11-26
申请号：EP05789067
申请日：2005-06-28
申请人： UNIV CALIFORNIA
发明人： XIE YA-HONG
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76227 , H01L21/76237 , H01L21/76245

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