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1. 发明授权

EP0242506B1 Sidewall spacers for cmos circuits stress relief/isolation and method for making 失效
标题翻译：用于CMOS电路的紧固件间隔件应力消除/隔离和制造方法
公开(公告)号：EP0242506B1
公开(公告)日：1993-03-24
申请号：EP87100962.7
申请日：1987-01-23
申请人： International Business Machines Corporation
发明人： Dally, Anthony John , Ogura, Seiki , Riseman, Jacob , Rovedo, Nivo
IPC分类号： H01L29/78 , H01L21/225 , H01L21/76
CPC分类号： H01L21/76224

2. 发明公开

EP0242506A2 Sidewall spacers for cmos circuits stress relief/isolation and method for making 失效
标题翻译：侧壁间隔物用于接收电压和CMOS电路的隔离，以及制造过程。
公开(公告)号：EP0242506A2
公开(公告)日：1987-10-28
申请号：EP87100962.7
申请日：1987-01-23
申请人： International Business Machines Corporation
发明人： Dally, Anthony John , Ogura, Seiki , Riseman, Jacob , Rovedo, Nivo
IPC分类号： H01L29/78 , H01L21/225 , H01L21/76
CPC分类号： H01L21/76224
摘要： A method for forming fully recessed (planar) isolation regions (22,24) on a semiconductor for the manufacture of CMOS integrated circuits, and the resulting semiconductor structure, comprising in a P doped silicon substrate (10) with mesas (22,24) formed therein, forming low viscosity sidewall spacers (30) of borosilicate glass in contact with the sidewalls of those mesas designated to have N-channel devices formed therein; then filling the trenches (11,12) in the substrate adjacent to the mesas with TEOS 32); and heating the structure until the boron in the sidewall spacers diffuses into the sidewalls of the designated mesas to form channel stops (40,42). These sidewall spacers reduce the occurrence of cracks in the TEOS by relieving internal mechanical stress therein and permit the formation of channel stops via diffusion, thereby permitting mesa walls to be substantially vertical.
摘要翻译：一种用于形成在半导体完全凹入（平面）的隔离区（22,24），用于CMOS的制造方法的集成电路，产生的半导体结构，在P掺杂硅衬底与台面，其包含（10）（22,24）形成于其中，形成与指定为具有N沟道器件形成于其中台面的那些侧壁接触的硼硅酸盐玻璃的低粘度侧壁间隔物（30）; 然后填充在邻近与TEOS 32）的台面的衬底沟槽（11,12）; 并加热该结构，直到在侧壁间隔件中的硼扩散进入指定台面以形成通道的侧壁停止（40,42）。这些侧壁间隔物通过在其中缓和内部机械应力减小TEOS裂纹的产生，并允许信道的形成通过扩散停止，由此允许台面的壁是基本垂直的。

3. 发明公开

EP0100897A3 Method for contacting a pn junction region and resulting structure 失效
标题翻译：接触PN结区域和结构结构的方法
公开(公告)号：EP0100897A3
公开(公告)日：1985-08-07
申请号：EP83106872
申请日：1983-07-13
申请人： International Business Machines Corporation
发明人： Bhatia, Harsaran Singh , Bhatia, Satyapal Singh , Riseman, Jacob , Valsamakis, Emmanuel A.
IPC分类号： H01L21/60 , H01L23/48
CPC分类号： H01L29/735 , H01L21/2257 , H01L21/28525 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： The method and resulting structure for making contact to a narrow width PN junction region in any desired semiconductor body utilizes a substantially vertical conformal conductive layer (26) formed over the desired PN junction region (30, 32). The body is heated to a suitable temperature to cause a dopant to diffuse from the vertical conductive layer (26) into the semiconductor body to form the narrow width PN junction region (30, 32). A substantially horizontal conductive layer (22) makes contact to the substantially vertical layer (26) so as to have the horizontal conductive layer (22) in electrical contact to the PN junction region (30, 32). Electrical contacts (34, 36) can be established to the horizontal conductive layer at any convenient location. A lateral PNP transistor is one type of device that can be made.

4. 发明公开

EP0083088A3 Method of producing field effect transistors having very short channel length 失效
标题翻译：生产具有非常短的通道长度的场效应晶体管的方法
公开(公告)号：EP0083088A3
公开(公告)日：1985-01-23
申请号：EP82111969
申请日：1982-12-27
申请人： International Business Machines Corporation
发明人： Riseman, Jacob , Tsang, Paul Ja-Min
IPC分类号： H01L21/00 , H01L29/68 , H01L29/78
CPC分类号： H01L29/66659 , H01L21/0337 , H01L21/2815 , H01L29/78 , Y10S438/942 , Y10S438/947
摘要： Methods for producing field effect transistor devices having very short channel length are described. A surface isolation pattern (12) in a semiconductor substrate (10) isolates device regions of the semiconductor within the substrate from one another. An insulating layer (16) destined to be the gate dielectric layer of the field effect transistor devices is formed over the isolation pattern (12). Then a first polycrystalline silicon layer (20) is formed thereover. A masking layer (22) such as silicon dioxide is then formed upon the first polycrystalline layer. The multilayer structure is etched to result in a patterned first polycrystalline silicon layer having substantially vertical sidewalls. A sub- micrometer thickness conductive layer (26') is formed on these vertical sidewalls. The patterned layer is then removed which leaves the pattern of sub-micrometer thickness conductive sidewall layer (26') portions of which extend across certain of the device regions. The sidewall conductive layer is utilized as the gate electrode of the field effect transistor devices.

5. 发明公开

EP0110211A2 Bipolar transistor integrated circuit and method for manufacturing 失效
标题翻译：一种集成电路，包括它们的制备双极晶体管和方法。
公开(公告)号：EP0110211A2
公开(公告)日：1984-06-13
申请号：EP83111220.6
申请日：1983-11-10
申请人： International Business Machines Corporation
发明人： Riseman, Jacob
IPC分类号： H01L21/60 , H01L21/285 , H01L29/60 , H01L29/62
CPC分类号： H01L29/456 , H01L21/28518 , H01L21/28537 , H01L29/42304
摘要： A metal silicide contact to silicon devices which has broad application to almost all of the variety of silicon semiconductor devices is described. This contact with a substantial side component has particular advantage as the base contact for a bipolar transistor. Subsequent to the formation of the metal silicide contact layer (40) the surface of said metal silicide is thermally oxidized to form a silicon dioxide layer (42) thereover. This causes the silicide contact structure to sink into the silicon body to a depth at least as great as the emitter-base junction depth. The metal silicide contact (40) itself is contacted by contact elements (52) reaching from the surface through said silicon dioxide layer (42).

6. 发明公开

EP0100897A2 Method for contacting a pn junction region 失效
标题翻译： Verfahren zum Kontaktieren eines pn-Übergangsgebietes。
公开(公告)号：EP0100897A2
公开(公告)日：1984-02-22
申请号：EP83106872.1
申请日：1983-07-13
申请人： International Business Machines Corporation
发明人： Bhatia, Harsaran Singh , Bhatia, Satyapal Singh , Riseman, Jacob , Valsamakis, Emmanuel A.
IPC分类号： H01L21/60 , H01L23/48
CPC分类号： H01L29/735 , H01L21/2257 , H01L21/28525 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： The method and resulting structure for making contact to a narrow width PN junction region in any desired semiconductor body utilizes a substantially vertical conformal conductive layer (26) formed over the desired PN junction region (30, 32). The body is heated to a suitable temperature to cause a dopant to diffuse from the vertical conductive layer (26) into the semiconductor body to form the narrow width PN junction region (30, 32). A substantially horizontal conductive layer (22) makes contact to the substantially vertical layer (26) so as to have the horizontal conductive layer (22) in electrical contact to the PN junction region (30, 32). Electrical contacts (34, 36) can be established to the horizontal conductive layer at any convenient location. A lateral PNP transistor is one type of device that can be made.
摘要翻译：用于与任何所需半导体主体中的窄宽度PN结区域接触的方法和所得结构利用形成在期望的PN结区域（30,32）上的基本垂直的保形导电层（26）。将本体加热到合适的温度，使掺杂剂从垂直导电层（26）扩散到半导体本体中，形成窄宽度的PN结区域（30,32）。基本上水平的导电层（22）与基本上垂直的层（26）接触，以使水平导电层（22）与PN结区域（30,32）电接触。电触点（34,36）可以在任何方便的位置建立到水平导电层。横向PNP晶体管是可以制造的一种类型的器件。

7. 发明公开

EP0071204A2 Method for forming recessed dielectric isolation 失效
标题翻译：一种用于凹陷介电隔离的制备方法。
公开(公告)号：EP0071204A2
公开(公告)日：1983-02-09
申请号：EP82106655.2
申请日：1982-07-23
申请人： International Business Machines Corporation
发明人： Pliskin, William Aaron , Riseman, Jacob , Shepard, Joseph Francis
IPC分类号： H01L21/76 , H01L21/316
CPC分类号： H01L21/02145 , H01L21/02266 , H01L21/02271 , H01L21/02282 , H01L21/02304 , H01L21/3105 , H01L21/31604 , H01L21/31608 , H01L21/76232 , H01L21/76237
摘要： A method is described for forming the recessed dielectric isolation in a silicon substrate. This method involves first forming trenches (16) which are less than 1 micron in depth in areas of one principal surface of the silicon substrate where isolation is desired. Where, for example, an NPN bipolar transistor structure is planned to be formed it is usually necessary to have a P+ region (6) underneath the recessed dielectric isolation to allow full isolation between the various bipolar transistor devices. A PNP transistor uses an N+ region underneath the isolation. Where a field effect transistor is planned a channel stop (30) can be substituted for the P+ region. Under the circumstance of bipolar devices, the P+ region (6) is formed in the substrate (2) prior to the deposition of an epitaxial layer (8) thereover. The trench formation is caused to be formed through the epitaxial layer and into the P+ regions therein. The surface of the trenches (16) are then oxidized in an oxidizing ambient to form a silicon dioxide layer (18) thereon. A glass (20) is deposited over this principal surface. The glass used has a thermal coefficient of expansion that approximates that of silicon and has a softening temperature of less than 1200°C. The structure is then heated to a temperature that allows the flow of the deposited glass on the surface so as to fill the trenches. The glass on the principal surface above the trench can be removed by a reactive ion etching method. Alternatively and preferably, the glass is removed from areas other than the immediate area of the trench by lithography and etching techniques followed by a second heating of the structure to cause the glass flow to result in surface planarization.

8. 发明公开

EP0010633A1 Verfahren zur Herstellung sehr schmaler Dosierungsgebiete in einem Halbleiterkörper sowie Verwendung dieses Verfahrens bei der Erzeugung von voneinander isolierten Halbleiterkörperbereichen, Bipolar-Halbleiteranordnungen, integrieten Injektionslogikschaltungen und doppelt diffundierten FET-Halbleiteranordnungen 失效
标题翻译：一种用于在半导体本体中产生非常窄的剂量区以及使用该方法用于产生所述主体的相互绝缘的半导体区，双极型半导体器件，integrieten注入逻辑电路，和双扩散FET的半导体器件的过程。
公开(公告)号：EP0010633A1
公开(公告)日：1980-05-14
申请号：EP79103770.8
申请日：1979-10-03
申请人： International Business Machines Corporation
发明人： Ho, Irving Tze , Riseman, Jacob
IPC分类号： H01L21/225 , H01L21/263
CPC分类号： H01L29/66545 , H01L21/0337 , H01L21/2255 , H01L21/2257 , H01L29/66272 , H01L29/7833 , Y10S148/131
摘要： Zur Herstellung sehr schmaler Dotierungsgebiete in einem Halbleiterkörper unter Ausnutzung einer Diffusion der jeweiligen Dotierstoffe aus zugehörigen Quellschichten wird ein Verfahren angegeben, mit dem diese Quellschichtbereiche kleiner als mit üblichen Lithographie- und Ätzverfahren möglich ausgelegt werden können. Dazu wird zunächst durch Aufbringen und Formen von Isolierschichtbereichen (50) auf einem Halbleiterkörper eine im wesentlichen horizontale und vertikale Oberflächenbereiche aufweisende Oberfläche gebildet. Auf die so beschaffene Oberfläche wird anschließend eine in der gewünschten Dotierungsart dotierte Quellschicht (52) aufgebracht. Unter Ausnutzung der unterschiedlichen Ätzrate in vertikaler und horizontaler Richtung wird mittels reaktivem lonenätzen die Quellschicht von den horizontalen Oberflächenbereichen abgetragen. Es verbleiben danach lediglich sehr schmale Quellschichtbereiche (52) auf den vertikal gerichteten Oberflächen. Die Bildung der letzlich sehr schmalen Dotierungsgebiete (56, 58) erfolgt schließlich durch eine an sich bekannte Wärmebehandlung aus den sehr schmalen Quellschichtbereichen (52). Ihre Breite läßt sich mit der jeweils gewählten Schichtdicke der Quellschicht (52) variieren. Es werden Anwendungen des Verfahrens für den Aufbau von FET-und Bipolar-Halbleiteranordnungen behandelt.
摘要翻译：用于通过利用相关联的源层的各自的掺杂剂的扩散的生产在半导体本体中很窄的掺杂区提供由该层的源极区可制成比用常规光刻和可能的蚀刻技术更小的方法。用于此目的的含表面的基本水平和垂直的表面区域首先被Isolierschichtbereichen（50）的在半导体本体施加和形式形成。然后在期望的掺杂型源极层（52）掺杂的被施加到这样构成的表面。利用在垂直方向和水平方向上的不同蚀刻速率的，源极层从水平表面区域通过反应离子蚀刻的手段除去。此后只留下很窄的源层区域（52）垂直定向的表面。的最终非常窄的掺杂区（56，58）的形成是从非常窄的源层区域（52）最后进行利用公知的热处理。其宽度可与源极层（52）的所选择的层厚度而变化。它涵盖用于构建，FET和双极型半导体器件的方法的应用。

9. 发明授权

EP0071205B1 Method for forming high density dielectric isolation 失效
标题翻译：形成高密度电介质隔离的方法
公开(公告)号：EP0071205B1
公开(公告)日：1989-10-18
申请号：EP82106656.0
申请日：1982-07-23
申请人： International Business Machines Corporation
发明人： Chu, Wei-Kan , Pliskin, William Aaron , Riseman, Jacob
IPC分类号： H01L21/76 , H01L21/316
CPC分类号： H01L21/02126 , H01L21/02282 , H01L21/02304 , H01L21/31051 , H01L21/31604 , H01L21/31608 , H01L21/76224 , Y10S438/951

10. 发明授权

EP0113405B1 Method for making semiconductor resistors 失效
标题翻译：制造半导体电阻的方法
公开(公告)号：EP0113405B1
公开(公告)日：1989-09-20
申请号：EP83110966.5
申请日：1983-11-03
申请人： International Business Machines Corporation
发明人： Bhatia, Harsaran Singh , Riseman, Jacob
IPC分类号： H01L21/00 , H01L21/225 , H01L29/86
CPC分类号： H01L28/20 , H01L21/0337 , H01L21/2257

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