专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

EP3123514A4 STRAIN COMPENSATION IN TRANSISTORS 有权
公开(公告)号：EP3123514A4
公开(公告)日：2017-11-22
申请号：EP14886927
申请日：2014-03-28
申请人： INTEL CORP
发明人： LE VAN H , CHU-KUNG BENJAMIN , KAVALIEROS JACK T , PILLARISETTY RAVI , RACHMADY WILLY , KENNEL HAROLD W
IPC分类号： H01L29/10 , H01L21/02 , H01L21/20 , H01L21/336 , H01L29/06 , H01L29/423 , H01L29/775 , H01L29/78
CPC分类号： H01L29/78696 , B82Y10/00 , B82Y40/00 , H01L21/02381 , H01L21/0245 , H01L21/02461 , H01L21/02463 , H01L21/02466 , H01L21/02505 , H01L21/02532 , H01L21/02543 , H01L21/02546 , H01L29/0673 , H01L29/1054 , H01L29/1079 , H01L29/155 , H01L29/165 , H01L29/42364 , H01L29/42392 , H01L29/66439 , H01L29/66742 , H01L29/66772 , H01L29/775 , H01L29/7849 , H01L29/78603 , H01L29/78618 , H01L29/78684
摘要： An embodiment includes a device comprising: a first epitaxial layer, coupled to a substrate, having a first lattice constant; a second epitaxial layer, on the first layer, having a second lattice constant; a third epitaxial layer, contacting an upper surface of the second layer, having a third lattice constant unequal to the second lattice constant; and an epitaxial device layer, on the third layer, including a channel region; wherein (a) the first layer is relaxed and includes defects, (b) the second layer is compressive strained and the third layer is tensile strained, and (c) the first, second, third, and device layers are all included in a trench. Other embodiments are described herein.

2. 发明公开

EP3036770A4 HIGH RESISTANCE LAYER FOR III-V CHANNEL DEPOSITED ON GROUP IV SUBSTRATES FOR MOS TRANSISTORS 有权
标题翻译： HOCHRESISTENTE SCHICHTFÜREINEN AUF GRUPPE-IV-SUBSTRATEN ABGELAGERTEN III-V-KANALFÜRMOS-TRANSISTOREN
公开(公告)号：EP3036770A4
公开(公告)日：2017-03-22
申请号：EP13891735
申请日：2013-08-23
申请人： INTEL CORP
发明人： GLASS GLENN A , MURTHY ANAND S
IPC分类号： H01L29/78 , H01L21/02 , H01L21/336 , H01L29/267
CPC分类号： H01L29/205 , H01L21/02241 , H01L21/02247 , H01L21/02373 , H01L21/02461 , H01L21/02463 , H01L21/02466 , H01L21/02546 , H01L21/02549 , H01L21/0262 , H01L21/30604 , H01L21/30612 , H01L21/7605 , H01L21/76224 , H01L21/76232 , H01L21/76264 , H01L27/0255 , H01L29/0653 , H01L29/0673 , H01L29/1033 , H01L29/1054 , H01L29/1079 , H01L29/1083 , H01L29/165 , H01L29/267 , H01L29/66522 , H01L29/66795 , H01L29/78 , H01L29/7848 , H01L29/785

3. 发明公开

EP3133046A1 AL-POOR BARRIER FOR INGAAS SEMICONDUCTOR STRUCTURE 审中-公开
标题翻译： AL-POOR-BARRIEREFÜRINGAAS-HALBLEITERSTRUKTUR
公开(公告)号：EP3133046A1
公开(公告)日：2017-02-22
申请号：EP16178831.0
申请日：2016-07-11
申请人： IMEC VZW
发明人： KUNERT, Bernadette , LANGER, Robert
IPC分类号： B82Y10/00 , H01L29/66 , H01L29/775 , H01L29/06 , H01L29/10 , H01L29/205
CPC分类号： H01L29/0673 , B82Y10/00 , H01L21/02381 , H01L21/02461 , H01L21/02463 , H01L21/02466 , H01L21/02502 , H01L21/02546 , H01L29/1033 , H01L29/1079 , H01L29/205 , H01L29/66469 , H01L29/775
摘要： The present invention relates to a semiconductor structure comprising:
a. a Si monocrystalline substrate (4),
b. a III-V structure (1) abutting said Si monocrystalline substrate (4), and
c. an In a Ga b As structure (3) overlaying said III-V structure (1), wherein a is from 0.40 to 1, b is from 0.30 to 0, and a + b is 1.00,
wherein said III-V structure (1) comprises a buffer (11) and a barrier portion (12) and has a top surface facing away from the Si monocrystalline substrate (4), said top surface having the chemical composition Ga g X x P p Sb s Z z , inlcuding for example GaPSb, GaBPSb, GaInPSb and GaInPSbAs.
摘要翻译：本发明涉及一种半导体结构，包括：a。 Si单晶衬底（4），b。邻接所述Si单晶衬底（4）的III-V结构（1），以及c。（a）的Ga b As结构（3），其中a为0.40〜1，b为0.30〜0，a + b为1.00，其中，所述III-V结构（1））包括缓冲器（11）和阻挡部分（12），并且具有背离Si单晶衬底（4）的顶表面，所述顶表面具有化学组成Ga g X x P p Sb s Z z，其包含例如GaPSb，GaBPSb，GaInPSb和GaInPSbAs。

4. 发明公开

EP2702606A2 SUBSTRATE COMPRISING SI-BASE AND INAS-LAYER 审中-公开
标题翻译：与SI基和INAS层基板
公开(公告)号：EP2702606A2
公开(公告)日：2014-03-05
申请号：EP12729250.6
申请日：2012-04-27
申请人： QuNano AB
发明人： WERNERSSON, Lars-Erik , GORJI GHALAMESTANI, Sepideh
IPC分类号： H01L21/02
CPC分类号： H01L21/02617 , B82Y10/00 , B82Y40/00 , H01L21/02381 , H01L21/02463 , H01L21/02466 , H01L21/02505 , H01L21/02538 , H01L21/02546 , H01L21/02549 , H01L21/02603 , H01L21/0262 , H01L21/02653 , H01L29/0676 , H01L29/205 , H01L29/66469 , H01L29/775
摘要： The present invention relates to a substrate (5) comprising a Si-base (1) and an InAs-layer (4) provided on said Si-base where said InAs-layer (4) has a thickness between 100 and 500 nanometers and root-mean-square roughness of the upper surface of said InAs-layer (4) is below 1 nanometer. The invention further relates to a method for forming said substrate. The invention also relates to growing InAs-nanowires (7) as well as a GaSb-layer (17) on said substrate (5).

5. 发明公开

EP2648234A1 LIGHT RECEIVING ELEMENT, SEMICONDUCTOR EPITAXIAL WAFER, METHOD FOR MANUFACTURING THE LIGHT RECEIVING ELEMENT AND THE SEMICONDUCTOR EPITAXIAL WAFER, AND DETECTING APPARATUS 审中-公开
标题翻译： LIGHT记录元件，半导体外延生长基板，其制造方法LIGHT记录元件和半导体晶片检测装置外延SO
公开(公告)号：EP2648234A1
公开(公告)日：2013-10-09
申请号：EP11844996.6
申请日：2011-11-29
申请人： Sumitomo Electric Industries, Ltd.
发明人： MIURA, Kohei , INADA, Hiroshi , IGUCHI, Yasuhiro , SAITO, Tadashi
IPC分类号： H01L31/10 , H01L31/0304 , H01L21/205 , H01L27/146
CPC分类号： H01L31/109 , B82Y20/00 , H01L21/02392 , H01L21/02463 , H01L21/02466 , H01L21/02505 , H01L21/02546 , H01L21/02549 , H01L27/1446 , H01L27/1464 , H01L31/0304 , H01L31/035236 , H01L31/075 , H01L31/105 , H01L31/184 , Y02E10/544 , Y02E10/548 , Y02P70/521
摘要： A light receiving element includes an InP substrate that is transparent to light having a wavelength of 3 to 12 µm, a buffer layer located in contact with the InP substrate, and a light-receiving layer having a multiple quantum well structure, the light-receiving layer having a cutoff wavelength of 3 µm or more and being lattice-matched with the buffer layer. In the light receiving element, the buffer layer is epitaxially grown on the InP substrate while the buffer layer and the InP substrate exceed a range of a normal lattice-matching condition, and the buffer layer is constituted by a GaSb layer.
摘要翻译：光接收元件包括在InP衬底上确实是透明的具有3至12微米，位于与所述InP基板接触的缓冲层，和具有多量子阱结构的光接收层，光接收的波长的光层具有3微米或更大的截止波长并且是晶格匹配的与缓冲层。在光接收元件中，缓冲层被外延生长在InP衬底，而缓冲层和InP衬底上超过一定范围的正常晶格匹配条件，并且所述缓冲层是由一个的GaSb层构成。

6. 发明公开

EP2626890A1 EPITAXIAL WAFER, LIGHT-RECEIVING ELEMENT, OPTICAL SENSOR DEVICE, AND METHOD FOR MANUFACTURING EPITAXIAL WAFER AND LIGHT-RECEIVING ELEMENT 审中-公开
标题翻译：外延片，光接收元件，用于生产外延片光学传感器装置和方法以及记录元件的光
公开(公告)号：EP2626890A1
公开(公告)日：2013-08-14
申请号：EP11830608.3
申请日：2011-10-03
申请人： Sumitomo Electric Industries, Ltd.
发明人： FUJII, Kei , AKITA, Katsushi , ISHIZUKA, Takashi
IPC分类号： H01L21/205 , C23C16/30 , C30B25/10 , C30B29/40 , H01L31/10
CPC分类号： H01L21/0262 , B82Y20/00 , C30B25/183 , C30B29/403 , H01L21/02387 , H01L21/02392 , H01L21/02458 , H01L21/02463 , H01L21/02466 , H01L21/02507 , H01L21/0254 , H01L21/02546 , H01L21/02549 , H01L31/035236 , H01L31/105 , H01L31/1844 , Y02E10/544 , Y02P70/521
摘要： Provided are an epitaxial wafer, a photodiode, and the like that include an antimony-containing layer and can be efficiently produced such that protruding surface defects causing a decrease in the yield can be reduced and impurity contamination causing degradation of the performance can be suppressed.
The production method includes a step of growing an antimony (Sb)-containing layer on a substrate 1 by metal-organic vapor phase epitaxy using only metal-organic sources; and a step of growing, on the antimony-containing layer, an antimony-free layer including a window layer 5, wherein, from the growth of the antimony-containing layer to completion of the growth of the window layer, the growth is performed at a growth temperature of 425°C or more and 525°C or less.
摘要翻译：本发明提供了在外延晶片，光电二极管等，其包括在含锑层和能够有效地制造搜索没有突出引起的产率降低的表面缺陷可以减少和杂质污染导致性能的劣化可以被抑制。该生产方法包括在锑（Sb）上的基板1通过金属有机气相外延仅利用金属有机源生长含层的步骤; 和成长，含锑层上，以无锑层包括窗口层5，worin，从含锑层的生长到窗口层的生长完成的步骤中，将生长在执行的的425℃或更大且525℃或更小的生长温度。

7. 发明公开

EP2477234A1 GROUP III-V COMPOUND SEMICONDUCTOR LIGHT RECEIVING ELEMENT, METHOD FOR MANUFACTURING GROUP III-V COMPOUND SEMICONDUCTOR LIGHT RECEIVING ELEMENT, LIGHT RECEIVING ELEMENT, AND EPITAXIAL WAFER 有权
标题翻译： III-V族复合半导体发光记录元件，制造方法中III-V族复合半导体发光记录元件，光线和记录元件外延片SO
公开(公告)号：EP2477234A1
公开(公告)日：2012-07-18
申请号：EP10813575.7
申请日：2010-07-21
申请人： Sumitomo Electric Industries, Ltd.
发明人： AKITA Katsushi , ISHIZUKA Takashi , FUJII Kei , NAGAI Youichi
IPC分类号： H01L31/10
CPC分类号： H01L31/035209 , H01L21/02392 , H01L21/02458 , H01L21/02461 , H01L21/02463 , H01L21/02466 , H01L21/02507 , H01L21/02546 , H01L31/03042 , H01L31/03046 , H01L31/035236 , H01L31/109 , H01L31/184 , Y02E10/544 , Y02P70/521
摘要： An object of the present invention is to provide a group III-V compound semiconductor photo detector comprising an absorption layer having a group III-V compound semiconductor layer containing Sb as a group V constituent element, and an n-type InP window layer, resulting in reduced dark current. The InP layer 23 grown on the absorption layer 23 contains antimony as impurity, due to the memory effect with antimony which is supplied during the growth of a GaAsSb layer of the absorption layer 21. In the group III-V compound semiconductor photo detector 11, the InP layer 23 contains antimony as impurity and is doped with silicon as n-type dopant. Although antimony impurities in the InP layer 23 generate holes, the silicon contained in the InP layer 23 compensates for the generated carriers. As a result, the second portion 23d of the InP layer 23 has sufficient n-type conductivity.
摘要翻译：本发明的一个目的是提供一种III-V族化合物半导体光电检测器吸收层的包含具有含Sb作为V族构成元素的III-V族化合物半导体层和n型InP窗口层，导致降低暗电流。生长在吸收层23上的InP层23含有锑作为杂质，由于其在吸收层21的一个的GaAsSb层的生长在III-V族化合物半导体光电检测器11中提供有锑的记忆效应的所有， InP层23含有锑作为杂质和掺杂有硅作n型掺杂剂。虽然在InP层23锑杂质产生的孔中，包含在InP层23中的硅补偿所产生的载流子。其结果是，在InP层23的第二部分23d具有足够的n型导电性。

8. 发明公开

EP1168466A2 Method for manufacturing semiconductors thin film, and magnetoelectric conversion element provided with semiconductor thin film thereby manufactured 有权
标题翻译：一种用于制造半导体薄膜的方法，和磁电转换元件具有这样的薄膜
公开(公告)号：EP1168466A2
公开(公告)日：2002-01-02
申请号：EP01114662.8
申请日：2001-06-19
申请人： Murata Manufacturing Co., Ltd.
发明人： Ueda, Masaya, (A170)Intellectual Property Dept. , Sato, Tomoharu, (A170)Intellectual Property Dept. , Nishikawa, Masanaga, (170)Intell. Property Dept.
IPC分类号： H01L43/10 , H01L43/12
CPC分类号： H01L43/12 , H01L21/02381 , H01L21/02466 , H01L21/02491 , H01L21/02502 , H01L21/02549 , H01L21/02631 , H01L21/02658 , H01L43/14
摘要： A method for manufacturing a semiconductor thin film having high carrier mobility, and a magnetoelectric conversion element provided with the semiconductor thin film manufactured by the aforementioned method are provided. The temperature of the Si single crystal substrate is raised to 270°C to 320°C, and an In buffer layer is formed by an electron beam heating type vacuum evaporation method. Subsequently, an initial seed layer made of Sb and In is formed. The temperature of the Si single crystal substrate is raised to 460°C to 480°C, and thereafter, a retention time approximated by a predetermined function of the temperature of the Si single crystal substrate is provided. Then, a main growth layer made of Sb and In is formed.
摘要翻译：本发明提供一种用于制造具有高载流子迁移的半导体薄膜，并且设置有通过上述方法制造的半导体薄膜的磁电转换元件的方法。在Si单晶衬底的温度升高到270℃至320℃，并在缓冲层是通过电子束加热式真空蒸镀法形成。随后，由Sb和在初始种子层上形成。在Si单晶衬底的温度升高到460℃至480℃，并且此后，提供了一种通过在Si单晶衬底的温度的预定函数近似的保留时间。然后，由Sb和In的主生长层中形成。

9. 发明公开

EP0632485A2 Method of fabricating semicondutor thin film and method of fabricating hall-effect device 失效
标题翻译：一种用于制造半导体薄膜及其制造方法的霍尔效应器件的方法。
公开(公告)号：EP0632485A2
公开(公告)日：1995-01-04
申请号：EP94108235.6
申请日：1994-05-27
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： Kawasaki, Tetuo , Koretika, Tetuhiro , Kitabatake, Makoto , Hirao, Takashi
IPC分类号： H01L21/20 , H01L43/14
CPC分类号： H01L43/08 , H01L21/02381 , H01L21/02466 , H01L21/02502 , H01L21/02549 , H01L21/02631 , H01L43/065 , Y10S438/974
摘要： A method of fabricating a semiconductor thin film (4) is initiated with preparing a substrate (1) having a surface consisting of a single crystal of Si. The surface has an oxide film. Then, the oxide film is removed. The dangling bonds of the Si atoms on the surface are terminated with hydrogen atoms. An initial layer (2) is formed on the substrate of the single crystal of Si terminated with the hydrogen atoms, of at least one selected from the group consisting of Al, Ga, and In. A buffer layer (3) containing at least In and Sb is formed on the initial layer. A semiconductor thin film (4) containing at least In and Sb is formed on the buffer layer (3) at a temperature higher than the temperature at which the buffer layer (3) is started to be formed.
There is also disclosed a method of fabricating a Hall-effect device. This method is initiated with forming a semiconductor thin film by making use of the above-described fabrication method. Then, electrodes are attached to the thin film.
摘要翻译：一种制造半导体薄膜的方法与制备具有表面由Si的单晶的衬底开始。表面有氧化物的电影。然后，将氧化膜被除去。表面上硅原子的悬空键终止氢原子。初始层形成在Si的单晶中的至少一个与氢原子封端的，从所述组自由Al，Ga和In中选择的底物。包含缓冲层至少In与Sb的形成的初始层上。一种半导体薄膜至少包含In和Sb被形成在比缓冲层开始被形成的温度更高的温度下在缓冲层上。因此，存在游离缺失盘制造霍尔效应器件的方法。这个方法与通过使用上述制造方法形成的半导体薄膜发起。然后，将电极连接到薄膜。

10. 发明授权

EP3067941B1 INFRARED DETECTION ELEMENT 有权
公开(公告)号：EP3067941B1
公开(公告)日：2018-05-23
申请号：EP14860034.9
申请日：2014-10-31
申请人： Hamamatsu Photonics K.K.
发明人： MISHIMA Asuka , OSHIMURA Yoshinori
IPC分类号： H01L31/105 , H01L31/0304
CPC分类号： H01L31/03046 , H01L21/02395 , H01L21/02463 , H01L21/02466 , H01L21/02505 , H01L21/02546 , H01L21/02549 , H01L21/02631 , H01L31/0304 , H01L31/0336 , H01L31/035236 , H01L31/105 , Y02E10/544
摘要： This infrared detection element includes a buffer layer (InAsSb layer) 3, a buffer layer (InAs layer) 4, and a light absorption layer (InAsSb layer) 5. A critical film thickness hc of the InAs layer satisfies a relation of hc

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式