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1. 发明公开

EP3293763A1 SEMICONDUCTOR DEVICE LAYOUT STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体器件布局结构及其制造方法
公开(公告)号：EP3293763A1
公开(公告)日：2018-03-14
申请号：EP17186560.3
申请日：2017-08-17
申请人： Semiconductor Manufacturing International Corporation (Beijing) , Semiconductor Manufacturing International Corporation (Shanghai)
发明人： QIAN, Gang , MIAO, Yiming , SUN, Yanlin , CHEN, Xubo
IPC分类号： H01L27/11 , H01L21/8234
CPC分类号： H01L29/66545 , G11C11/417 , H01L21/265 , H01L21/76224 , H01L21/76895 , H01L21/823475 , H01L23/535 , H01L27/1104 , H01L27/1112 , H01L29/0649
摘要： A semiconductor device includes a semiconductor substrate, a trench isolator portion in the semiconductor substrate, a dummy gate on the semiconductor substrate, a first doped region between the trench isolator portion and the dummy gate in the semiconductor substrate, and a first connecting member electrically connected the dummy gate with the first doped region. With the dummy gate electrically connected to the first doped region, a transistor including the dummy gate is turned off, thereby preventing the occurrence of current leakage and improving the reliability of a memory device having the semiconductor device.
摘要翻译：一种半导体器件，包括：半导体衬底;半导体衬底中的沟槽隔离器部分;半导体衬底上的伪栅极;半导体衬底中的沟槽隔离器部分和伪栅极之间的第一掺杂区域;以及第一连接构件，具有第一掺杂区的伪栅极。通过伪栅极电连接到第一掺杂区域，包括伪栅极的晶体管截止，由此防止电流泄漏的发生并且提高具有该半导体器件的存储器件的可靠性。

2. 发明授权

EP2973577B1 SYSTEM AND METHOD TO REGULATE OPERATING VOLTAGE OF A MEMORY ARRAY 有权
标题翻译：调节存储器阵列的操作电压的系统和方法
公开(公告)号：EP2973577B1
公开(公告)日：2017-12-20
申请号：EP14722821.7
申请日：2014-03-11
申请人： Qualcomm Incorporated
发明人： SONG, Stanley Seungchul , WANG, Zhongze
IPC分类号： G11C11/417 , G11C11/413 , G11C7/04 , G11C5/14 , G06F17/50
CPC分类号： G11C11/4074 , G06F17/5072 , G11C5/147 , G11C7/04 , G11C11/413 , G11C11/417

3. 发明公开

EP3245584A2 METHODS AND APPARATUSES FOR GENERATING RANDOM NUMBERS BASED ON BIT CELL SETTLING TIME 审中-公开
标题翻译：基于位细胞稳定时间生成随机数的方法和设备
公开(公告)号：EP3245584A2
公开(公告)日：2017-11-22
申请号：EP15874419.3
申请日：2015-12-14
申请人： Qualcomm Incorporated
发明人： CHEN, Nan , ZHANG, Junmou , CHEN, Min
IPC分类号： G06F7/58
CPC分类号： G11C11/417 , G06F7/588 , G11C7/1006
摘要： One feature pertains to a true random number generator that utilizes the settling time of a bit cell as an entropy source to generate random digital output values. The bit cell may be a static random access memory bit cell. The bit cell's settling time may be converted into a digital output using an analog to digital converter. A plurality of bit cells may serially couple to one another in a ring formation. The bit cell ring can then be enabled such that each bit cell of the plurality of bit cells achieves a settling value that activates the subsequent bit cell in the ring causing it to in turn reach a settling value, and so on. An output node of one of the bit cells in the ring can then be sampled using a flip-flop to generate a continuous stream of random bits.

4. 发明公开

EP2529376A4 DATA PROCESSING SYSTEM HAVING BROWN-OUT DETECTION CIRCUIT 有权转让
公开(公告)号：EP2529376A4
公开(公告)日：2017-11-15
申请号：EP11737455
申请日：2011-01-19
申请人： NXP USA INC
发明人： DAO CHRIS C , PIETRI STEFANO , VILAS BOAS ANDRE LUIS
IPC分类号： G01R19/165 , G06F11/30 , G11C11/417
CPC分类号： G01R19/16552 , G01R19/16519 , G06F11/3024 , G06F11/3062 , G06F11/3093 , G11C11/417

5. 发明公开

EP3155722A1 CIRCUIT SKEW COMPENSATION TRIGGER SYSTEM 审中-实审
标题翻译：澳大利亚麻省理工学院
公开(公告)号：EP3155722A1
公开(公告)日：2017-04-19
申请号：EP15806764.5
申请日：2015-06-12
申请人： Synopsys, Inc.
发明人： KAWA, Jamil , NGUYEN, Thu , LEUNG, Raymond
IPC分类号： H03K3/2893 , H03K5/1252
CPC分类号： H03K19/00384 , G11C5/14 , G11C8/08 , G11C11/417 , G11C29/023 , G11C29/028
摘要： A circuit skew compensation trigger system comprises a voltage divider including a P-transistor and an N-transistor and a center node in the voltage divider pulled to a first level. The circuit skew compensation trigger system further comprising a trigger to activate when a skew between the P-transistor and the N-transistor is above a threshold. The trigger to initiate a compensator to adjust for the skew.
摘要翻译：电路偏移补偿触发系统包括分压器，该分压器包括P晶体管和N晶体管，分压器中的中心节点拉至第一电平。电路偏移补偿触发系统还包括当P晶体管和N晶体管之间的偏斜高于阈值时激活的触发器。启动补偿器的触发器调整偏移。

6. 发明公开

EP3032540A4 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
标题翻译： VORRICHTUNG MIT EINER INTEGRIERTEN HALBLEITERSCHALTUNG
公开(公告)号：EP3032540A4
公开(公告)日：2017-03-15
申请号：EP13891121
申请日：2013-08-06
申请人： RENESAS ELECTRONICS CORP
发明人： NII KOJI
IPC分类号： H01L27/11 , G11C8/16 , G11C11/412 , H01L27/02
CPC分类号： H01L27/1104 , G11C8/16 , G11C11/412 , G11C11/417 , H01L23/528 , H01L27/0207 , H01L27/1116 , H01L29/1095 , H01L29/41758 , H01L29/7851 , H01L2924/0002 , H01L2924/00
摘要： In a chip that processes image information or the like, a multi-port SRAM is mixed together with a logic circuit such as a digital signal processing circuit. In that case, for example, in case that the 3 port is used, the 1 port may serve as a differential write and readout port, and the 2 port may serve as a single ended readout dedicated port. However, in this configuration, it is obvious that there is a problem, in that while the occupied area of an embedded SRAM is reduced, the number of write and readout ports is limited to only one, and readout characteristics as fast as differential readout cannot be expected in single ended readout. The outline of the present application is that three differential write and readout ports are included in a memory cell structure of the embedded SRAM, an N-well region, for example, is arranged at the center of a cell, and a P-well region is arranged on both sides thereof.
摘要翻译：在处理图像信息等的芯片中，多端口SRAM与诸如数字信号处理电路的逻辑电路混合在一起。在这种情况下，例如，在使用3端口的情况下，1端口可以用作差分写入和读出端口，并且2端口可以用作单端读出专用端口。然而，在这种配置中，显然存在一个问题，即当嵌入式SRAM的占用面积减小时，写入和读出端口的数量仅限于一个，并且与差分读出一样快的读出特性不能预计在单端读出。本申请的概述是三个差分写入和读出端口包括在嵌入式SRAM的存储单元结构中，例如，N阱区域被布置在单元的中心，并且P阱区域布置在其两侧。

7. 发明授权

EP2380174B1 SELF-TUNING OF SIGNAL PATH DELAY IN CIRCUIT EMPLOYING MULTIPLE VOLTAGE DOMAINS 有权
标题翻译：多个电压域自调节信号路径延迟发作
公开(公告)号：EP2380174B1
公开(公告)日：2016-03-23
申请号：EP09793663.7
申请日：2009-12-11
申请人： QUALCOMM Incorporated
发明人： CHAI, Chiaming , LILES, Stephen Edward
IPC分类号： G11C7/08 , G11C11/413 , G11C11/417 , G11C11/419 , G11C7/22
CPC分类号： G11C7/08 , G11C7/22 , G11C7/222 , G11C11/413 , G11C11/417 , G11C11/419

8. 发明公开

EP2948954A1 STATIC RANDOM ACCESS MEMORIES (SRAM) WITH READ-PREFERRED CELL STRUCTURES, WRITE DRIVERS, RELATED SYSTEMS, AND METHODS 有权
标题翻译：静态随机存取存储器（SRAM）伴读优先小区的结构，编写驱动程序，相关系统和方法
公开(公告)号：EP2948954A1
公开(公告)日：2015-12-02
申请号：EP14702731.2
申请日：2014-01-22
申请人： Qualcomm Incorporated
发明人： JUNG, Seong-Ook , YANG, Younghwi , YANG, Bin , WANG, Zhongze , YEAP, Choh fei
IPC分类号： G11C11/412 , G11C11/417
CPC分类号： G11C11/412 , G11C11/417 , G11C11/419 , H01L27/0207 , H01L27/1104 , Y10T29/41
摘要： Static random access memories (SRAM) with read-preferred cell structures and write drivers are disclosed. In one embodiment, the SRAM has a six transistor bit cell. The read-preferred bit cell is implemented by providing two inverters, each having a pull up transistor, a pull down transistor and a pass gate transistor. Each pull up transistor is associated with a feedback loop. The feedback loop improves random static noise margin. Each transistor has a width and a length. The lengths of the pass gate transistors are increased. The widths of the pull down transistors are equal to one another and also equal to the widths of the pass gate transistors. The widths of the pass gate and pull down transistors may also be increased relative to prior designs. A write assist circuit may also be used to improve performance.

9. 发明公开

EP2798638A1 APPARATUS AND METHOD FOR IMPROVING POWER DELIVERY IN A MEMORY, SUCH AS, A RANDOM ACCESS MEMORY 有权转让
标题翻译：装置和方法用于改善STORE电源，例如，一个随机存取存储器
公开(公告)号：EP2798638A1
公开(公告)日：2014-11-05
申请号：EP11879108.6
申请日：2011-12-28
申请人： Intel Corporation
发明人： TAUFIQUE, Mohammed H. , CUMMINGS, Daniel J. , NGO, Hieu T. , GANGULY, Shantanu
IPC分类号： G11C7/12 , G11C5/14 , G11C11/413
CPC分类号： G11C11/4091 , G11C7/12 , G11C11/417
摘要： Embodiments of an apparatus and method to improve power delivery including a pre-charge circuit that may include a first voltage supply rail configured to provide a first voltage amount to perform a first phase of a pre-charge of a bit line and a second voltage supply rail configured to provide a second voltage amount to perform a second phase of the pre-charge of the bit line are described herein. In embodiments, the pre-charge circuit may be a pre charge circuit for a static random-access memory (SRAM) memory cell.

10. 发明公开

EP2777045A1 CIRCUIT DE POLARISATION ARRIERE D'INVERSEURS POUR REDUCTION DE LA CONSOMMATION D'UNE MÉMOIRE SRAM 有权
标题翻译： SCHALTUNGSANORDNUNG ZUR VORSPANNUNG DER INVERTERN-WANNEN ZUR REDUZIERUNG DES ENERGIEVERBRAUCHS EINES SRAMS
公开(公告)号：EP2777045A1
公开(公告)日：2014-09-17
申请号：EP12775242.6
申请日：2012-10-18
申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives
发明人： THOMAS, Olivier , MAKOSIEJ, Adam , VLADIMIRESCU, Andrei
IPC分类号： G11C5/14 , G11C11/412 , H03K19/00 , G11C11/417
CPC分类号： H03K3/012 , G11C5/14 , G11C5/146 , G11C5/147 , G11C11/4074 , G11C11/41 , G11C11/412 , G11C11/417 , G11C13/0038 , G11C2207/2227
摘要： The invention relates to integrated CMOS circuits with very low power consumption at rest, and especially volatile SRAM memories. The inverters of the circuit are formed by an nMOS transistor and a pMOS transistor. According to the invention, a biasing circuit applies a first reverse bias voltage NBIAS to the wells of the nMOS transistors and a second reverse bias voltage PBIAS to the wells of the pMOS transistors. The biasing circuit comprises: a detecting array (SN) formed by many inverters in parallel, having a common output (SN_out) delivering a logic signal the value of which depends on the reverse bias voltages applied to the array; a circuit (CTRL, SA) for producing incrementing or decrementing pulses, controlled by the output of the detecting array; and an integrating circuit (BFP, BFN) connected to the pulse producing circuit, in order to produce and gradually vary, incrementally in response to these pulses, a biasing voltage PBIAS and a biasing voltage NBIAS.
摘要翻译：提供空闲时具有非常低的消耗的CMOS集成电路，特别是SRAM易失性存储器。电路的反相器由NMOS晶体管和PMOS晶体管组成。偏置电路将第一后偏置电压NBIAS施加到NMOS晶体管的阱，并将第二后偏置电压PBIAS施加到PMOS晶体管的阱。偏置电路包括：由许多并联的反相器组成的检测阵列，具有提供逻辑信号的公共输出，该逻辑信号的值取决于施加到阵列的后偏置电压，用于产生由输出控制的递增或递减脉冲的电路以及与脉冲产生电路连接的积分电路，用于响应于这些脉冲，偏置电压PBIAS和偏置电压NBIAS逐渐增加产生和变化。

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