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1. 发明公开

EP1378996A2 Correction circuit, delay circuit, and ring oscillator circuit 有权
标题翻译： Korrekturschaltung，Verzögerungsschaltung和Ringoszillator
公开(公告)号：EP1378996A2
公开(公告)日：2004-01-07
申请号：EP03253227.7
申请日：2003-05-23
申请人： SHARP KABUSHIKI KAISHA
发明人： Morikawa, Yoshinao
IPC分类号： H03K5/13 , H03K3/354
CPC分类号： H03K3/0315 , H03K3/011 , H03K5/133 , H03K2005/00026 , H03K2005/00039 , H03K2005/0013 , H03K2005/00143 , H03K2005/00208
摘要： A correction circuit for generating a control signal for correcting a characteristic change of a first transistor includes a control signal adjusting section including a constant voltage reduction element for determining either one of a maximum voltage and a minimum voltage of the control signal and a second transistor for determining a characteristic of the control signal, a gate electrode of the second transistor receiving a prescribed voltage; and a resistor section including two types of resistor elements having resistance values of different temperature dependency characteristics from each other, the resistor elements being connected in series. The constant voltage reduction element, the second transistor, and the resistor section are connected in series between a supply terminal and a ground terminal. The control signal is output from a connection point between the control signal adjusting section and the resistor section.
摘要翻译：用于产生用于校正第一晶体管的特性变化的控制信号的校正电路包括：控制信号调节部，包括用于确定控制信号的最大电压和最小电压中的任一个的恒定电压降低元件;以及第二晶体管，确定所述控制信号的特性，所述第二晶体管的栅电极接收规定的电压; 以及电阻器部分，其包括具有彼此不同的温度依赖特性的电阻值的两种类型的电阻器元件，电阻器元件串联连接。恒定电压降低元件，第二晶体管和电阻器部分串联连接在电源端子和接地端子之间。控制信号从控制信号调节部和电阻部之间的连接点输出。

2. 发明授权

EP0599275B1 Circuit intégré semi-conducteur comportant un circuit de retard avec une caractéristique tension-retard proportionelle à la tension d'alimentation 失效
标题翻译：具有延迟电路，包括一个正比于工作电压，电压延迟的半导体集成电路
公开(公告)号：EP0599275B1
公开(公告)日：1996-03-20
申请号：EP93118839.5
申请日：1993-11-23
申请人： NEC CORPORATION
发明人： Chonan, Toru
IPC分类号： H03K5/13
CPC分类号： H01L27/0218 , H03K5/133 , H03K2005/0013 , H03K2005/00143 , H03K2005/00195

3. 发明公开

EP0423963A2 Temperature self-compensated time delay circuits 失效
标题翻译： Temitaturkompensation（Zeitverzögerungsschaltungen）
公开(公告)号：EP0423963A2
公开(公告)日：1991-04-24
申请号：EP90310649.0
申请日：1990-09-28
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Chen, Kou-Su
IPC分类号： H03K5/13
CPC分类号： H03K5/133 , H03K2005/00065 , H03K2005/00143 , H03K2005/00195
摘要： A constant time delay circuit which is insensitive to variations in temperature and has no D.C. power dissipation includes a temperature-insensitive reference current source (12) for dynamically charging and discharging a capacitive load (M5), a polysilicon resistor (16), and at least one time delay control circuit (14) to produce a constant time delay. In an alternate embodiment, there is provided a temperature self-compensated programmable delay circuit which includes electrically programmable resistor means (30) for adjusting the total resistance in a temperature-insensitive reference current source (12b). As a result, the amount of the reference current is controlled so as to obtain a desired delay time.
摘要翻译：对温度变化不敏感并且没有直流功率耗散的恒定时间延迟电路包括用于动态地对容性负载（M5）充电和放电的温度不敏感参考电流源（12），多晶硅电阻器（16）至少一个时间延迟控制电路（14）产生恒定的时间延迟。在替代实施例中，提供了一种温度自补偿可编程延迟电路，其包括用于调节温度不敏感参考电流源（12b）中的总电阻的电可编程电阻器装置（30）。结果，控制参考电流的量以获得期望的延迟时间。

4. 发明公开

EP1791256A1 Clock signal output circuit 有权
标题翻译： Taktsignalausgangsschaltung
公开(公告)号：EP1791256A1
公开(公告)日：2007-05-30
申请号：EP06024662.6
申请日：2006-11-28
申请人： DENSO CORPORATION
发明人： Ohta, Norikazu, c/o K.K. Toyota Chuo Kenkyusho , Ohira, Yoshie, c/o K.K. Toyota Chuo Kenkyusho , Makino, Yasuaki , Ariyoshi, Hiromi
IPC分类号： H03K3/03
CPC分类号： H03K3/354 , H03K3/0315 , H03K2005/0013 , H03K2005/00143 , H03K2005/00169
摘要： 1 st to n th pairs of transistors (1-3) (n=an odd number) are connected in parallel, and each pair of transistors (1-3) has an upper transistor (1a-3a) and a lower transistor (1 b-3b) connected in series. A point (1 d-3d) between the upper transistor (1a-3a) and the lower transistor (1b-3b) of a preceding pair of transistors is connected to a gate of the lower transistor of a subsequent transistor, and the point between the upper transistor and the lower transistor of n th pair of transistors is connected to the gate of the first lower transistor. A capacitor (1c-3c) is inserted between the lower transistor (1b-3b) and a direct power source (12). A current regulating circuit (26) is connected to gates of the upper transistors (1a-5a), wherein the current regulating circuit (26) supplies a gate voltage to each gate of the each upper transistor (1a-5a). The magnitude of the gate voltage is adjusted such that a magnitude of current that flows between the source and drain of the upper transistor (1 a-3a) due to the gate voltage is proportional to a voltage between the source and gate of the corresponding lower transistor (1 b-3b) when the lower transistor (1 b-3b) is turned on.
摘要翻译：第一至第n对晶体管（1-3）（n =奇数）并联连接，每对晶体管（1-3）具有上晶体管（1a-3a）和下晶体管（1） b-3b）串联连接。前一对晶体管的上部晶体管（1a-3a）和下部晶体管（1b-3b）之间的点（1d-3d）连接到随后的晶体管的下部晶体管的栅极，第n对晶体管的上晶体管和下晶体管连接到第一下晶体管的栅极。电容器（1c-3c）插入在下部晶体管（1b-3b）和直接电源（12）之间。电流调节电路（26）连接到上部晶体管（1a-5a）的栅极，其中电流调节电路（26）向每个上部晶体管（1a-5a）的每个栅极提供栅极电压。调节栅极电压的大小，使得由于栅极电压而在上部晶体管（1a-3a）的源极和漏极之间流动的电流的大小与相应较低的源极和栅极之间的电压成比例当下晶体管（1b-3b）导通时，晶体管（1b-3b）。

5. 发明授权

EP0527366B1 Variable delay circuit 失效
标题翻译：可变延迟电路。
公开(公告)号：EP0527366B1
公开(公告)日：1995-09-27
申请号：EP92112549.8
申请日：1992-07-22
申请人： ADVANTEST CORPORATION
发明人： Ochiai, Katsumi
IPC分类号： G01R31/28 , G01R31/3177
CPC分类号： H03K5/131 , G01R31/3191 , G01R31/31922 , G01R31/31926 , H03K2005/00104 , H03K2005/00143
摘要： A plurality of delay stages (21) are connected in cascade, each delay stage having a construction in which either one of a path of a delay element (17) utilizing the propagation delay of a gate array and a path (18) not passing through the delay element is selected by a path selector (19). Each bit of control data is used to control the path selector of the corresponding delay stages. Composite delays are measured for all combinations of such paths, control data (DC) which provides a measured composite delay closest to an intended delay corresponding to each set data (DL) is determined and is prestored in a main conversion table (22). A prediction is made, through calculation, as to a delay for each control data when ambient temperature rises INCREMENT T DEG C from a temperature TO at which the main conversion table was produced, the thus predicted delay is used to determine control data which provides a predicted delay closest to an intended delay for each set data, and the relationship between the control data and the set data is prestored in a corrected conversion table (31, 32). Ambient temperature is detected by temperature detection/control circuit (36). When the difference INCREMENT t between the detected temperature and the temperature tO is INCREMENT t /= INCREMENT T DEG C, control data of the corrected conversion table is selected, and the path selector of each delay stage is controlled accordingly.

6. 发明公开

EP0527366A1 Variable delay circuit 失效
标题翻译：变量Verzögerungsschaltung。
公开(公告)号：EP0527366A1
公开(公告)日：1993-02-17
申请号：EP92112549.8
申请日：1992-07-22
申请人： ADVANTEST CORPORATION
发明人： Ochiai, Katsumi
IPC分类号： G01R31/28 , G01R31/3177
CPC分类号： H03K5/131 , G01R31/3191 , G01R31/31922 , G01R31/31926 , H03K2005/00104 , H03K2005/00143
摘要： A plurality of delay stages (21) are connected in cascade, each delay stage having a construction in which either one of a path of a delay element (17) utilizing the propagation delay of a gate array and a path (18) not passing through the delay element is selected by a path selector (19). Each bit of control data is used to control the path selector of the corresponding delay stages. Composite delays are measured for all combinations of such paths, control data (D C ) which provides a measured composite delay closest to an intended delay corresponding to each set data (D L ) is determined and is prestored in a main conversion table (22). A prediction is made, through calculation, as to a delay for each control data when ambient temperature rises △T°C from a temperature T O at which the main conversion table was produced, the thus predicted delay is used to determine control data which provides a predicted delay closest to an intended delay for each set data, and the relationship between the control data and the set data is prestored in a corrected conversion table (31, 32). Ambient temperature is detected by temperature detection/control circuit (36). When the difference △t between the detected temperature and the temperature t O is △t
摘要翻译：多个延迟级（21）级联连接，每个延迟级具有利用门阵列的传播延迟的延迟元件（17）的路径和不通过的路径（18）的结构延迟元件由路径选择器（19）选择。控制数据的每一位用于控制相应延迟级的路径选择器。对这种路径的所有组合测量复合延迟，确定提供最接近对应于每个集合数据（DL）的预期延迟的测量复合延迟的控制数据（DC），并将其预存储在主转换表（22）中。通过计算，当环境温度从产生主转换表的温度T0升高到INCREMENT T°C时，通过计算来预测每个控制数据的延迟，由此预测的延迟用于确定提供预测延迟最接近于每个设定数据的预期延迟，并且控制数据与设定数据之间的关系预先存储在校正转换表（31,32）中。环境温度由温度检测/控制电路（36）检测。当检测温度和温度t0之间的差值INCREMENT t为INCREMENT t / = INCREMENT T DEGC时，选择校正的转换表的控制数据，并且相应地控制每个延迟级的路径选择器。

7. 发明公开

EP0423963A3 Temperature self-compensated time delay circuits 失效
标题翻译：温度自补偿时间延迟电路
公开(公告)号：EP0423963A3
公开(公告)日：1991-09-18
申请号：EP90310649.0
申请日：1990-09-28
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Chen, Kou-Su
IPC分类号： H03K5/13
CPC分类号： H03K5/133 , H03K2005/00065 , H03K2005/00143 , H03K2005/00195
摘要： A constant time delay circuit which is insensitive to variations in temperature and has no D.C. power dissipation includes a temperature-insensitive reference current source (12) for dynamically charging and discharging a capacitive load (M5), a polysilicon resistor (16), and at least one time delay control circuit (14) to produce a constant time delay. In an alternate embodiment, there is provided a temperature self-compensated programmable delay circuit which includes electrically programmable resistor means (30) for adjusting the total resistance in a temperature-insensitive reference current source (12b). As a result, the amount of the reference current is controlled so as to obtain a desired delay time.

8. 发明授权

EP2239849B1 Apparatus and method for compensating for process, voltage, and temperature variation of the time delay of a digital delay line 失效转让
标题翻译：用于补偿数字延迟线的时间延迟的过程，电压和温度变化的设备和方法
公开(公告)号：EP2239849B1
公开(公告)日：2018-03-14
申请号：EP10152009.6
申请日：2010-01-28
申请人： III Holdings 12, LLC
发明人： Seefeldt, James , Feng, Xiaoxin , Roper, Weston
IPC分类号： H03K5/13 , H03K5/133 , H03L7/08 , H03L7/081 , H03L7/085 , G11C7/10 , G11C7/22 , G11C11/4072 , G11C11/4093 , G11C29/02 , H03K5/00 , G11C7/04
CPC分类号： G11C29/022 , G11C7/04 , G11C7/1057 , G11C7/1066 , G11C7/222 , G11C11/4072 , G11C11/4093 , G11C29/023 , G11C29/028 , H03K5/133 , H03K2005/00097 , H03K2005/00123 , H03K2005/0013 , H03K2005/00143
摘要： A process, voltage, and temperature (PVT) compensation circuit and a method of continuously generating a delay measure are provided. The compensation circuit includes two delay lines, each delay line providing a delay output. The two delay lines may each include a number of delay elements, which in turn may include one or more current-starved inverters. The number of delay lines may differ between the two delay lines. The delay outputs arc provided to a combining circuit that determines an offset pulse based on the two delay outputs and then averages the voltage of the offset pulse to determine a delay measure. The delay measure may be one or more currents or voltages indicating an amount of PVT compensation to apply to input or output signals of an application circuit, such as a memory-bus driver, dynamic random access memory (DRAM), a synchronous DRAM, a processor or other clocked circuit.

9. 发明授权

EP1791256B1 Clock signal output circuit 有权
标题翻译：时钟信号输出电路
公开(公告)号：EP1791256B1
公开(公告)日：2010-11-17
申请号：EP06024662.6
申请日：2006-11-28
申请人： DENSO CORPORATION
发明人： Ohta, Norikazu, c/o K.K. Toyota Chuo Kenkyusho , Ohira, Yoshie, c/o K.K. Toyota Chuo Kenkyusho , Makino, Yasuaki , Ariyoshi, Hiromi
IPC分类号： H03K3/03
CPC分类号： H03K3/354 , H03K3/0315 , H03K2005/0013 , H03K2005/00143 , H03K2005/00169

10. 发明公开

EP0390226A1 Jitter absorption circuit 失效
标题翻译： Absorptionsschaltung des Zitterns。
公开(公告)号：EP0390226A1
公开(公告)日：1990-10-03
申请号：EP90108904.5
申请日：1985-07-30
申请人： YAMAHA CORPORATION
发明人： Tomisawa, Norio
IPC分类号： G11B20/10 , G11B20/22 , H04N9/89 , H04N5/95
CPC分类号： H03K5/133 , G11B20/10009 , G11B20/225 , H03H11/265 , H03K3/0315 , H03K7/06 , H03K7/08 , H03K2005/00065 , H03K2005/00097 , H03K2005/00143 , H03K2005/00195
摘要： A jitter absorption circuit comprises a variable delay device using CMOS gate circuit means for delaying the reproduced signal of a compact disc and a circuit (200,202,203,204,207) for reproducing time axis data of said reproduced signal. The delay time in said signal delay device (184) is controlled by an output signal of said time axis data reproducing circuit in such a manner that the delay time is prolonged when the reproduced signal is ahead of a reference position in the time axis direction and the delay time is shortened when the reproduced signal is delayed from the reference position whereby jitter in the reproduced signal is absorbed.
摘要翻译：抖动吸收电路包括使用用于延迟光盘的再现信号的CMOS门电路装置的可变延迟装置和用于再现所述再现信号的时间轴数据的电路（200,202,203,204,207）。所述信号延迟装置（184）中的延迟时间由所述时间轴数据再现电路的输出信号控制，使得当再现信号在时间轴方向上超过基准位置时延迟时间延长，并且当再现信号从参考位置延迟时，延迟时间缩短，从而吸收再现信号中的抖动。

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