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1. 发明公开

EP4379720A1 SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF 审中-公开
公开(公告)号：EP4379720A1
公开(公告)日：2024-06-05
申请号：EP23196181.4
申请日：2023-09-08
申请人： Samsung Electronics Co., Ltd.
发明人： JO, Byoungkon , OH, Gyesik , IM, Wangyong , KIM, Duk Sung , CHOI, Jangseok
IPC分类号： G11C7/10 , G11C11/4076 , G11C11/4093 , G11C11/4096
CPC分类号： G11C11/4096 , G11C11/4093 , G11C11/4076 , G11C7/1075 , G11C5/025
摘要： A semiconductor memory device (1200), includes, a cell array (1210) including a plurality of memory banks (1210a, 1210b, 1210c, 1210d), a command decoder (1230) configured to decode a read/write command (R&W), a read command (R), and a write command (W) that are input from outside of the semiconductor memory device, an address decoder (1220) receiving a read address (R_ADD) and a write address (W_ADD), an input receiver (1290) configured to transmit write data (W_DATA) input through a write data pad (WDQ) to a global input/output driver (GIODRV) of a memory bank corresponding to the write address (W_ADD), and an output driver (1295) configured to transmit read data (R_DATA) output from an input/output sense amplifier (IOSA) of a memory bank corresponding to the read address (R_ADD) to a read data pad (RDQ), wherein the write data (W_DATA) is input via the write data pad (WDQ) in a single data rate method and transmitted to the global input/output driver (GIODRV) without deserialization processing, and the read data (R_DATA) is transmitted from the input/output sense amplifier (IOSA) to the read data pad (RDQ) without serialization processing. In some embodiments, the semiconductor memory device (1200) is electrically and physically coupled to a central processing unit (1100) by hybrid copper bonding (1006).

2. 发明授权

EP2965316B1 APPARATUSES AND METHODS FOR PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY 有权
公开(公告)号：EP2965316B1
公开(公告)日：2018-11-28
申请号：EP14760332.8
申请日：2014-02-20
申请人： Micron Technology, Inc.
发明人： MANNING, Troy A.
IPC分类号： G11C7/06 , G11C7/10 , G11C11/4096 , G11C11/4091 , G11C11/4094 , G11C11/4093 , G11C15/00 , G06F15/78
CPC分类号： G11C7/065 , G06F12/00 , G11C7/1006 , G11C7/1051 , G11C11/4091 , G11C11/4093 , G11C11/4094 , G11C11/4096 , G11C15/00
摘要： The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry is configured to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input. The sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access.

3. 发明公开

EP3284089A1 LOW POWER AND HIGH SPEED SENSE AMPLIFIER LATCH WITH LOW POWER RAIL-TO-RAIL INPUT COMMON MODE RANGE 审中-公开
标题翻译：低功率和高速感应放大器与低功率轨到轨输入通用模式范围锁定
公开(公告)号：EP3284089A1
公开(公告)日：2018-02-21
申请号：EP16780406.1
申请日：2016-02-10
申请人： INTEL Corporation
发明人： DUDULWAR, Pankaj Vinayak , BANDI, Chenchu Punnarao , TEH, Lip Khoon , TAN, Tat Hin
IPC分类号： G11C7/06 , G11C5/14
CPC分类号： H04L7/0037 , G11C7/062 , G11C7/065 , G11C7/08 , G11C7/10 , G11C7/1057 , G11C7/106 , G11C7/1078 , G11C7/1084 , G11C7/1087 , G11C11/165 , G11C11/4093 , G11C11/4096 , H03L7/0812 , H04L27/0002
摘要： Described is an apparatus which comprises: an input sensing stage for sensing an input signal relative to another signal; a decision making circuit, coupled to the input sensing stage, for determining whether the input signal is a logic low or a logic high; and a power management circuit, coupled to the input sensing stage and the decision making circuit, which is operable to monitor a state of the decision making circuit and to disable the input sensing stage according to the monitored state. Described is an apparatus which comprises: a decision making circuit integrated with an input sensing stage, wherein the decision making circuit is operable to pre-charge its internal nodes during a phase of the clock signal; and a latching circuit to latch an output of the decision making circuit.

4. 发明公开

EP3268965A1 APPARATUSES AND METHODS FOR DATA MOVEMENT 审中-公开
标题翻译：数据移动的装置和方法
公开(公告)号：EP3268965A1
公开(公告)日：2018-01-17
申请号：EP16762198.6
申请日：2016-03-04
申请人： Micron Technology, Inc.
发明人： HUSH, Glen E. , PINNEY, David L.
IPC分类号： G11C7/06 , G11C7/10
CPC分类号： G06F3/0647 , G06F3/0604 , G06F3/0673 , G11C5/025 , G11C7/06 , G11C7/065 , G11C7/1006 , G11C7/1012 , G11C11/4087 , G11C11/4091 , G11C11/4093 , G11C11/4094 , G11C11/4096 , G11C11/4097 , G11C2207/10 , G11C2207/104
摘要： The present disclosure includes apparatuses and methods for data movement. An example apparatus comprises a memory device. The memory device includes an array of memory cells and sensing circuitry coupled to the array via a plurality of sense lines. The sensing circuitry includes a sense amplifier and a compute component coupled to a sense line and configured to implement operations. A controller in the memory device is configured to couple to the array and sensing circuitry. A shared I/O line in the memory device is configured to couple a source location and a destination location.

5. 发明公开

EP3243137A1 GENERATING AND EXECUTING A CONTROL FLOW 有权
标题翻译：生成和执行控制流程
公开(公告)号：EP3243137A1
公开(公告)日：2017-11-15
申请号：EP16735388.7
申请日：2016-01-07
申请人： Micron Technology, Inc.
发明人： WHEELER, Kyle B. , MURPHY, Richard C. , MANNING, Troy A. , KLEIN, Dean A.
IPC分类号： G06F12/02 , G06F9/30 , G11C7/06
CPC分类号： G06F9/3877 , G06F15/7821 , G11C7/06 , G11C7/065 , G11C7/1006 , G11C7/1036 , G11C11/4087 , G11C11/4096
摘要： Examples of the present disclosure provide apparatuses and methods related to generating and executing a control flow. An example apparatus can include a first device configured to generate control flow instructions, and a second device including an array of memory cells, an execution unit to execute the control flow instructions, and a controller configured to control an execution of the control flow instructions on data stored in the array.

6. 发明授权

EP2278474B8 Method and apparatus for coordinating memory operations among diversely-located memory components 有权
公开(公告)号：EP2278474B8
公开(公告)日：2015-10-21
申请号：EP10178677.0
申请日：2002-04-23
申请人： Rambus Inc.
发明人： Ware, Frederick , Tsern, Ely K. , Perego, Richard E. , Hampel, Craig E.
IPC分类号： G06F13/16
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A specific address and control bus, and a data bus (108), are connected to a memory controller (102) and a memory module (103). The data bus using differential signaling, has symbol time lesser than specific address and control bus symbol time.

7. 发明授权

EP2273376B1 Method and apparatus for coordinating memory operations among diversely-located memory components 有权
标题翻译：用于协调不同布置的存储元件之间的存储器操作的方法和装置
公开(公告)号：EP2273376B1
公开(公告)日：2014-10-29
申请号：EP10179110.1
申请日：2002-04-23
申请人： Rambus Inc.
发明人： Ware, Frederick , Tsern,, Ely K. , Perego, Richard E. , Hampel, Craig E.
IPC分类号： G06F13/16
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A specific address and control bus, and a data bus (108), are connected to a memory controller (102) and a memory module (103). The data bus using differential signaling, has symbol time lesser than specific address and control bus symbol time.
摘要翻译：一个特定的地址和控制总线和数据总线（108）连接到存储器控制器（102）和存储器模块（103）。使用差分信令数据总线，具有符号时间比特定地址和控制总线符号时间较少。

8. 发明公开

EP2353058A4 MESOCHRONOUS SIGNALING SYSTEM WITH CLOCK-STOPPED LOW POWER MODE 有权转让
标题翻译：低功耗模式TAKTGESTEUERTEM MESOCHRONES信令系统
公开(公告)号：EP2353058A4
公开(公告)日：2014-04-09
申请号：EP09837752
申请日：2009-07-09
申请人： RAMBUS INC
发明人： WARE FREDERICK A , PALMER ROBERT E , POULTON JOHN W , FULLER ANDREW M
IPC分类号： G06F1/04 , G06F1/32 , G06F12/00 , G06F13/16
CPC分类号： G06F1/3237 , G06F1/12 , G06F1/3225 , G06F1/324 , G06F3/0604 , G06F3/0625 , G06F3/0629 , G06F3/0673 , G06F9/3836 , G06F12/0857 , G06F13/1689 , G06F13/36 , G06F2201/88 , G11C7/04 , G11C7/10 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C7/225 , G11C11/4076 , G11C11/4096 , G11C2207/2254 , Y02B60/1228 , Y02D10/14
摘要： In a low-power signaling system, an integrated circuit device includes an open loop- clock distribution circuit and a transmit circuit that cooperate to enable highspeed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.

9. 发明公开

EP2499667A4 PARALLELIZED CHECK POINTING USING MATs AND THROUGH SILICON VIAs (TSVs) 有权转让
标题翻译：平行检查与垫和硅内孔
公开(公告)号：EP2499667A4
公开(公告)日：2014-03-05
申请号：EP09851339
申请日：2009-11-13
申请人： HEWLETT PACKARD DEVELOPMENT CO
发明人： MURALIMANOHAR NAVEEN , JOUPPI NORMAN PAUL
IPC分类号： H01L23/043 , G06F11/14 , G11C5/02 , G11C5/04 , G11C7/10 , G11C8/12 , G11C11/408 , G11C11/4096 , H01L25/065
CPC分类号： G11C5/02 , G11C5/04 , G11C7/1069 , G11C7/1078 , G11C8/12 , G11C11/4087 , G11C11/4096 , H01L25/0657 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A system and method that includes a memory die, residing on a stacked memory, which is organized into a plurality of mats that include data. The system and method also includes an additional memory die, residing on the stacked memory, that is organized into an additional plurality of mats and connected to the memory die by a Through Silicon Vias (TSVs), the data to be transmitted along the TSVs.

10. 发明公开

EP2615611A3 Multi-mode memory device and method 有权
标题翻译：多模式存储设备和方法
公开(公告)号：EP2615611A3
公开(公告)日：2013-07-31
申请号：EP13157772.8
申请日：2009-06-10
申请人： Micron Technology, Inc.
发明人： Jeddeloh, Joseph, M.
IPC分类号： G11C11/4093 , G11C11/4096 , G11C11/409 , G11C11/408 , G06F13/00 , G11C5/02
CPC分类号： G11C11/408 , G06F13/1694 , G11C5/02 , G11C11/4093 , G11C11/4096
摘要： Memory device systems, systems and methods are disclosed, such as those involving a plurality of stacked memory device dice and a logic die connected to each other through a plurality of conductors. The logic die serves, for example, as a memory interface device to a memory access device, such as a processor. The logic die can include a command register that allows selective operation in either of two modes. In a direct mode, conventional command signals as well as row and column address signals are applied to the logic die, and the logic die can essentially couple these signals directly to the memory device dice. In an indirect mode, a packet containing a command and a composite address are applied to the logic die, and the logic die can decode the command and composite address to apply conventional command signals as well as row and column address signals to the memory device dice.
摘要翻译：公开了存储器件系统，系统和方法，诸如涉及通过多个导体相互连接的多个堆叠的存储器件裸片和逻辑裸片的存储器件系统，系统和方法。逻辑管芯例如用作存储器接口设备到存储器访问设备，例如处理器。逻辑裸片可以包括允许以两种模式中的任一种进行选择性操作的命令寄存器。在直接模式中，常规命令信号以及行和列地址信号被施加到逻辑裸片，并且逻辑裸片可以基本上将这些信号直接耦合到存储器件裸片。在间接模式中，包含命令和复合地址的分组被施加到逻辑管芯，并且逻辑管芯可以解码命令和复合地址以将常规命令信号以及行和列地址信号施加到存储器设备管芯。

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