专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

EP2605121B1 Systems and methods for handling out of order reporting in a storage device 有权
标题翻译：系统和用于在存储设备搬运他们的订单以外的报告方法
公开(公告)号：EP2605121B1
公开(公告)日：2016-09-21
申请号：EP12192221.5
申请日：2012-11-12
申请人： LSI Corporation
发明人： Yang, Shaohua , Zhang, Fan , Han, Yang , Wu, Xuebin
IPC分类号： G06F3/06 , G11B20/10 , G11B20/12 , G11B20/18
CPC分类号： G06F7/24 , G06F3/0604 , G06F3/0611 , G06F3/0659 , G06F3/0674 , G11B20/10 , G11B20/12 , G11B20/18

2. 发明公开

EP2767899A3 Non-volatile memory channel control using a general purpose programmable processor in combination with a low level programmable sequencer 审中-公开
标题翻译：组合使用可编程处理器与可编程序控制的低级别的非易失性存储器信道控制器
公开(公告)号：EP2767899A3
公开(公告)日：2016-08-17
申请号：EP14154095.5
申请日：2014-02-06
申请人： LSI Corporation
发明人： Brewer, Christopher , Cohen, Earl T.
IPC分类号： G06F9/30 , G06F9/26 , G06F3/06 , G06F9/38 , G06F12/02 , G06F13/16 , G06F13/38 , G11C5/04
CPC分类号： G06F3/0613 , G06F3/0659 , G06F3/0688 , G06F9/38 , G06F12/0246 , G06F13/1694 , G06F13/385 , G11C5/04
摘要： A system includes a control processor, a non-volatile memory device interface, and a micro-sequencer. The control processor may be configured to receive commands and send responses via a command interface. The non-volatile memory device interface may be configured to couple the system to one or more non-volatile memory devices. The micro-sequencer is generally coupled to (i) the control processor and (ii) the non-volatile memory device interface. The micro-sequencer includes a control store readable by the micro-sequencer and writable by the control processor. In response to receiving a particular one of the commands, the control processor is enabled to cause the micro-sequencer to begin executing at a location in the control store according to the particular command and the micro-sequencer is enabled to perform at least a portion of the particular command according to a protocol of the one or more non-volatile memory devices coupled to the non-volatile memory device interface.

3. 发明公开

EP2637171A3 Storage device having write signal with multiple-slope data transition 审中-公开
标题翻译：与具有多个梯度数据传送写入信号的存储器设备
公开(公告)号：EP2637171A3
公开(公告)日：2015-10-14
申请号：EP13158612.5
申请日：2013-03-11
申请人： LSI Corporation
发明人： Livshitz, Boris , Gleason, Jeffrey A. , Goldberg, Jason S. , Mazur, Paul , Rabe, Cameron C.
IPC分类号： G11B20/10 , G11B5/02 , G11B5/09
CPC分类号： G11B20/10009 , G11B5/02
摘要： A hard disk drive or other disk-based storage device comprises a storage disk, a read/write head configured to read data from and write data to the disk, and control circuitry coupled to or otherwise associated with the read/write head. The control circuitry comprises a write driver configured to generate a write signal for data to be written to the storage disk, and a ultiple-slope transition controller associated with the write driver and configured to control a data transition in the write signal such that the data transition comprises at least two different segments each having a different slope, with the transition controller comprising separate slope control mechanisms for each of the segments. By way of example, the data transition may comprise a dual-slope transition having first and second segments arranged sequentially between a start point and an end point of the data transition, with the slope of the first segment being than or less than the slope of the second segment.

4. 发明公开

EP2750018A3 Non-volatile memory program failure recovery via redundant arrays 审中-公开
标题翻译：非易失性存储器阵列的冗余方案的恢复
公开(公告)号：EP2750018A3
公开(公告)日：2015-05-20
申请号：EP13196184.9
申请日：2013-12-09
申请人： LSI Corporation
发明人： Werner, Jeremy Isaac Nathaniel , Cohen, Earl T.
IPC分类号： G06F3/06 , G06F11/10 , G06F11/20
CPC分类号： G06F11/1068 , G06F3/061 , G06F3/0619 , G06F3/064 , G06F3/0656 , G06F3/0679 , G06F3/0688 , G06F11/1044 , G06F11/108 , G06F11/2056 , G11C29/52
摘要： Non-volatile memory program failure recovery via redundant arrays enables higher programming bandwidth and/or reduced latency in some storage subsystem implementations, e.g. a solid-state disk. Data to program N portions of a plurality of non-volatile memories is received at a non-volatile memory controller. The data includes particular data to program a particular one of the N portions. The particular data is stored in an allocated buffer associated with the non-volatile memory controller. Programming the particular data to a particular one of the non-volatile memories is begun. Redundancy information sufficient to recover from failures of M of the N portions is updated. The allocated buffer is freed. At least one of the storing, the beginning programming, the updating, and the freeing is in response to the receiving of the particular data. The freeing is prior to the particular non-volatile memory completing the programming.

5. 发明公开

EP2779468A9 Min-sum based hybrid non-binary low-density parity check (LDPC) decoder 审中-公开
标题翻译：最小和基于混合解码器的非二进制低密度奇偶校验码
公开(公告)号：EP2779468A9
公开(公告)日：2014-12-24
申请号：EP14151571.8
申请日：2014-01-17
申请人： LSI Corporation
发明人： Wang, Chung-Li , Li, Zongwang , Li, Shu , Zhang, Fan , Yang, Shaohua
IPC分类号： H03M13/11
CPC分类号： H03M13/13 , H03M13/1122 , H03M13/1125 , H03M13/1171 , H03M13/6583
摘要： Systems, methods, devices, circuits for a min-sum based hybrid non-binary low density parity check decoder are disclosed. A data processing system (200) is disclosed including an apparatus for decoding data having a variable node processor (202) and a check node processor (204). The variable node processor is operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages. The check node processor is operable to generate the check node to variable node messages and to calculate checksums based on variable node to check node messages. The variable node processor and the check node processor operate on different Galois fields GF(q) and GF(p), which requires transformations (242, 262) of the messages exchanged between the check and variable node processors from GF(q) to GF(p) and vice versa.

6. 发明授权

EP2503347B9 Low-power and area-efficient scan cell for integrated circuit testing 有权
标题翻译：用于集成电路测试低电流和有效面积扫描单元
公开(公告)号：EP2503347B9
公开(公告)日：2014-12-17
申请号：EP12160993.7
申请日：2012-03-23
申请人： LSI Corporation
发明人： Tekumalla, Ramesh C , Kumar, Priyesh , Krishnamoorthy, Prakash , Madhani, Parag
IPC分类号： G01R31/3185
CPC分类号： G01R31/318541 , G01R31/318575

7. 发明公开

EP2779490A2 Transmit reference signal cleanup within a synchronous network application 审中-公开
标题翻译： Säuberungeines Sendereferenzsignals innerhalb einer同步Netzwerkanwendung
公开(公告)号：EP2779490A2
公开(公告)日：2014-09-17
申请号：EP14157543.1
申请日：2014-03-03
申请人： LSI Corporation
发明人： Nemawarkar, Shashank , Beers, Gregory E. , Bedrosian, Paul S. , Bordogna, Mark A. , Wan, Hong
IPC分类号： H04J3/06 , H03L7/00
CPC分类号： H04L7/0331 , H04J3/0688 , H04J3/0697
摘要： A network processor is described that includes a network reference clock processor module for providing an at least substantially low-jitter, low-wander reference signal. In one or more embodiments, the network reference clock processor module includes a digital phase locked loop configured to at least substantially attenuate a wander noise portion from a reference signal. The network reference clock processor module also includes an analog phase locked loop communicatively coupled to the digital phase locked loop and configured to receive the reference signal from the digital phase locked loop. The analog phase locked loop is configured to attenuate a jitter noise portion having a first frequency characteristic from the reference signal and to provide the reference signal to a transceiver communicatively coupled to the analog phase locked loop. The transceiver is configured to attenuate a jitter noise portion having a second frequency characteristic from the reference signal.
摘要翻译：描述了一种网络处理器，其包括用于提供至少基本上低抖动，低漂移参考信号的网络参考时钟处理器模块。在一个或多个实施例中，网络参考时钟处理器模块包括被配置为从参考信号至少基本上衰减漂移噪声部分的数字锁相环。网络参考时钟处理器模块还包括通信地耦合到数字锁相环并被配置为从数字锁相环接收参考信号的模拟锁相环。模拟锁相环被配置为从参考信号衰减具有第一频率特性的抖动噪声部分，并将参考信号提供给通信地耦合到模拟锁相环的收发器。收发器被配置为从参考信号衰减具有第二频率特性的抖动噪声部分。

8. 发明公开

EP2779459A1 Biased bang-bang phase detector for clock and data recovery 审中-公开
标题翻译： Vorgespannter Zweipunkt-PhasendetektorfürTakt- undDatenrückgewinnung
公开(公告)号：EP2779459A1
公开(公告)日：2014-09-17
申请号：EP14157040.8
申请日：2014-02-27
申请人： LSI Corporation
发明人： Malipatil, Amaresh V. , Srinivasa, Sunil , Healey, Adam B. , Aziz, Pervez M.
IPC分类号： H03L7/08 , H03L7/089 , H03L7/091 , H04L7/033
CPC分类号： H03L7/00 , H03L7/0807 , H03L7/089 , H03L7/091 , H04L7/033
摘要： An apparatus includes a plurality of phase detector circuits and a summing circuit. Each of the plurality of phase detector circuits may be configured to generate a phase up signal and a phase down signal in response to a respective pair of data samples and intervening transition sample. The summing circuit may be configured to generate an adjustment signal in response to the phase up and phase down signals of the plurality of phase detector circuits. A sum of the phase up signals and a sum of the phase down signals are weighted to provide a bias to a phase adjustment.
摘要翻译：一种装置包括多个相位检测器电路和一个求和电路。多个相位检测器电路中的每一个可以被配置为响应于相应的数据样本对和中间转换样本而产生相位上升信号和相位降低信号。求和电路可以被配置为响应于多个相位检测器电路的相位上升和下降信号而产生调整信号。相位相加信号和相位下降信号之和被加权，以向相位调整提供偏置。

9. 发明公开

EP2778933A1 System, method and computer-readable medium for managing a cache store to achieve improved cache ramp-up across system reboots 审中-公开
标题翻译：系统，方法和高速缓冲存储器管理的计算机可读介质，以实现对系统重新引导的改进的高速缓存启动时间
公开(公告)号：EP2778933A1
公开(公告)日：2014-09-17
申请号：EP14158963.0
申请日：2014-03-11
申请人： LSI Corporation
发明人： Shivashankaraiah, Vinay Bangalore , Parameswaran, Subramanian , Ish, Mark
IPC分类号： G06F12/08
CPC分类号： G06F12/0842 , G06F12/0871 , G06F2212/222 , G06F2212/225 , G06F2212/282 , G06F2212/311
摘要： A cache controller having a cache store and associated with a storage system maintains information stored in the cache store across a reboot of the cache controller. The cache controller communicates with a host computer system and a data storage system. The cache controller partitions the cache memory to include a metadata portion and log portion. A separate portion is used for cached data elements. The cache controller maintains a copy of the metadata in a separate memory accessible to the host computer system. Data is written to the cache store hen the metadata log reaches its capacity. Upon a reboot, metadata is copied back to the host computer system and the metadata log is traversed to copy additional changes in the cache that have not been saved to the data storage system.
摘要翻译：具有高速缓存存储和与存储系统相关联的高速缓冲存储器控制器保持跨越高速缓冲存储器控制器的重启存储在缓存中存储信息。高速缓存控制器与主机计算机系统和数据存储系统进行通信。高速缓存控制器分割高速缓冲存储器包括元数据部分和日志部分。一个单独的部分被用于高速缓存的数据元素。高速缓存控制器保持元数据的副本，在向主计算机系统可访问的单独的存储器中。数据被写入到高速缓存存储母鸡中的元数据日志达到其容量。一旦重新启动，元数据被复制回到主计算机系统和元数据日志运行到复制缓存中的其他更改thathave没有被保存到数据存储系统。

10. 发明公开

EP2772032A1 PROCESSOR HAVING INSTRUCTION SET WITH USER-DEFINED NON-LINEAR FUNCTIONS FOR DIGITAL PRE-DISTORTION (DPD) AND OTHER NON-LINEAR APPLICATIONS 审中-公开
标题翻译：带有定制的非线性函数数字预失真（DPD）和其他非线性应用指令集处理器
公开(公告)号：EP2772032A1
公开(公告)日：2014-09-03
申请号：EP12843512.0
申请日：2012-10-26
申请人： LSI Corporation
发明人： AZADET, Kameran , YU, Meng-Lin , PINAULT, Steven, C. , WILLIAMS, Joseph , MOLINA, Albert
IPC分类号： H04L25/02
CPC分类号： G06F9/3001 , G06F5/01 , G06F9/30036 , G06F17/15 , H03F1/0288 , H03F1/3241 , H03F1/3258 , H03F3/189 , H03F3/24 , H03F2200/336 , H03F2201/3209 , H03F2201/3212 , H03F2201/3224 , H03F2201/3233 , H03H17/06 , H03M3/30 , H04B1/0003 , H04B1/0475 , H04B1/62 , H04B2001/0408 , H04L1/0054 , H04L25/02 , H04L25/03 , H04L25/03178 , H04L25/03216 , H04L25/4917 , H04L27/2334
摘要： A processor is provided having an instruction set with user-defined non-linear functions for digital pre-distortion (DPD) and other non-linear applications. A signal processing function, such as DPD, is implemented in software by obtaining at least one software instruction that performs at least one non-linear function for an input value, x, wherein the at least one non-linear function comprises at least one user-specified parameter; in response to at least one of the software instructions for at least one non-linear function having at least one user-specified parameter, performing the following steps: invoking at least one functional unit that implements the at least one software instruction to apply the non-linear function to the input value, x; and generating an output corresponding to the non-linear function for the input value, x. The user-specified parameter can optionally be loaded from memory into at least one register.
摘要翻译：使用非对称的脉冲被提供波峰因子降低（CFR）的技术。甲振幅因数减小方法包括：获得一个或多个数据采样; 检测所述一个或多个数据样本中的至少一个峰; 通过向非对称消除脉冲到至少一个检测到的峰值对所述至少一个检测到的峰峰值抵消; 和提供处理的一个或多个数据采样的版本。非对称抵消脉冲产生，例如，由最小相位滤波器，并且具有大致最小群延迟。具有峰值再生长相关联的新的峰基本上只介绍非对称消除脉冲的一侧上。该方法可任选地在量为大于或等于通过倒带基本上不对称消除脉冲的群延迟，以解决预游标的有限数量并可以存在于不对称消除脉冲。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式