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1. 发明授权

EP2503347B9 Low-power and area-efficient scan cell for integrated circuit testing 有权
标题翻译：用于集成电路测试低电流和有效面积扫描单元
公开(公告)号：EP2503347B9
公开(公告)日：2014-12-17
申请号：EP12160993.7
申请日：2012-03-23
申请人： LSI Corporation
发明人： Tekumalla, Ramesh C , Kumar, Priyesh , Krishnamoorthy, Prakash , Madhani, Parag
IPC分类号： G01R31/3185
CPC分类号： G01R31/318541 , G01R31/318575

2. 发明授权

EP2503347B1 Low-power and area-efficient scan cell for integrated circuit testing 有权
标题翻译：用于集成电路测试的低功耗和面积效率的扫描单元
公开(公告)号：EP2503347B1
公开(公告)日：2014-08-13
申请号：EP12160993.7
申请日：2012-03-23
申请人： LSI Corporation
发明人： Tekumalla, Ramesh C , Kumar, Priyesh , Krishnamoorthy, Prakash , Madhani, Parag
IPC分类号： G01R31/3185
CPC分类号： G01R31/318541 , G01R31/318575

3. 发明公开

EP2587273A1 Dynamic clock domain bypass for scan chains 审中-公开
标题翻译： Dynamische TaktbereichsumgebungfürAbtastketten
公开(公告)号：EP2587273A1
公开(公告)日：2013-05-01
申请号：EP12188947.1
申请日：2012-10-18
申请人： LSI Corporation
发明人： Tekumalla, Ramesh C. , Kumar, Priyesh
IPC分类号： G01R31/3185
CPC分类号： G01R31/318558 , G01R31/318594
摘要： An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of sub-chains associated with respective distinct clock domains, and clock domain bypass circuitry configured to selectively bypass one or more of the sub-chains. The scan chain is configurable in a scan shift mode of operation to form a serial shift register that includes fewer than all of the sub-chains with at least a remaining one of the sub-chains being bypassed by the clock domain bypass circuitry so as to not be part of the serial shift register in the scan shift mode. By selectively bypassing portions of the scan chain associated with particular clock domains, the clock domain bypass circuitry serves to reduce test time and power consumption during scan testing.
摘要翻译：集成电路包括扫描测试电路和经受使用扫描测试电路的测试的附加电路。扫描测试电路包括至少一个扫描链，其具有与相应的不同时钟域相关联的多个子链，以及被配置为选择性地绕过一个或多个子链的时钟域旁路电路。扫描链可以在扫描移动模式中被配置以形成串行移位寄存器，该串行移位寄存器包括少于所有的子链，其中至少一个子链被时钟域旁路电路旁路，以便不是扫描移位模式下串行移位寄存器的一部分。通过选择性地绕过与特定时钟域相关联的扫描链的部分，时钟域旁路电路用于在扫描测试期间减少测试时间和功耗。

4. 发明公开

EP2503347A1 Low-power and area-efficient scan cell for integrated circuit testing 有权
标题翻译： Niederstrom- und bereichswirksame-Scanzellefüreine integrierteSchaltungsprüfung
公开(公告)号：EP2503347A1
公开(公告)日：2012-09-26
申请号：EP12160993.7
申请日：2012-03-23
申请人： LSI Corporation
发明人： Tekumalla, Ramesh C , Kumar, Priyesh , Krishnamoorthy, Prakash , Madhani, Parag
IPC分类号： G01R31/3185
CPC分类号： G01R31/318541 , G01R31/318575
摘要： An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells, with the scan chain being configured to operate as a serial shift register in a scan shift mode of operation and to capture functional data from at least a portion of the additional circuitry in a functional mode of operation. At least a given one of the scan cells of the scan chain comprises output control circuitry which is configured to disable a functional data output of the scan cell in the scan shift mode of operation and to disable a scan output of the scan cell in the functional mode of operation.
摘要翻译：集成电路包括扫描测试电路和经受使用扫描测试电路的测试的附加电路。扫描测试电路包括具有多个扫描单元的至少一个扫描链，其中扫描链被配置为以扫描移动模式运行作为串行移位寄存器，并从附加的至少一部分中捕获功能数据功能运行模式的电路。扫描链的至少一个扫描单元中的一个包括输出控制电路，其被配置为在扫描移动运行模式中禁用扫描单元的功能数据输出，并禁用功能中的扫描单元的扫描输出操作模式。

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