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1. 发明授权

EP2814175B1 Pulse synthesizing circuit 有权
标题翻译： Impulssynthetisierungsschaltung
公开(公告)号：EP2814175B1
公开(公告)日：2017-02-01
申请号：EP14169999.1
申请日：2014-05-27
申请人： Onkyo Corporation
发明人： Nakanishi, Yoshinori , Kawaguchi, Tsuyoshi , Sekiya, Mamoru
IPC分类号： H03K19/0944 , H03M5/16 , H04L25/49
CPC分类号： H03K19/0002 , H03K19/09443 , H03K19/21 , H03M3/30 , H04L25/4923 , H04L25/4925

2. 发明公开

EP3075077A1 METHODS AND DEVICES FOR ERROR CORRECTION OF A SIGNAL USING DELTA SIGMA MODULATION 审中-公开
标题翻译：方法和设备的信号由Sigma-delta调制误差校正
公开(公告)号：EP3075077A1
公开(公告)日：2016-10-05
申请号：EP13898054.5
申请日：2013-11-28
申请人： Smart Energy Instruments Inc.
发明人： DIONNE, Donald Jeffrey , HOWSE, Brian Leonard William , MCCANN, Jennifer Marie
IPC分类号： H03L7/085 , H03M3/02
CPC分类号： H03L7/0994 , G06F1/02 , G06F17/10 , H03L1/00 , H03L7/081 , H03L7/095 , H03M3/30
摘要： A method for correcting long-term phase drift of a crystal oscillator in a numerically- controlled oscillator is described. The method includes determining the phase error in an oscillator signal in comparison with an external time base; delta-sigma modulating the phase error to generate a delta-sigma error bitstream; conditionally adding or subtracting an error correction step size from a phase increment value in each clock cycle based on the delta-sigma error bitstream, to create a modulated phase increment value; and adding the modulated phase increment value to a phase accumulator to generate an error-corrected output digital signal. The delta-sigma-based error correction method avoids the use of multipliers. The same delta-sigma error signal can be used in multiple numerically-controlled oscillators configured to different output frequency if driven by the same reference oscillator.

3. 发明公开

EP3008825A1 QUANTIZATION NOISE COUPLING DELTA SIGMA ADC WITH A DELAY IN THE MAIN DAC FEEDBACK 有权
标题翻译：量化噪声耦合DELTA SIGMA ADC，主DAC反馈延迟
公开(公告)号：EP3008825A1
公开(公告)日：2016-04-20
申请号：EP14738946.4
申请日：2014-06-12
申请人： Microchip Technology Incorporated
发明人： QUIQUEMPOIX, Vincent , VAUCHER, Fabien
IPC分类号： H03M3/00
CPC分类号： H03M3/39 , H03M3/30 , H03M3/368 , H03M3/496
摘要： A delta-sigma modulator has a first summing point subtracting a first feedback signal from an input signal and forwarding a result to a transfer function, a second summing point adding an output signal from said transfer function to the input signal and subtracting a second feedback signal, a first integrator receiving an output signal from the second summing point, a quantizer receiving an output signal from the integrator and generating an output bitstream, and a digital-to-analog converter receiving the bitstream, wherein the first and second feedback signal are the output signal from said digital-to-analog converter delayed by a one sample delay.
摘要翻译： Δ-Σ调制器具有从输入信号中减去第一反馈信号并将结果转发至传递函数的第一求和点，将来自所述传递函数的输出信号与输入信号相加并且将第二反馈信号，接收来自第二求和点的输出信号的第一积分器，接收来自积分器的输出信号并产生输出比特流的量化器，以及接收比特流的数模转换器，其中第一和第二反馈信号是所述数字 - 模拟转换器的输出信号延迟一个采样延迟。

4. 发明公开

EP2888818A1 CONFIGURABLE MIXED-SIGNAL SYSTEMS 审中-公开
标题翻译：配置型混合信号系统
公开(公告)号：EP2888818A1
公开(公告)日：2015-07-01
申请号：EP13756767.3
申请日：2013-08-16
申请人： Missing Link Electronics Inc.
发明人： SCHUBERT, Nils Endric , BROCK, Johannes , GRUMBEIN, Christian
IPC分类号： H03M3/02 , H03M7/30
CPC分类号： H03M3/458 , G06F17/5022 , G06F17/5054 , G06F17/5063 , H03M3/30 , H03M3/392 , H03M3/46 , H03M7/3015
摘要： An electronic system includes a configurable processing device. The configurable processing device includes a processor that performs digital processing, a first input that receives digital signal, a first output that sends digital signal and a converter that converts between analog and digital signals. The converter includes a delta-sigma modulator.

5. 发明公开

EP2863547A3 Multi-stage noise shaping analog-to-digital converter 审中-公开
标题翻译：多级噪声整形模拟到数字转换器
公开(公告)号：EP2863547A3
公开(公告)日：2015-06-17
申请号：EP14188331.4
申请日：2014-10-09
申请人： Analog Devices Global
发明人： Dong, Yunzhi , Shibata, Hajime , Yang, Wenhua , Schreier, Richard
IPC分类号： H03M3/04
CPC分类号： H03M3/344 , H03M1/00 , H03M1/12 , H03M1/144 , H03M1/145 , H03M3/30 , H03M3/416 , H04L25/067 , H04M1/72519
摘要： The present disclosure describes an improved multi-stage noise shaping (MASH) analogto-digital converter (ADC) for converting an analog input signal to a digital output signal. In particular, a full delta-sigma (Δ∑) modulator is provided at the front-end of the MASH ADC, and another full Δ∑ modulator is provided at the back-end of the MASH ADC. The front-end Δ∑ modulator digitizes an analog input signal, and the back-end Δ∑ modulator digitizes an error between the output of the front-end Δ∑ modulator and the (original) analog input signal. In this configuration where the back-end modulator digitizes the error of the (full) front-end modulator, some design constraints of the front-end are relaxed. These design constraints include thermal noise, digital noise cancellation filter complexity (the quantization noise of the front-end is already shaped by the noise transfer function of the front-end), and/or non-linearity.

6. 发明公开

EP2797236A3 Zeitkontinuierlicher Delta-Sigma-Modulator 有权转让
标题翻译：连续时间Σ-Δ调制器
公开(公告)号：EP2797236A3
公开(公告)日：2015-03-04
申请号：EP14001368.1
申请日：2014-04-15
申请人： Micronas GmbH
发明人： Muthers, David
IPC分类号： H03M3/02 , H03M3/04
CPC分类号： H03M3/30 , H03M3/322 , H03M3/458
摘要： Zeitkontinuierlicher Delta-Sigma-Modulator,
- mit einem Integrator (Int) und einem mit einer Taktfrequenz (f clk ) getakteten Komparator (Comp), die in einer Rückkopplungsschleife verbunden sind,
- mit einer Spannungsquelle (Cal), die mit dem Komparator (Comp) zum Anlegen einer Schwellspannung (V th ) an den Komparator (Comp) verbunden ist,
- bei dem eine Integrationszeitkonstante des Integrators (Int) einen ersten Widerstand (R 1 ) und eine erste Kapazität (C 1 ) aufweist,
- bei dem die Spannungsquelle (Cal) einen zweiten Widerstand (R 2 ) und eine zweite Kapazität (C 2 ) zur Einstellung der Schwellspannung (V th ) aufweist,
- bei dem der erste Widerstand (R 1 ) und der zweite Widerstand (R 2 ) Bestandteil einer Widerstandspaarungsstruktur sind, und
- bei dem die erste Kapazität (C 1 ) und die zweite Kapazität (C 2 ) Bestandteil einer Kapazitätspaarungsstruktur sind.

7. 发明公开

EP2814180A1 Signal modulation circuit 审中-公开
标题翻译： Signalmodulationsschaltung
公开(公告)号：EP2814180A1
公开(公告)日：2014-12-17
申请号：EP14170009.6
申请日：2014-05-27
申请人： Onkyo Corporation
发明人： Nakanishi, Yoshinori , Kawaguchi, Tsuyoshi , Sekiya, Mamoru
IPC分类号： H03M3/02
CPC分类号： H03M3/37 , G11B20/10009 , G11B2020/00065 , H03M3/30 , H03M3/346 , H03M3/348 , H03M3/424 , H04R3/00
摘要： Provided is a modulation circuit that can correct an output state in real time and reliably modulate an input signal to output the modulated signal. The signal modulation circuit includes a subtracter, an integrator, a chopper circuit, a frequency divider, and a D-type flip-flop. A delay circuit of a sigma delta modulation circuit is not provided to a feedback circuit, and a signal is delayed and quantized in the D-type flip-flop. The chopper circuit inserts a zero level at timing synchronized with a clock signal, so that pulse density modulation is performed.
摘要翻译：提供了可以实时校正输出状态并可靠地调制输入信号以输出调制信号的调制电路。信号调制电路包括减法器，积分器，斩波电路，分频器和D型触发器。 Σ-Δ调制电路的延迟电路不提供给反馈电路，并在D型触发器中延迟和量化信号。斩波电路在与时钟信号同步的定时插入零电平，从而执行脉冲密度调制。

8. 发明公开

EP2814175A1 Pulse synthesizing circuit 有权
标题翻译：脉冲合成电路
公开(公告)号：EP2814175A1
公开(公告)日：2014-12-17
申请号：EP14169999.1
申请日：2014-05-27
申请人： Onkyo Corporation
发明人： Nakanishi, Yoshinori , Kawaguchi, Tsuyoshi , Sekiya, Mamoru
IPC分类号： H03K19/0944 , H03M5/16 , H04L25/49
CPC分类号： H03K19/0002 , H03K19/09443 , H03K19/21 , H03M3/30 , H04L25/4923 , H04L25/4925
摘要： A circuit having versatility synthesizes one-bit digital signals to generate a ternary signal. The pulse synthesizing circuit synthesizes one-bit digital signals from two DFFs to generate a ternary signal. The pulse synthesizing circuit has a first NOR gate, a second NOR gate, a third NOR gate, and three switches. The first switch is connected to a first electric potential, the second switch is connected to a second electric potential, and the third switch is connected to a third electric potential. The first to third switches are turned on/off according to logical values of the signals from the two DFFs, and any of the first electric potential, the second electric potential, and the third electric potential is set as an output potential so that a ternary signal is generated.
摘要翻译：具有多功能性的电路合成一位数字信号以生成三元信号。脉冲合成电路合成来自两个DFF的一位数字信号以产生三元信号。脉冲合成电路具有第一或非门，第二或非门，第三或非门以及三个开关。第一开关连接到第一电位，第二开关连接到第二电位，并且第三开关连接到第三电位。第一至第三开关根据来自两个DFF的信号的逻辑值被导通/截止，并且第一电位，第二电位和第三电位中的任一个被设置为输出电位，使得三元信号被生成。

9. 发明公开

EP2809007A2 Electric signal conversion 有权转让
标题翻译： Umwandlung eines elektrischen信号
公开(公告)号：EP2809007A2
公开(公告)日：2014-12-03
申请号：EP14168345.8
申请日：2014-05-14
申请人： Analog Devices Technology
发明人： Caldwell, Trevor Clifford , Schreier, Richard E. , Alldred, David , Yang, Wenhua W.
IPC分类号： H03M1/06 , H03M1/36 , H03M1/74
CPC分类号： H03M1/0673 , H03M1/361 , H03M1/74 , H03M3/30 , H03M3/338 , H03M3/464
摘要： In one aspect, an electrical signal converter is disclosed. The exemplary electrical signal converter may include a plurality of ordered converter elements. Element selection logic may be provided to pseudorandomly select a pointer to a switch matrix, wherein the switch matrix maps converter elements according to a stepwise "delta-two-maximum pattern." Advantageously, pseudorandom stepwise delta-two-maximum patterns may be applied both to a first order converter, and to a feedback converter for error correction.
摘要翻译：一方面，公开了一种电信号转换器。示例性电信号转换器可以包括多个有序转换元件。可以提供元素选择逻辑以伪随机选择指向开关矩阵的指针，其中开关矩阵根据逐步的“Δ-two-maximum模式”映射转换器元件。有利地，可以将伪随机逐步的Δ-二最大模式应用于一阶转换器和用于纠错的反馈转换器。

10. 发明公开

EP2772032A1 PROCESSOR HAVING INSTRUCTION SET WITH USER-DEFINED NON-LINEAR FUNCTIONS FOR DIGITAL PRE-DISTORTION (DPD) AND OTHER NON-LINEAR APPLICATIONS 审中-公开
标题翻译：带有定制的非线性函数数字预失真（DPD）和其他非线性应用指令集处理器
公开(公告)号：EP2772032A1
公开(公告)日：2014-09-03
申请号：EP12843512.0
申请日：2012-10-26
申请人： LSI Corporation
发明人： AZADET, Kameran , YU, Meng-Lin , PINAULT, Steven, C. , WILLIAMS, Joseph , MOLINA, Albert
IPC分类号： H04L25/02
CPC分类号： G06F9/3001 , G06F5/01 , G06F9/30036 , G06F17/15 , H03F1/0288 , H03F1/3241 , H03F1/3258 , H03F3/189 , H03F3/24 , H03F2200/336 , H03F2201/3209 , H03F2201/3212 , H03F2201/3224 , H03F2201/3233 , H03H17/06 , H03M3/30 , H04B1/0003 , H04B1/0475 , H04B1/62 , H04B2001/0408 , H04L1/0054 , H04L25/02 , H04L25/03 , H04L25/03178 , H04L25/03216 , H04L25/4917 , H04L27/2334
摘要： A processor is provided having an instruction set with user-defined non-linear functions for digital pre-distortion (DPD) and other non-linear applications. A signal processing function, such as DPD, is implemented in software by obtaining at least one software instruction that performs at least one non-linear function for an input value, x, wherein the at least one non-linear function comprises at least one user-specified parameter; in response to at least one of the software instructions for at least one non-linear function having at least one user-specified parameter, performing the following steps: invoking at least one functional unit that implements the at least one software instruction to apply the non-linear function to the input value, x; and generating an output corresponding to the non-linear function for the input value, x. The user-specified parameter can optionally be loaded from memory into at least one register.
摘要翻译：使用非对称的脉冲被提供波峰因子降低（CFR）的技术。甲振幅因数减小方法包括：获得一个或多个数据采样; 检测所述一个或多个数据样本中的至少一个峰; 通过向非对称消除脉冲到至少一个检测到的峰值对所述至少一个检测到的峰峰值抵消; 和提供处理的一个或多个数据采样的版本。非对称抵消脉冲产生，例如，由最小相位滤波器，并且具有大致最小群延迟。具有峰值再生长相关联的新的峰基本上只介绍非对称消除脉冲的一侧上。该方法可任选地在量为大于或等于通过倒带基本上不对称消除脉冲的群延迟，以解决预游标的有限数量并可以存在于不对称消除脉冲。

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