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1. 发明公开

EP2557568A1 Programmable read-only memory device and method of writing the same 有权
标题翻译：程序员Festwertspeichervorrichtung und Verfahren zu deren Beschreiben
公开(公告)号：EP2557568A1
公开(公告)日：2013-02-13
申请号：EP12176635.6
申请日：2012-07-17
申请人： Thomson Licensing
发明人： Kropp, Holger , Blawat, Meinolf
IPC分类号： G11C17/10 , G11C13/02 , H01L29/06 , B82Y10/00
CPC分类号： G11C17/10 , B82Y10/00 , B82Y30/00 , G11C13/025 , G11C23/00 , G11C2213/16 , G11C2213/19 , G11C2213/35 , G11C2213/81 , H01L27/101 , H01L27/1021 , H01L29/0665
摘要： A bit cell of the PROM-device comprises a carbon nanotube having a tilted portion comprising a free end and a fixed portion which is to the reference node. The carbon nanotube comprises a structural defect between the fixed and the tilted portion which causes the carbon nanotube to tilt such that the free end is electrically connected to either the storage electrode or an opposite release electrode.
摘要翻译： PROM装置的位单元包括具有包括自由端的倾斜部分和到参考节点的固定部分的碳纳米管。碳纳米管包括固定和倾斜部分之间的结构缺陷，导致碳纳米管倾斜，使得自由端电连接到存储电极或相对的释放电极。

2. 发明公开

EP2199954A4 SEMICONDUCTOR STORAGE DEVICE AND STORAGE SYSTEM 有权
标题翻译：半导体存储器件与存储系统
公开(公告)号：EP2199954A4
公开(公告)日：2011-03-09
申请号：EP08835488
申请日：2008-09-26
申请人： SHARP KK , UNIV KYOTO , UNIV KEIO
发明人： IMAI SHIGEKI , NAKAMURA YUKIHIRO , OCHI HIROYUKI , OHTA NAOHISA , ONO SADAYASU
IPC分类号： G06K19/077 , G06F3/033 , G06K19/07
CPC分类号： G11C17/10 , G11C5/04 , G11C7/1006 , G11C2207/107 , H01L23/48 , H01L25/16 , H01L31/03921 , H01L31/0445 , H01L31/048 , H01L2924/0002 , H01L2924/3011 , Y02E10/50 , H01L2924/00

3. 发明公开

EP1577898A2 Method for reading multiple bit ROM cell 有权
标题翻译： Verfahren zum Lesen von Multibit ROM-Zellen
公开(公告)号：EP1577898A2
公开(公告)日：2005-09-21
申请号：EP05251525.1
申请日：2005-03-14
申请人： Cambridge Silicon Radio Limited
发明人： Chang, Simon Cambridge Silicon Radio Limited
IPC分类号： G11C17/10 , G11C11/56
CPC分类号： G11C17/10 , G11C11/5692
摘要： A method for reading data stored in a multiple bit memory cell, the memory cell comprising a switch located within an array of switches arranged in columns and rows, each switch having a control node and first and second switched nodes between which the flow of current is dependent on the voltage applied to the control node, wherein each row has a word line connected to the control nodes of the switches of that row, each column comprises only one switch from each row, and each column has first, second and third bit lines connectable to one of the switched nodes of each switch of that column to define the stored data, the method comprising: fixing the voltage of the second bit line of the switch and reading data from the first and third bit lines, and subsequently: fixing the voltage of the first bit line of the switch and reading data from the second and third bit lines.
摘要翻译：一种用于读取存储在多位存储单元中的数据的方法，所述存储器单元包括位于列和列中布置的开关阵列内的开关，每个开关具有控制节点和第一和第二开关节点，其间的电流流为取决于施加到控制节点的电压，其中每行具有连接到该行的开关的控制节点的字线，每列仅包括来自每一行的一个开关，并且每列具有第一，第二和第三位线可连接到该列的每个开关的切换节点之一以定义存储的数据，该方法包括：固定开关的第二位线的电压并从第一和第三位线读取数据，随后：将开关的第一位线的电压，并从第二和第三位线读取数据。

4. 发明公开

EP1115120A3 Method and apparatus for temperature compensation of read-only memory 审中-公开
标题翻译：用于只读存储器的温度补偿方法和装置
公开(公告)号：EP1115120A3
公开(公告)日：2003-09-10
申请号：EP00310932.9
申请日：2000-12-08
申请人： LUCENT TECHNOLOGIES INC.
发明人： Mills, Allen P.
IPC分类号： G11C17/10
CPC分类号： G11C7/04 , G11C17/10
摘要： A method and apparatus for temperature compensation of a resistive based Read-Only Memory device is disclosed. In accordance with the method of the invention, the input voltage supplied to ROM device is adjusted in response to changes in temperature to maintain the current through the ROM at a substantially constant level even as the resistivity of the temperature-dependent connection resistors (29) changes. In one embodiment of the invention, the voltage across the reference resistor (29) is determined by providing a constant current source (27) to the reference resistor and this voltage level is applied to the input of the ROM device. The reference resistor is selected to have similar properties of conductivity as those of the data resistor (30), for example, a polysilicon resistor. As the temperature increases, the resistivity of a polysilicon data resistor (30) and a reference resistor (29) decrease in a similar manner and, accordingly, the voltage across the reference resistor also decreases. The voltage across the reference resistor decreases at a rate commensurate with a decreased voltage drop across the data resistor, thus maintaining the current through a selected data resistor constant.

5. 发明公开

EP1115120A2 Method and apparatus for temperature compensation of read-only memory 审中-公开
标题翻译： Verfahren und Vorrichtung zur Temperaturkompensation eines Festwertspeichers
公开(公告)号：EP1115120A2
公开(公告)日：2001-07-11
申请号：EP00310932.9
申请日：2000-12-08
申请人： LUCENT TECHNOLOGIES INC.
发明人： Mills, Allen P.
IPC分类号： G11C17/10
CPC分类号： G11C7/04 , G11C17/10
摘要： A method and apparatus for temperature compensation of a resistive based Read-Only Memory device is disclosed. In accordance with the method of the invention, the input voltage supplied to ROM device is adjusted in response to changes in temperature to maintain the current through the ROM at a substantially constant level even as the resistivity of the temperature-dependent connection resistors changes. In one embodiment of the invention, the voltage across the reference resistor is determined by providing a constant current source to the reference resistor and this voltage level is applied to the input of the ROM device. The reference resistor is selected to have similar properties of conductivity as those of the data resistor, for example, a polysilicon. As the temperature increases, the resistivity of a polysilicon data resistor and resistor decrease in a similar manner and, accordingly, the voltage across the reference resistor also decreases. The voltage across the reference resistor decreases at a rate commensurate with a decreased voltage drop across the data resistor, thus maintaining the current through a selected data resistor constant.
摘要翻译：公开了一种基于电阻式只读存储器件的温度补偿方法和装置。根据本发明的方法，响应于温度的变化来调节提供给ROM器件的输入电压，以使得通过ROM的电流保持在基本上恒定的水平，即使是依赖于温度的连接电阻器（29）的电阻率，变化。在本发明的一个实施例中，通过向参考电阻器提供恒定电流源（27）来确定参考电阻器（29）两端的电压，并且该电压电平被施加到ROM器件的输入端。参考电阻器被选择为具有与数据电阻器（30），例如多晶硅电阻器类似的导电性。随着温度升高，多晶硅数据电阻器（30）和参考电阻器（29）的电阻率以类似的方式降低，因此，参考电阻器两端的电压也降低。参考电阻两端的电压以与数据电阻两端降低的电压降相当的速率降低，从而保持电流通过选定的数据电阻不变。

6. 发明公开

EP1100125A1 Integrated circuit with identification signal writing circuitry distributed on multiple metal layers 审中-公开
标题翻译：包括：在多个金属层的集成电路分布式布线用于写入的识别信号
公开(公告)号：EP1100125A1
公开(公告)日：2001-05-16
申请号：EP99830699.7
申请日：1999-11-10
申请人： STMicroelectronics S.r.l.
发明人： Vai, Gianfranco , Savo, Pierandrea
IPC分类号： H01L23/544 , G06F11/00 , G11C17/10
CPC分类号： G11C17/10 , G06F11/006 , H01L23/544 , H01L2223/5444 , H01L2223/54473 , H01L2924/0002 , H01L2924/00
摘要： Integrated device (100) comprising a plurality of conducting layers (115a-115c), each having a first (120ga-120gc) and a second (120va-120vc) power supply contact for providing, respectively, a first and a second binary value, and means for supplying at least one identification bit of a version of the integrated device (100); the integrated device (100) includes, for each identification bit, parity check means (135abi, 135bci) having a plurality of input terminals whose number is equal to the number of conducting layers (115a-115c), and an output terminal, each input terminal being connected to one contact selected from the first (120ga-120gc) and the second (120va-120vc) power supply contacts of a corresponding one of the conducting layers (115a-115c), and the output terminal supplying the corresponding identification bit.
摘要翻译：集成器件（100）包括导电层（115A-115C）的复数，每个都具有第一（120ga-120gc）和用于提供第二（120VA-120vc）供电接触件，分别为第一和第二二进制值，和装置，用于提供一个版本的集成设备（100）中的至少一个识别位; 集成器件（100）包括，对于每个识别位，奇偶校验手段（135abi，135bci），其具有输入端子，其数量等于导电层（115A-115C）的数量，和输出端子的复数，每个输入端子被连接到从第一（120ga-120gc）选择的一个接触，并且相应的所述导电层中的一个（115A-115C）的第二个（120VA-120vc）电源触点，和输出端供给对应的识别位。

7. 发明公开

EP0528490A3 Electronic matrix array devices and systems incorporating such devices 失效
标题翻译：电子矩阵阵列装置和结合这种装置的系统
公开(公告)号：EP0528490A3
公开(公告)日：1995-04-19
申请号：EP92202479.9
申请日：1992-08-11
申请人： PHILIPS ELECTRONICS UK LIMITED , Philips Electronics N.V.
发明人： Bird, Neil Christopher, c/o Philips Research Lab.
IPC分类号： G11C11/34 , G11C7/00
CPC分类号： G11C8/10 , G11C17/10
摘要： In an electronic matrix array device, for example a data storage device, such as a datacard, or an electro-optic active matrix display device, comprising crossing sets of row and column conductors (11,12) and matrix elements, e.g. memory cell locations or picture elements (70) respectively, at the intersections of the sets of conductors, at least some of which elements comprise two terminal thin film non-linear devices (14,72), either bidirectional, e.g. MIMs, or unidirectional, e.g. diodes, and further including address circuits (16,18) for the sets of conductors, the row and/or column address circuit comprises a decoder circuit (16,18) consisting of a respective stage for each conductor of the associated set comprising a multi-input, single output logic (AND) gate circuit (30) having a capacitance (31) connected to its output and in which each input is connected to the output via a respective non-linear device (34) of the same kind as those of the array, the inputs being connected to a common address bus (19) to which address codes are applied to select the matrix elements. The decoder circuit can be readily integrated with at least part of the matrix array by common thin film fabrication on the same substrate, thus simplifying manufacture and reducing the number of external interconnections required.
摘要翻译：在电子矩阵阵列装置中，例如数据存储装置，例如数据卡或电光有源矩阵显示装置，包括交叉组的行和列导体（11,12）和矩阵元件，例如，存储器单元位置或图像元件（70），在导体组的交叉点处，至少一些元件包括两个端子薄膜非线性器件（14,72），或者是双向的，例如双向的。 MIM，或单向，例如二极管，并且还包括用于导体组的地址电路（16,18），行和/或列地址电路包括由用于相关组的每个导体的相应级组成的解码器电路（16,18） - 输入端，具有连接到其输出端的电容（31）的单输出逻辑（AND）门电路（30），并且其中每个输入端经由与那些相同类型的相应非线性装置（34）连接到输出端输入端连接到一个公共地址总线（19），地址码被加到这个公共地址总线上以选择矩阵元素。解码器电路可以通过在同一衬底上的普通薄膜制造容易地与矩阵阵列的至少一部分集成，因此简化了制造并减少了所需的外部互连的数量。

8. 发明授权

EP1494283B1 A modifiable circuit, methods of use and making thereof 有权
标题翻译：修改的电路，使用和制备
公开(公告)号：EP1494283B1
公开(公告)日：2008-10-15
申请号：EP04013796.0
申请日：2004-06-11
申请人： Broadcom Corporation
发明人： Catalasan, Manolito , Rakshani, Vafa J. , Spittles, Edmund H. , Sippel, Tim , Unda, Richard
IPC分类号： H01L23/544 , H01L23/525 , H01L23/528 , H01L23/58 , G06F11/00 , G11C17/10
CPC分类号： G11C17/10 , H01L23/544 , H01L27/118 , H01L2223/5444 , H01L2924/0002 , H01L2924/00

9. 发明公开

EP1577898A3 Method for reading multiple bit ROM cell 有权
标题翻译：一种用于读取多ROM细胞的方法
公开(公告)号：EP1577898A3
公开(公告)日：2006-08-30
申请号：EP05251525.1
申请日：2005-03-14
申请人： Cambridge Silicon Radio Limited
发明人： Chang, Simon Cambridge Silicon Radio Limited
IPC分类号： G11C17/10 , G11C11/56
CPC分类号： G11C17/10 , G11C11/5692
摘要： A method for reading data stored in a multiple bit memory cell, the memory cell comprising a switch located within an array of switches arranged in columns and rows, each switch having a control node and first and second switched nodes between which the flow of current is dependent on the voltage applied to the control node, wherein each row has a word line connected to the control nodes of the switches of that row, each column comprises only one switch from each row, and each column has first, second and third bit lines connectable to one of the switched nodes of each switch of that column to define the stored data, the method comprising: fixing the voltage of the second bit line of the switch and reading data from the first and third bit lines, and subsequently: fixing the voltage of the first bit line of the switch and reading data from the second and third bit lines.

10. 发明公开

EP1691373A1 Dispositif semi-conducteur de mémoire morte et procédé de programmation correspondant 审中-公开
标题翻译： ROM-Halbleiterspeicher和Programmierverfahren
公开(公告)号：EP1691373A1
公开(公告)日：2006-08-16
申请号：EP06290145.9
申请日：2006-01-24
申请人： STMicroelectronics SA
发明人： Schoellkopf, Jean-Pierre
IPC分类号： G11C17/10 , H01L21/8246
CPC分类号： G11C17/10 , Y10S257/91
摘要： Une cellule semi-conductrice comporte au sein d'une région de substrat quatre zones actives (Z1-Z4) mutuellement isolées latéralement, la première zone active étant destinée à être reliée à une première tension (VDD), la deuxième zone active, d'un type de conductivité opposé à celui de la première zone active, étant destinée à être reliée à une deuxième tension (GND), les troisième et quatrième zones actives (Z3-Z4) étant mutuellement reliées par une connexion de raccordement (P34) électriquement conductrice et extérieure au substrat. On définit la valeur de l'information binaire par une implantation de type choisi dans une partie (CSA) prédéterminée de la région de substrat (SB) ou dans les troisième et quatrième zones actives (Z3-Z4).
摘要翻译：该器件具有在衬底内相互隔离的4个有源区（Z1-Z4）的单元。邻近基板的导电连接（P34）连接区域（Z3，Z4）。半导体电连接基于单元中的二进制数据的逻辑值将区域（Z3，Z4）中的一个连接到区域（Z1，Z2）之一。半导体电隔离将区域（Z3，Z4）与各个区域（Z1，Z2）隔离。区域（Z1，Z2）分别连接到电源电压和接地。还包括以下独立权利要求：（1）读取存储在存储器件单元中的二进制数据的逻辑值的方法（2）一种对存储器件单元中的二进制数据进行编程的方法。

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