专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

EP0545082A3 Process for manufacturing MOS-type integrated circuits comprising LOCOS isolation regions 失效
标题翻译：一种用于生产所述LOCOS型的绝缘区的MOS类型的集成电路过程。
公开(公告)号：EP0545082A3
公开(公告)日：1994-10-12
申请号：EP92118785.2
申请日：1992-11-02
申请人： SGS-THOMSON MICROELECTRONICS S.r.l.
发明人： Cereda, Manlio Sergio , Ginami, Giancarlo , Laurin, Enrico , Ravaglia, Andrea
IPC分类号： H01L21/76 , H01L21/82
CPC分类号： H01L27/11526 , H01L21/76216 , H01L21/76218 , H01L21/823878 , H01L27/11546
摘要： A process for producing integrated circuits comprising the steps of: selectively growing field insulating regions (10) of insulating material extending partly inside a substrate (1) having a given type of conductivity (P); depositing a polycrystalline silicon layer (14) on the substrate; shaping the polycrystalline silicon layer through a mask (20); and selectively implanting (21) ions of the same conductivity type (P) as the substrate (1) using the shaping mask (20) and through the field insulating regions (10), the implanted ions penetrating inside the substrate (1) having the given type of conductivity (P), for forming channel stopper regions (8') beneath the field insulating regions.

2. 发明公开

EP0335148A2 Method for programming MOS and CMOS rom memories 失效
标题翻译： Verfahren zur Pragrammierung von MOS和CMOS-ROM-Speichern。
公开(公告)号：EP0335148A2
公开(公告)日：1989-10-04
申请号：EP89104165.9
申请日：1989-03-09
申请人： SGS-THOMSON MICROELECTRONICS S.r.l.
发明人： Bekkering, Roland Quirinus , Cereda, Manlio Sergio
IPC分类号： H01L21/82 , H01L27/10
CPC分类号： H01L27/11266 , H01L27/112
摘要： A method for programming ROM memories at an advanced memory manufacture stage. The method, after defining the active regions, possibly implanting threshold-correction boron, performing gate oxidation and providing the gate regions, comprises at least partially masking the regions adjacent to the gate regions of the memory cells which must be made permanently non-conductive. During the subsequent implanting of the source and drain regions, the regions thus shielded are not implanted, so that in the programmed cells the source and/or drain regions are completely missing or in any case separated from the related gate regions by such a distance as to prevent switching on of the memory cell when reading in the memory.
摘要翻译：一种在高级存储器制造阶段对ROM存储器进行编程的方法。该方法在定义有源区域之后，可能注入阈值校正硼，执行栅极氧化和提供栅极区域，包括至少部分地掩蔽与必须永久不导电的存储器单元的栅极区域相邻的区域。在随后的源极和漏极区域的注入期间，这样屏蔽的区域不被植入，使得在编程的单元中源极和/或漏极区域完全缺失或者在任何情况下都与相关的栅极区域分开一段距离以防止在读取存储器时接通存储器单元。

3. 发明公开

EP0655776A1 Autoplanarizing process for the passivation of an integrated circuit 失效
标题翻译： Selbstplanarisierungsverfahrenfürdie passivierung von einer integrierten Schaltung。
公开(公告)号：EP0655776A1
公开(公告)日：1995-05-31
申请号：EP93830480.5
申请日：1993-11-30
申请人： SGS-THOMSON MICROELECTRONICS S.r.l.
发明人： Cereda, Manlio Sergio , Daffra, Stefano , Stucchi, Elena
IPC分类号： H01L21/314 , H01L21/768
CPC分类号： H01L21/314 , H01L27/115
摘要： In a passivating method using silicon oxidonitride, prior to forming that layer (10), the surface is planarized by overlying the circuit structures (2,3) with at least a first layer (8) of a dielectric material, and on top of this, a second layer (9) of a dielectric material. The layers have such thickness dimensions as to ensure planarization of the top surface. In addition, the invention may be used with a passivation method without oxidonitride wherein the underlying morphology is also planarized by forming those same dielectric layers.
摘要翻译：在使用硅氧化氮的钝化方法中，在形成该层（10）之前，通过用电介质材料的至少第一层（8）覆盖电路结构（2,3）来平坦化表面，并且在该顶部，介电材料的第二层（9）。这些层具有这样的厚度尺寸以确保顶表面的平坦化。此外，本发明可以与没有氧化氮化物的钝化方法一起使用，其中下面的形态也通过形成这些相同的介电层而被平坦化。

4. 发明公开

EP0545082A2 Process for manufacturing MOS-type integrated circuits comprising LOCOS isolation regions 失效
标题翻译： Verfahren zur Herstellung Isolationszonen des LOCOS-类型fürintegrierte Schaltungen vom MOS-Typ。
公开(公告)号：EP0545082A2
公开(公告)日：1993-06-09
申请号：EP92118785.2
申请日：1992-11-02
申请人： SGS-THOMSON MICROELECTRONICS S.r.l.
发明人： Cereda, Manlio Sergio , Ginami, Giancarlo , Laurin, Enrico , Ravaglia, Andrea
IPC分类号： H01L21/76 , H01L21/82
CPC分类号： H01L27/11526 , H01L21/76216 , H01L21/76218 , H01L21/823878 , H01L27/11546
摘要： A process for producing integrated circuits comprising the steps of: selectively growing field insulating regions (10) of insulating material extending partly inside a substrate (1) having a given type of conductivity (P); depositing a polycrystalline silicon layer (14) on the substrate; shaping the polycrystalline silicon layer through a mask (20); and selectively implanting (21) ions of the same conductivity type (P) as the substrate (1) using the shaping mask (20) and through the field insulating regions (10), the implanted ions penetrating inside the substrate (1) having the given type of conductivity (P), for forming channel stopper regions (8') beneath the field insulating regions.
摘要翻译：一种用于制造集成电路的方法，包括以下步骤：选择性地生长绝缘材料的场绝缘区域（10），其部分地在具有给定类型导电性（P）的衬底（1）内延伸; 在衬底上沉积多晶硅层（14）; 通过掩模（20）对所述多晶硅层进行成形; 以及使用成形掩模（20）和通过场绝缘区域（10）选择性地注入与衬底（1）相同的导电类型（P）的（21）离子，所述注入的离子穿透在具有给定类型的导电率（P），用于在场绝缘区域下形成沟道阻挡区域（8'）。

5. 发明公开

EP0793273A1 Method for improving the intermediate dielectric profile, particularly for non-volatile memories 失效
标题翻译：为了提高中间介电曲线，特别是用于非易失性存储器的方法
公开(公告)号：EP0793273A1
公开(公告)日：1997-09-03
申请号：EP96830086.3
申请日：1996-02-28
申请人： SGS-THOMSON MICROELECTRONICS s.r.l.
发明人： Brambilla, Claudio , Ginami, Giancarlo , Daffra, Stefano , Ravaglia, Andrea , Cereda, Manlio Sergio
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method for improving the intermediate dielectric profile, particularly for non-volatile memories constituted by a plurality of cells, which comprises the following steps:

-- forming field oxide regions (14) and drain active area regions (15) on a substrate (1);
-- forming word lines (16) on the field oxide regions (14);
-- depositing oxide to form oxide wings (13) that are adjacent to the word lines (16);
characterized in that it comprises the following additional steps:

-- opening, by masking (20), source regions (18) and the drain active area regions (15), keeping the field oxide regions (14) that separate one memory cell from the other, inside the memory, covered with resist; and
-- removing field oxide (14) in the source regions (18) and removing oxide wings (13) from both sides of the word lines (16).
摘要翻译：一种提高在中间电介质分布，特别是用于通过细胞的复数，其包括以下步骤构成的非易失性存储器的方法： - 形成场氧化区（14）和漏有源区的区域（15）上的基板（1 ）; - 形成字线（16）上的场氧化区（14）; - （13）做了沉积氧化，从而形成氧化翼邻近于字线（16）; 在这样做是包括下列附加步骤，其特征在于： - 开口，通过掩蔽（20），源极区（18）和漏有源区的区域（15），保持场氧化区（14）做了单独的一个存储器单元从所述其他，存储器，覆盖有抗蚀剂的内部; 和 - 从所述字线（16）的bothsides除去在源极区（18）和除去氧化物翼（13）的场氧化物（14）。

6. 发明公开

EP0655773A1 Lithographic image size reduction 失效
标题翻译： Lithographische Reduzierung derBildgrösse。
公开(公告)号：EP0655773A1
公开(公告)日：1995-05-31
申请号：EP93830427.6
申请日：1993-10-27
申请人： SGS-THOMSON MICROELECTRONICS S.r.l.
发明人： Brambilla, Claudio , Cereda, Manlio Sergio , Ravaglia, Andrea
IPC分类号： H01L21/033 , H01L21/308
CPC分类号： H01L21/0337 , H01L21/0338
摘要： A mask having features of a smaller size than a lithographically defined image width is formed by depositing a first layer of a different material from the underlying material to be treated through the openings of the mask. This first layer is lithographically patterned and thereafter a conformally deposited second layer is anisotropically etched, thus leaving residues on vertical definition walls of the first layer. The mask openings are restricted to a controllably reduced width as compared with the width of the lithographically defined window. Empirical relationships between the thicknesses of the deposited layers and the reduction of the lithographic image size that is achieved provide a good dimensional control of the mask openings that are finally produced, adequate for sub-micron line-width processes.
摘要翻译：具有比光刻图像宽度小的特征的掩模通过从掩模的开口沉积不同材料的第一层与待处理的下层材料而形成。该第一层被光刻图案化，其后共形沉积的第二层被各向异性地蚀刻，从而在第一层的垂直定义壁上留下残留物。与光刻定义的窗口的宽度相比，掩模开口被限制为可控制地减小的宽度。沉积层的厚度与实现的平版印刷图像尺寸的减小之间的经验关系提供了最终产生的足够用于亚微米线宽工艺的掩模开口的良好尺寸控制。

7. 发明公开

EP0335148A3 Method for programming MOS and CMOS rom memories 失效
标题翻译：编程MOS和CMOS ROM存储器的方法
公开(公告)号：EP0335148A3
公开(公告)日：1990-01-24
申请号：EP89104165.9
申请日：1989-03-09
申请人： SGS-THOMSON MICROELECTRONICS S.r.l.
发明人： Bekkering, Roland Quirinus , Cereda, Manlio Sergio
IPC分类号： H01L21/82 , H01L27/10
CPC分类号： H01L27/11266 , H01L27/112
摘要： A method for programming ROM memories at an advanced memory manufacture stage. The method, after defining the active regions, possibly implanting threshold-correction boron, performing gate oxidation and providing the gate regions, comprises at least partially masking the regions adjacent to the gate regions of the memory cells which must be made permanently non-conductive. During the subsequent implanting of the source and drain regions, the regions thus shielded are not implanted, so that in the programmed cells the source and/or drain regions are completely missing or in any case separated from the related gate regions by such a distance as to prevent switching on of the memory cell when reading in the memory.
摘要翻译：一种在高级存储器制造阶段对ROM存储器进行编程的方法。该方法在定义有源区域之后，可能注入阈值校正硼，执行栅极氧化和提供栅极区域，包括至少部分地掩蔽与必须永久不导电的存储器单元的栅极区域相邻的区域。在随后的源极和漏极区域的注入期间，这样屏蔽的区域不被植入，使得在编程的单元中源极和/或漏极区域完全缺失或者在任何情况下都与相关的栅极区域分开一段距离以防止在读取存储器时接通存储器单元。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式