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1. 发明授权

EP1394852B1 Method of fabricating a semiconductor device 有权
公开(公告)号：EP1394852B1
公开(公告)日：2018-07-11
申请号：EP03018690.2
申请日：2003-08-22
申请人： Fujitsu Semiconductor Limited
发明人： Saito, Hitoshi, Fujitsu Limited
IPC分类号： H01L21/762 , H01L27/105 , H01L27/11526 , H01L27/11543 , H01L27/11546
CPC分类号： H01L21/76229 , H01L27/105 , H01L27/11526 , H01L27/11543 , H01L27/11546
摘要： A pad oxide film (11) and a silicon nitride film (12) are formed on a semiconductor substrate (10). Next, after the patterning of the silicon nitride film (12), by etching the pad oxide film (11) and the substrate (10), a first trench (13a) is formed in a first region and a second trench (13b) is formed in a second region. After that, by performing side etching of the pad oxide film (11) of the first region while protecting the second region with a resist, a gap is formed between the substrate (10) and the silicon nitride film (12). Subsequently, the inner surfaces of the first and second trenches (13a, 13b) are oxidized. At this time, a relatively large volume of oxidizing agent (oxygen) is supplied to a top edge portion of the first trench (13a), and the curvature of the corner of the substrate (10) increases.

2. 发明公开

EP3097561A4 METHODS AND APPARATUSES WITH VERTICAL STRINGS OF MEMORY CELLS AND SUPPORT CIRCUITRY 无效
公开(公告)号：EP3097561A4
公开(公告)日：2018-01-03
申请号：EP15740682
申请日：2015-01-21
申请人： MICRON TECHNOLOGY INC
发明人： HASEGAWA TAKEHIRO , SAKUI KOJI
IPC分类号： G11C5/02 , G11C5/04 , G11C5/14 , G11C16/04 , H01L27/06 , H01L27/11546 , H01L27/11556 , H01L27/11573 , H01L27/11582
CPC分类号： H01L27/11531 , G11C5/145 , G11C16/0483 , H01L21/28273 , H01L21/28282 , H01L27/0694 , H01L27/115 , H01L27/11546 , H01L27/11556 , H01L27/11573 , H01L27/11582 , H01L29/66477 , H01L29/78
摘要： Apparatuses and methods have been disclosed. One such apparatus includes strings of memory cells formed on a topside of a substrate. Support circuitry is formed on the backside of the substrate and coupled to the strings of memory cells through vertical interconnects in the substrate. The vertical interconnects can be transistors, such as surround substrate transistors and/or surround gate transistors.

3. 发明公开

EP3248220A1 METHOD OF FORMING SPLIT-GATE MEMORY CELL ARRAY ALONG WITH LOW AND HIGH VOLTAGE LOGIC DEVICES 有权
标题翻译：用低压和高压逻辑器件形成分裂栅极存储器单元阵列的方法
公开(公告)号：EP3248220A1
公开(公告)日：2017-11-29
申请号：EP16702642.6
申请日：2016-01-19
申请人： Silicon Storage Technology Inc.
发明人： WU, Man-Tang , YANG, Jeng-Wei , SU, Chien-sheng , CHEN, Chun-Ming , DO, Nhan
IPC分类号： H01L27/115 , H01L29/423
CPC分类号： H01L29/66537 , H01L21/28273 , H01L27/11519 , H01L27/11546 , H01L29/42328 , H01L29/66825
摘要： A method of forming a memory device on a substrate having memory, LV and HV areas, including forming pairs of spaced apart memory stacks in the memory area, forming a first conductive layer over and insulated from the substrate, forming a first insulation layer on the first conductive layer and removing it from the memory and HV areas, performing a conductive material deposition to thicken the first conductive layer in the memory and HV areas, and to form a second conductive layer on the first insulation layer in the LV area, performing an etch to thin the first conductive layer in the memory and HV areas and to remove the second conductive layer in the LV area, removing the first insulation layer from the LV area, and patterning the first conductive layer to form blocks of the first conductive layer in the memory, LV and HV areas.

4. 发明授权

EP1865554B1 Semiconductor memory device and method for operation 有权
标题翻译：一种半导体存储器件及其操作方法
公开(公告)号：EP1865554B1
公开(公告)日：2017-01-11
申请号：EP06011932.8
申请日：2006-06-09
申请人： ams AG
发明人： Leisenberger, Friedrich Peter , Park, Jong Mun
IPC分类号： H01L27/115 , H01L27/105
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11546

5. 发明授权

EP1416540B8 SEMICONDUCTOR NONVOLATILE MEMORY DEVICE 有权
标题翻译： HALBLEITERFESTWERTSPEICHER-BAUELEMENT
公开(公告)号：EP1416540B8
公开(公告)日：2016-12-07
申请号：EP02749325.3
申请日：2002-07-22
申请人： Renesas Electronics Corporation
发明人： TANAKA, Toshihiro c/o Semicond.& Integr. Circuits , UMEMOTO, Yukiko c/o Semicond.& Integr. Circuits , HIRAKI, Mitsuru c/o Semicond.& Integr. Circuits , SHINAGAWA, Yutaka c/o HITACHI ULSI SYST CO., LTD. , FUJITO, Masamichi c/o HITACHI ULSI SYST.CO., LTD. , SUZUKAWA, Kazufumi c/o HITACHI ULSI SYST.CO.,LTD. , TANIKAWA, Hiroyuki c/o Semicond.& Integr. Circ. , YAMAKI, Takashi c/o Semicond.& Integr. Circuits , KAMIGAKI, Yoshiaki c/o Central Research Lab. , MINAMI, Shinichi c/o Semicond.& Integr. Circuits , KATAYAMA, Kozo c/o Semicond. & Integr. Circuits , MATSUZAKI, Nozomu c/o Central Research Laboratory
IPC分类号： H01L27/115 , G11C16/04 , H01L29/423 , H01L29/792 , H01L29/788
CPC分类号： G11C16/26 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/30 , H01L21/28 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42328 , H01L29/42332 , H01L29/4234 , H01L29/66825 , H01L29/7885 , H01L29/792
摘要： Each non-volatile memory cell (1) of the device has MOS-type transistor (3) for information storage and MOS-type transistor (4) for selecting transistor (3). The gate dielectric strength and thickness of gate insulation film of transistor (4) are lower than that of transistor (3).
摘要翻译：器件的每个非易失性存储单元（1）具有用于信息存储的MOS型晶体管（3）和用于选择晶体管（3）的MOS型晶体管（4）。晶体管（4）的栅极绝缘膜的栅极绝缘强度和厚度比晶体管（3）低。

6. 发明授权

EP1274132B1 Semiconductor non volatile memory device and method of producing the same 有权
标题翻译：一种非易失性半导体存储器件及其制备方法
公开(公告)号：EP1274132B1
公开(公告)日：2015-10-07
申请号：EP02290504.6
申请日：2002-03-01
申请人： Fujitsu Semiconductor Limited
发明人： Hiroshi, Hashimoto , Koji, Takahashi
IPC分类号： H01L27/115 , H01L29/788 , H01L21/8247 , H01L21/336
CPC分类号： H01L27/105 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L27/11558 , H01L29/7883

7. 发明授权

EP1156524B1 Manufacturing process of an integrated circuit including high-density and logic components portion 有权
标题翻译：用于制造具有高密度和逻辑器件的一部分的集成电路的方法
公开(公告)号：EP1156524B1
公开(公告)日：2014-10-22
申请号：EP00201716.8
申请日：2000-05-15
申请人： Micron Technology, Inc.
发明人： Maurelli, Alfonso
IPC分类号： H01L21/8247 , H01L21/8239 , H01L27/105 , H01L21/8238 , H01L27/115
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11517 , H01L27/11546

8. 发明公开

EP2267767A3 Semiconductor device and method of fabricating the same 审中-公开
标题翻译： Halbleiterbauelement和dessen Herstellungsverfahren
公开(公告)号：EP2267767A3
公开(公告)日：2013-12-25
申请号：EP10187862.7
申请日：2003-08-22
申请人： Fujitsu Microelectronics Limited
发明人： Saito, Hitoshi
IPC分类号： H01L21/8239 , H01L27/105 , H01L21/762 , H01L27/115
CPC分类号： H01L21/76229 , H01L27/105 , H01L27/11526 , H01L27/11543 , H01L27/11546
摘要： A pad oxide film and a silicon nitride film are formed on a semiconductor substrate. Next, after the patterning of the silicon nitride film, by etching the pad oxide film and the substrate, a first trench is formed in a first region and a second trench is formed in a second region. After that, by performing side etching of the pad oxide film of the first region while protecting the second region with a resist, a gap is formed between the substrate and the silicon nitride film. Subsequently, the inner surfaces of the first and second trenches are oxidized. At this time, a relatively large volume of oxidizing agent (oxygen) is supplied to a top edge portion of the first trench, and the curvature of the corner of the substrate increases.
摘要翻译：在半导体衬底（10）上形成衬垫氧化膜（11）和氮化硅膜（12）。接下来，在氮化硅膜（12）的图案化之后，通过蚀刻衬垫氧化膜（11）和衬底（10），在第一区域中形成第一沟槽（13a），并且第二沟槽（13b）形成于第二区域。之后，通过对第一区域的衬垫氧化膜（11）进行侧蚀刻，同时用抗蚀剂保护第二区域，在衬底（10）和氮化硅膜（12）之间形成间隙。随后，第一和第二沟槽（13a，13b）的内表面被氧化。此时，将较大体积的氧化剂（氧）供给到第一沟槽（13a）的顶部边缘部分，并且衬底（10）的角部的曲率增加。

9. 发明公开

EP2648220A1 Floating gate memory device with trench isolation and method for manufacturing thereof 有权
标题翻译： Schwebegatespeicher-Bauelement mit Isolationsgraben und dessen Herstellung
公开(公告)号：EP2648220A1
公开(公告)日：2013-10-09
申请号：EP13175277.6
申请日：2006-06-30
申请人： Fujitsu Semiconductor Limited
发明人： EmaMA, Taiji , Mizutani, Kazuhiro
IPC分类号： H01L27/115 , H01L21/8247 , H01L21/762
CPC分类号： H01L29/788 , H01L21/762 , H01L21/76232 , H01L27/105 , H01L27/11526 , H01L27/11536 , H01L27/11546 , H01L27/11548 , H01L27/11575 , H01L29/42336 , H01L29/7881
摘要： A semiconductor device includes: a semiconductor substrate having first and second areas; an STI isolation region being made of an isolation trench formed in the semiconductor substrate and an insulating film burying the isolation trench and defining a plurality of active regions in the first and second areas; a first structure formed on an area from the active region in the first area to a nearby STI isolation region and having a first height; and a second structure formed on an area from the active region in the second area to a nearby STI isolation region and having a second height, wherein the surface of the said STI isolation region in the first area is lower than the surface of said STI isolation region in the second area.
摘要翻译：半导体器件包括：具有第一和第二区域的半导体衬底; STI隔离区域由形成在半导体衬底中的隔离沟槽和绝缘膜构成，绝缘膜掩埋隔离沟槽并且在第一和第二区域中限定多个有源区域; 形成在从所述第一区域中的有源区域到附近的STI隔离区域并具有第一高度的区域上的第一结构; 以及形成在从所述第二区域中的有源区域到附近的STI隔离区域并具有第二高度的区域上的第二结构，其中所述第一区域中的所述STI隔离区域的表面低于所述STI隔离物的表面区域在第二区域。

10. 发明授权

EP1265276B1 METHOD FOR FORMING DIELECTRIC FILM 有权
标题翻译：方法的介电薄膜教育
公开(公告)号：EP1265276B1
公开(公告)日：2011-06-22
申请号：EP01912316.5
申请日：2001-03-13
申请人： Ohmi, Tadahiro
发明人： OHMI, Tadahiro , SUGAWA, Shigetoshi, Graduate School of Engineering, Tohoku University
IPC分类号： H01L21/316 , H01L21/318 , H01L29/78 , H01L29/788 , H01L29/792 , H01L21/8247
CPC分类号： H01L21/31641 , C23C8/02 , C23C8/36 , H01L21/0217 , H01L21/02238 , H01L21/02247 , H01L21/02252 , H01L21/02323 , H01L21/02329 , H01L21/0234 , H01L21/3105 , H01L21/3144 , H01L21/31612 , H01L21/31637 , H01L21/31662 , H01L21/3185 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42324
摘要： A method of forming an insulation film includes the steps of forming an insulation film on a substrate, and modifying a film quality of the insulation film by exposing the insulation film to atomic state oxygen O* or atomic state hydrogen nitride radicals NH* formed with plasma that uses Kr or Ar as inert gas.

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