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    • 1. 发明公开
    • NON-VOLATILE MEMORY ARRAY WITH CONCURRENTLY FORMED LOW AND HIGH VOLTAGE LOGIC DEVICES
    • 非易失性存储器阵列与同时形成的低电压和高电压逻辑器件
    • EP3227923A1
    • 2017-10-11
    • EP15795310.0
    • 2015-11-06
    • Silicon Storage Technology Inc.
    • ZHOU, FengLIU, XianDO, Nhan
    • H01L29/423H01L27/115
    • H01L27/11521H01L27/11526H01L27/11546H01L29/42328H01L29/513H01L29/517H01L29/66545H01L29/66825H01L29/66833H01L29/788H01L29/792
    • A memory cell includes source and drain regions in a substrate with a channel region therebetween, an erase gate over the source region, a floating gate over a first channel region portion, a control gate over the floating gate, and a wordline gate over a second channel region portion. A first logic device includes second source and drain regions in the substrate with a second channel region therebetween under a first logic gate. A second logic device includes third source and drain regions in the substrate with a third channel region therebetween under a second logic gate. The wordline gate and the first and second logic gates comprise the same conductive metal material. The second logic gate is insulated from the third channel region by first and second insulation. The first logic gate is insulated from the second channel region by the second insulation and not by the first insulation.
    • 存储器单元包括衬底中的源极区和漏极区,其间具有沟道区,源极区上方的擦除栅极,第一沟道区部分上方的浮动栅极,浮动栅极上方的控制栅极以及第二沟道区域上方的字线​​栅极 沟道区域部分。 第一逻辑器件包括在衬底中的第二源极和漏极区域,其中第一逻辑门下方的第二沟道区域位于第二逻辑器件之间。 第二逻辑器件包括衬底中的第三源极区和漏极区,第二逻辑门下面具有第三沟道区。 字线门和第一和第二逻辑门包括相同的导电金属材料。 第二逻辑门通过第一和第二绝缘与第三沟道区域绝缘。 第一逻辑门通过第二绝缘而不通过第一绝缘与第二通道区域绝缘。
    • 6. 发明公开
    • Patterning a gate stack of a non-volatile memory (nvm) with simultaneous etch in non-nvm area
    • 图案化的非易失性存储器的栅极堆叠与所述非易失性存储区域的同时蚀刻
    • EP2423952A2
    • 2012-02-29
    • EP11176611.9
    • 2011-08-04
    • Freescale Semiconductor, Inc.
    • Shroff, Mehul D.
    • H01L21/28H01L29/423H01L29/788
    • H01L29/7881H01L21/28273H01L27/11534H01L27/11546H01L29/42328H01L29/42332
    • Forming a gate stack of a non-volatile memory (NVM) over a substrate (84) having an NVM region (82) and non-NVM region (80) which does not overlap the NVM region includes forming a select gate layer (92) over the substrate in the NVM and non-NVM regions; simultaneously etching the select gate layer in the NVM and non-NVM regions; forming a charge storage layer (96) over the substrate in the NVM and non-NVM regions; forming a control gate layer (98) over the charge storage layer in the NVM and non-NVM regions; and simultaneously etching the charge storage layer in the NVM and the non-NVM regions. Etching the select gate layer in the NVM region results in a portion of the charge storage layer over a portion of the select gate layer and overlapping a sidewall of the select gate layer and results in a portion of the control gate layer over the portion of the charge storage layer.
    • 形成栅极的非易失性存储器(NVM)的在基板具有在NVM区域(82)和非NVM区域(80)堆(84)不重叠的NVM区域包括形成选择栅极层(92) 过在NVM和非NVM区域的基板; 同时蚀刻在NVM和非NVM区域选择栅极层; 上方形成在NVM和非NVM区域衬底的电荷存储层(96); 上方形成在NVM和非NVM区域所述电荷存储层的控制栅极层(98); 同时并蚀刻在NVM和非NVM区域电荷存储层。 蚀刻在所述NVM区域结果选择栅极层中在选择栅极层的部分上的电荷存储层的一部分和在该控制栅层的一部分上的所述部分选择栅极层和结果的侧壁重叠的 电荷存储层。