专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

EP0886209B1 Extensible risc microprocessor architecture 失效
标题翻译： RISC处理器与可膨胀结构
公开(公告)号：EP0886209B1
公开(公告)日：2005-03-23
申请号：EP98119123.2
申请日：1992-07-07
申请人： SEIKO EPSON CORPORATION
发明人： Nguyen, Le Trong , Miyayama, Yoshiyuki , Lentz, Derek J. , Garg, Sanjiv , Hagiwara, Yasuaki , Wang, Johannes , Lau, Tei-Li , Trang, Quang H.
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/30167 , G06F9/30054 , G06F9/30101 , G06F9/30105 , G06F9/30112 , G06F9/30116 , G06F9/3012 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30141 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3814 , G06F9/3824 , G06F9/3828 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3853 , G06F9/3857 , G06F9/3861 , G06F9/3865 , G06F9/3885

2. 发明公开

EP0886209A2 Extensible risc microprocessor architecture 失效
标题翻译： RISC-Prozessor mit erweiterbarer Architektur
公开(公告)号：EP0886209A2
公开(公告)日：1998-12-23
申请号：EP98119123.2
申请日：1992-07-07
申请人： SEIKO EPSON CORPORATION
发明人： Nguyen, Le Trong , Miyayama, Yoshiyuki , Lentz, Derek J. , Garg, Sanjiv , Hagiwara, Yasuaki , Wang, Johannes , Lau, Tei-Li , Trang, Quang H.
IPC分类号： G06F9/38
CPC分类号： G06F9/30167 , G06F9/30054 , G06F9/30101 , G06F9/30105 , G06F9/30112 , G06F9/30116 , G06F9/3012 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30141 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3814 , G06F9/3824 , G06F9/3828 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3853 , G06F9/3857 , G06F9/3861 , G06F9/3865 , G06F9/3885
摘要： The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of functional units. The fetch unit generally maintains a predetermined number of instructions in an instruction buffer. The execution unit includes an instruction selection unit, coupled to the instruction buffer, for selecting instructions for execution, and a plurality of functional units for performing instruction specified functional operations. A unified instruction scheduler, within the instruction selection unit, initiates the processing of instructions through the functional units when instructions are determined to be available for execution and for which at least one of the functional units implementing a necessary computational function is available. Unified scheduling is performed across mutliple execution data paths, where each execution data path, and corresponding functional units, is generally optimized for the type of computational function that is to be performed on the data: integer, floating point, and boolean. The number, type and computational specifics of the functional units provided in each data path, and as between data paths, are mutually independent.
摘要翻译：高性能的基于RISC核心的微处理器架构包括用于从指令存储器取出指令集的指令获取单元和通过并行的功能单元阵列实现多个指令并行执行的执行单元。提取单元通常在指令缓冲器中保持预定数量的指令。执行单元包括指令选择单元，耦合到指令缓冲器，用于选择用于执行的指令;以及多个功能单元，用于执行指令指定的功能操作。在指令选择单元内的统一指令调度器在确定可用于执行的指令并且实现必要的计算功能的功能单元中的至少一个可用时，通过功能单元启动对指令的处理。在多个执行数据路径上执行统一调度，其中每个执行数据路径和相应的功能单元通常针对要对数据执行的计算函数类型进行优化：整数，浮点和布尔值。在每个数据路径中以及数据路径之间提供的功能单元的数量，类型和计算细节是相互独立的。

3. 发明公开

EP0945787A3 Risc microprocessor architecture implementing fast trap and exception state 失效
标题翻译： Risc-Mikroprozessorarchitektur mit schneller Unterbrechung und Ausnahmezustand
公开(公告)号：EP0945787A3
公开(公告)日：2008-12-31
申请号：EP99112833.1
申请日：1992-07-07
申请人： Seiko Epson Corporation
发明人： Nguyen, Le Trong , Miyayama, Yoshiyuki , Garg, Sanjiv , Trang, Quang H. , Lentz, Derek J. , Hagiwara, Yasuaki , Wang, Johannes , Lau, Tei-li
IPC分类号： G06F9/38
CPC分类号： G06F9/3865 , G06F9/3017 , G06F9/32 , G06F9/322 , G06F9/3802 , G06F9/3804 , G06F9/3814 , G06F9/3836 , G06F9/384 , G06F9/3857 , G06F9/3861 , G06F9/3885 , G06F9/462 , G06F9/4812 , G06F15/7842
摘要： Fast trap mechanism for a microprocessor, wherein a vector trap table is maintained which contains space for a plurality of instructions in each table entry. When a fast trap occurs, control is transferred directly into the table entry corresponding to the trap number. The trap handler can be located completely inside the table entry, or it can transfer control to additional handler code.
摘要翻译：一种用于微处理器的快速陷阱机制，其中维护一个矢量陷阱表，其中包含每个表条目中的多个指令的空间。当发生快速陷阱时，控制将直接传输到与陷阱号对应的表条目中。陷阱处理程序可以完全位于表条目中，也可以将控制权转移到附加处理程序代码。

4. 发明公开

EP0911724A2 Process and method for utilizing register file resources 失效
标题翻译： Prozess und Verfahren zur Verwendung von Registerspeichern
公开(公告)号：EP0911724A2
公开(公告)日：1999-04-28
申请号：EP99102406.8
申请日：1992-07-08
申请人： Seiko Epson Corporation
发明人： Lentz, Derek J. , Nguyen, Le Trong , Garg, Sanjiv , Chen, Sho Long
IPC分类号： G06F9/30
CPC分类号： G06F9/30029 , G06F9/30036 , G06F9/30112 , G06F9/30116 , G06F9/3012 , G06F9/30123 , G06F9/3013 , G06F9/30138 , G06F9/30167 , G06F9/30189 , G06F9/3851
摘要： The invention provides a processor and method for efficiently utilizing register file resources. The processor comprises an execution unit that performs at least one operation according to an instruction; a first register set including a plurality of first registers each for holding integer data; and a second register set including a plurality of second registers each for holding said integer data and for holding floating point data, wherein said instruction specifies which of said first and second register sets is to be accessed, and wherein said execution unit accesses said first register set or said second register set as specified by said instruction, reads an operand value from either said first register set or second register set as specified by said instruction, and writes an result value to said first register set or said second register set as specified by said instruction.
摘要翻译：本发明提供一种用于有效利用寄存器文件资源的处理器和方法。处理器包括执行单元，其执行根据指令的至少一个操作; 包括多个第一寄存器的第一寄存器组，每个用于保持整数数据; 以及包括多个第二寄存器的第二寄存器组，每个第二寄存器用于保持所述整数数据并保存浮点数据，其中所述指令指定要访问所述第一和第二寄存器组中的哪一个，并且其中所述执行单元访问所述第一寄存器由所述指令指定的设置或所述第二寄存器，从由所述指令指定的所述第一寄存器组或第二寄存器组读取操作数值，并将结果值写入所述第一寄存器组或所述第二寄存器组，如说了指令

5. 发明公开

EP0911724A3 Process and method for utilizing register file resources 失效
标题翻译：使用寄存器堆的过程和方法
公开(公告)号：EP0911724A3
公开(公告)日：2000-01-12
申请号：EP99102406.8
申请日：1992-07-08
申请人： Seiko Epson Corporation
发明人： Lentz, Derek J. , Nguyen, Le Trong , Garg, Sanjiv , Chen, Sho Long
IPC分类号： G06F9/30
CPC分类号： G06F9/30029 , G06F9/30036 , G06F9/30112 , G06F9/30116 , G06F9/3012 , G06F9/30123 , G06F9/3013 , G06F9/30138 , G06F9/30167 , G06F9/30189 , G06F9/3851
摘要： The invention provides a processor and method for efficiently utilizing register file resources. The processor comprises an execution unit that performs at least one operation according to an instruction; a first register set including a plurality of first registers each for holding integer data; and a second register set including a plurality of second registers each for holding said integer data and for holding floating point data, wherein said instruction specifies which of said first and second register sets is to be accessed, and wherein said execution unit accesses said first register set or said second register set as specified by said instruction, reads an operand value from either said first register set or second register set as specified by said instruction, and writes an result value to said first register set or said second register set as specified by said instruction.

6. 发明授权

EP0834816B1 Microprocessor architecture capable of supporting multiple heterogenous processors 无效转让
标题翻译：微处理器架构能够支持多个异构处理器
公开(公告)号：EP0834816B1
公开(公告)日：2000-01-05
申请号：EP97119364.4
申请日：1992-07-07
申请人： SEIKO EPSON CORPORATION
发明人： Lentz, Derek J. , Hagiwara, Yasuaki , Tang, Cheng-Long , Lau, Te-Li
IPC分类号： G06F15/16
CPC分类号： G06F12/0813 , G06F12/0215 , G06F12/0831 , G06F12/0855 , G06F13/18 , G06F13/4022 , G06F15/167 , G06F15/17 , G06F15/173

7. 发明公开

EP0834816A2 Microprocessor architecture capable of supporting multiple heterogenous processors 无效转让
标题翻译：微处理器架构能够支持多个异构处理器
公开(公告)号：EP0834816A2
公开(公告)日：1998-04-08
申请号：EP97119364.4
申请日：1992-07-07
申请人： SEIKO EPSON CORPORATION
发明人： Lentz, Derek J. , Hagiwara, Yasuaki , Tang, Cheng-Long , Lau, Te-Li
IPC分类号： G06F15/16
CPC分类号： G06F12/0813 , G06F12/0215 , G06F12/0831 , G06F12/0855 , G06F13/18 , G06F13/4022 , G06F15/167 , G06F15/17 , G06F15/173
摘要： A computer system comprising a microprocessor architecture capable of supporting multiple processors comprising a memory array unit (MAU), an MAU system bus comprising data, address and control signal buses, an I/O bus comprising data, address and control signal buses, a plurality of I/O devices and a plurality of microprocessors. Data transfers between data and instruction caches and I/O devices and a memory and other I/O devices are handled using a switch network port data and instruction cache and I/O interface circuits. Access to the memory buses is controlled by arbitration circuits which utilize fixed and dynamic priority schemes. A test and set bypass circuit is provided for preventing a loss of memory bandwidth due to spin-locking. A content addressable memory (CAM) is used to store the address of the semaphore and is checked by devices attempting to access the memory to determine whether the memory is available before an address is placed on the memory bus. Writing to the region protected by the semaphore clears the semaphore and the CAM. A row match comparison circuit is provided for reducing memory latency by giving an increased priority to successive requests for access to memory locations having the same row address. Dynamic switch/port arbitration is provided by changing the priority of the devices based on the intrinsic priority of the device, the number of times that a request has been serviced based on a row match, the number of times that a device has been denied service and the number of times that a device has been serviced. Circuits are also provided for invalidation and intervention such that master and slave devices are operating with the most current information. Circuits are also included to provide dynamic memory refresh on an automatic basis by signals from any one of the processors since each of the processors keep track when a memory refresh has occurred and the lapse time between refresh requests.
摘要翻译：一种计算机系统，包括微处理器架构能够支持多个处理器包括存储器阵列单元（MAU）至MAU系统总线包括数据，地址和控制信号总线到I / O总线包括数据，地址和控制信号总线，多个的I / O设备和微处理器的复数。数据和指令高速缓存和I / O设备和存储器和其他I / O设备之间的数据传输使用的是交换机网络端口的数据和指令高速缓存和I / O接口电路处理。到所述存储器总线的访问由其利用固定仲裁电路和动态优先级方案来控制。

8. 发明授权

EP1385085B1 High performance risc microprocessor architecture 失效
标题翻译：对于RISC微处理器高性能架构
公开(公告)号：EP1385085B1
公开(公告)日：2009-12-02
申请号：EP03024585.6
申请日：1992-07-07
申请人： Seiko Epson Corporation
发明人： Nguyen, Le Trong , Lentz, Derek J. , Miyayama, Yoshiyuki , Garg, Sanjiv , Hagiwara, Yasuaki , Wang, Johannes , Lau, Tei-Li , Trang, Quang H.
IPC分类号： G06F9/38
CPC分类号： G06F9/3822 , G06F9/30061 , G06F9/30072 , G06F9/30112 , G06F9/30116 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30167 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3806 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865 , G06F9/3885

9. 发明授权

EP0886225B1 Microprocessor architecture capable of supporting multiple heterogenous processors 有权转让
标题翻译：微处理器架构能够支持多个不同类型的处理器
公开(公告)号：EP0886225B1
公开(公告)日：2006-09-06
申请号：EP98115836.3
申请日：1992-07-07
申请人： SEIKO EPSON CORPORATION
发明人： Lentz, Derek J. , Hagiwara, Yasuaki , Tang, Cheng-Long , Lau, Te-Li
IPC分类号： G06F15/173
CPC分类号： G06F12/0813 , G06F12/0215 , G06F12/0831 , G06F12/0855 , G06F13/18 , G06F13/4022 , G06F15/167 , G06F15/17 , G06F15/173

10. 发明公开

EP0886209A3 Extensible risc microprocessor architecture 失效
标题翻译： RISC Prozessopr与可扩展的架构
公开(公告)号：EP0886209A3
公开(公告)日：2001-10-10
申请号：EP98119123.2
申请日：1992-07-07
申请人： SEIKO EPSON CORPORATION
发明人： Nguyen, Le Trong , Miyayama, Yoshiyuki , Lentz, Derek J. , Garg, Sanjiv , Hagiwara, Yasuaki , Wang, Johannes , Lau, Tei-Li , Trang, Quang H.
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/30167 , G06F9/30054 , G06F9/30101 , G06F9/30105 , G06F9/30112 , G06F9/30116 , G06F9/3012 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30141 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3814 , G06F9/3824 , G06F9/3828 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3853 , G06F9/3857 , G06F9/3861 , G06F9/3865 , G06F9/3885
摘要： The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of functional units. The fetch unit generally maintains a predetermined number of instructions in an instruction buffer. The execution unit includes an instruction selection unit, coupled to the instruction buffer, for selecting instructions for execution, and a plurality of functional units for performing instruction specified functional operations. A unified instruction scheduler, within the instruction selection unit, initiates the processing of instructions through the functional units when instructions are determined to be available for execution and for which at least one of the functional units implementing a necessary computational function is available. Unified scheduling is performed across mutliple execution data paths, where each execution data path, and corresponding functional units, is generally optimized for the type of computational function that is to be performed on the data: integer, floating point, and boolean. The number, type and computational specifics of the functional units provided in each data path, and as between data paths, are mutually independent.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式