专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

EP1886218B1 HANDLING CACHE MISS IN AN INSTRUCTION CROSSING A CACHE LINE BOUNDARY 有权
公开(公告)号：EP1886218B1
公开(公告)日：2018-10-24
申请号：EP06770879.2
申请日：2006-05-18
申请人： QUALCOMM INCORPORATED
发明人： STEMPEL, Brian, Michael , BRIDGES, Jeffrey, Todd , SMITH, Rodney, Wayne , SARTORIUS, Thomas, Andrew
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30149 , G06F9/30047 , G06F9/30181 , G06F9/3802 , G06F9/3814 , G06F9/3816 , G06F9/3875 , G06F12/0875 , G06F12/0886 , G06F2212/655
摘要： A fetch section of a processor comprises an instruction cache and a pipeline of several stages for obtaining instructions. Instructions may cross cache line boundaries. The pipeline stages process two addresses to recover a complete boundary crossing instruction. During such processing, if the second piece of the instruction is not in the cache, the fetch with regard to the first line is invalidated and recycled. On this first pass, processing of the address for the second part of the instruction is treated as a pre-fetch request to load instruction data to the cache from higher level memory, without passing any of that data to the later stages of the processor. When the first line address passes through the fetch stages again, the second line address follows in the normal order, and both pieces of the instruction are can be fetched from the cache and combined in the normal manner.

2. 发明授权

EP2457168B1 SIGNAL PROCESSING SYSTEM, INTEGRATED CIRCUIT COMPRISING BUFFER CONTROL LOGIC AND METHOD THEREFOR 有权
公开(公告)号：EP2457168B1
公开(公告)日：2018-09-26
申请号：EP09847522.1
申请日：2009-07-20
申请人： NXP USA, Inc.
发明人： ROBERTSON, Alistair , CIRCELLO, Joseph , Maiolani, Mark
IPC分类号： G06F12/127 , G06F12/0862 , G06F12/123 , G06F13/16 , G06F5/00 , G06F12/12 , G06F12/08 , G06F9/38
CPC分类号： G06F12/0862 , G06F9/3804 , G06F9/3814 , G06F12/123 , G06F12/127 , G06F2212/6022
摘要： A signal processing system comprising buffer control logic arranged to allocate a plurality of buffers for the storage of information fetched from at least one memory element. Upon receipt of fetched information to be buffered, the buffer control logic is arranged to categorize the information to be buffered according to at least one of: a first category associated with sequential flow and a second category associated with change of flow, and to prioritize respective buffers from the plurality of buffers storing information relating to the first category associated with sequential flow ahead of buffers storing information relating to the second category associated with change of flow when allocating a buffer for the storage of the fetched information to be buffered.

3. 发明公开

EP2972836A4 A METHOD FOR EMULATING A GUEST CENTRALIZED FLAG ARCHITECTURE BY USING A NATIVE DISTRIBUTED FLAG ARCHITECTURE 有权转让
标题翻译： VERFAHREN ZUR EMULIERUNG EINER ZENTRALISIERTEN GAST-FLAG-ARCHITEKTUR MITHILFE EINER NATIVEN VERTEILTEN FLAG-ARCHITEKTUR
公开(公告)号：EP2972836A4
公开(公告)日：2017-08-02
申请号：EP14770976
申请日：2014-03-12
申请人： INTEL CORP
发明人： ABDALLAH MOHAMMAD
IPC分类号： G06F9/455 , G06F9/30 , G06F9/38 , G06F9/46
CPC分类号： G06F9/30145 , G06F9/3005 , G06F9/30094 , G06F9/3012 , G06F9/30174 , G06F9/3814 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3863 , G06F9/3893
摘要： A method for emulating a guest centralized flag architecture by using a native distributed flag architecture. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks, wherein each of the instruction blocks comprise two half blocks; scheduling the instructions of the instruction block to execute in accordance with a scheduler; and using a distributed flag architecture to emulate a centralized flag architecture for the emulation of guest instruction execution.
摘要翻译：一种通过使用本地分布式标志体系结构来模拟客户集中式标志体系结构的方法。该方法包括使用全局前端来接收传入指令序列; 将指令分组以形成指令块，其中每个指令块包括两个半块; 根据调度器调度指令块的指令以执行; 并使用分布式标志体系结构来模拟用于仿真访客指令执行的集中式标志体系结构。

4. 发明公开

EP3175355A2 METHOD AND APPARATUS FOR INSTRUCTION PREFETCH 有权
标题翻译：用于指导预备的方法和设备
公开(公告)号：EP3175355A2
公开(公告)日：2017-06-07
申请号：EP15801496.9
申请日：2015-07-27
申请人： Linear Algebra Technologies Limited
发明人： BARRY, Brendan , CONNOR, Fergal , O'RIORDAN, Martin , MOLONEY, David , POWER, Sean
IPC分类号： G06F9/30 , G06F5/12 , G06F9/38
CPC分类号： G06F9/3005 , G06F1/0307 , G06F1/035 , G06F9/30149 , G06F9/3814
摘要： A vector processor is disclosed including a variety of variable-length instructions. Computer-implemented methods are disclosed for efficiently carrying out a variety of operations in a time-conscious, memory-efficient, and power-efficient manner. Methods for more efficiently managing a buffer by controlling the threshold based on the length of delay line instructions are disclosed. Methods for disposing multi-type and multi-size operations in hardware are disclosed. Methods for condensing look-up tables are disclosed. Methods for in-line alteration of variables are disclosed.
摘要翻译：公开了一种包括各种可变长度指令的矢量处理器。公开了计算机实现的方法，用于以节省时间，高效率和高效率的方式高效地执行各种操作。公开了通过基于延迟线指令的长度来控制阈值来更高效地管理缓冲器的方法。公开了用硬件处理多种类型和多种尺寸操作的方法。公开了用于冷凝查找表的方法。公开了用于在线改变变量的方法。

5. 发明公开

EP2893460A1 PROCESSOR, SYSTEM, AND METHOD FOR EFFICIENT, HIGH-THROUGHPUT PROCESSING OF TWO-DIMENSIONAL, INTERRELATED DATA SETS 无效转让
标题翻译：处理器，系统和方法高效高性能处理维相关记录
公开(公告)号：EP2893460A1
公开(公告)日：2015-07-15
申请号：EP13753372.5
申请日：2013-08-09
申请人： Mireplica Technology, LLC , Johnson, William, M.
发明人： JOHNSON, William, M.
IPC分类号： G06F15/76 , G06T1/20 , G06T1/60
CPC分类号： G06T1/20 , G06F9/30043 , G06F9/3814 , G06F9/3824 , G06F9/3887 , G06F9/3893 , G06F15/80 , G06T1/60
摘要： Systems, processors and methods are disclosed for organizing processing datapaths to perform operations in parallel while executing a single program. Each datapath executes the same sequence of instructions, using a novel instruction sequencing method. Each datapath is implemented through a processor having a data memory partitioned into identical regions. A master processor fetches instructions and conveys them to the datapath processors. All processors are connected serially by an instruction pipeline, such that instructions are executed in parallel datapaths, with execution in each datapath offset in time by one clock cycle from execution in adjacent datapaths. The system includes an interconnection network that enables full sharing of data in both horizontal and vertical dimensions, with the effect of coupling any datapath to the memory of any other datapath without adding processing cycles in common usage. This approach enables programmable visual computing with throughput approaching that of hardwired solutions.

6. 发明公开

EP2437176A3 System and method of using an N-way cache 审中-公开
标题翻译：系统和方法使用n路高速缓存
公开(公告)号：EP2437176A3
公开(公告)日：2012-08-01
申请号：EP11181782.1
申请日：2008-03-19
申请人： Qualcomm Incorporated
发明人： Venkumahanti, Suresh , Jones, Phil
IPC分类号： G06F12/08 , G06F9/38
CPC分类号： G06F12/0864 , G06F9/3806 , G06F9/381 , G06F9/3814 , G06F2212/1016 , G06F2212/1028 , G06F2212/171 , G06F2212/452 , G06F2212/6082 , Y02D10/13
摘要： A system and method of using an n-way cache are disclosed. In an embodiment, a method includes determining a first way of a first instruction stored in a cache and storing the first way in a list of ways. The method also includes determining a second way of a second instruction stored in the cache and storing the second way in the list of ways. In an embodiment, the first way may be used to access a first cache line containing the first instruction and the second way may be used to access a second cache line containing the second instruction.

7. 发明授权

EP1150213B1 Data processing system and method 有权
标题翻译：数据处理系统和方法
公开(公告)号：EP1150213B1
公开(公告)日：2012-01-25
申请号：EP00109045.5
申请日：2000-04-28
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： Holmberg, Per Anders
IPC分类号： G06F12/08 , G06F9/38
CPC分类号： G06F9/3814 , G06F9/3802 , G06F9/3804 , G06F12/0862 , G06F2212/6028

8. 发明公开

EP2372562A1 Bounding box prefetcher 有权转让
标题翻译：包围盒，预取
公开(公告)号：EP2372562A1
公开(公告)日：2011-10-05
申请号：EP11158696.2
申请日：2011-03-17
申请人： VIA Technologies, Inc.
发明人： Hooker, Rodney E. , Greer, John Michael
IPC分类号： G06F12/08
CPC分类号： G06F9/3814 , G06F12/0862 , G06F2212/602 , G06F2212/6026
摘要： A data prefetcher in a microprocessor having a cache memory receives memory accesses each to an address within a memory block. The access addresses are non-monotonically increasing or decreasing as a function of time. As the accesses are received, the prefetcher maintains a largest address and a smallest address of the accesses and counts of changes to the largest and smallest addresses and maintains a history of recently accessed cache lines implicated by the access addresses within the memory block. The prefetcher also determines a predominant access direction based on the counts and determines a predominant access pattern based on the history. The prefetcher also prefetches into the cache memory, in the predominant access direction according to the predominant access pattern, cache lines of the memory block which the history indicates have not been recently accessed.
摘要翻译：具有高速缓冲存储器的微处理器中的数据预取器接收每个存储器块内的地址的存储器访问。访问地址作为时间的函数是非单调递增或递减的。当接收到访问时，预取器维护访问的最大地址和最小地址以及对最大和最小地址的更改的计数，并且维护由存储器块内的访问地址所牵连的最近访问的高速缓存行的历史。预取器还基于计数确定主要的访问方向，并且基于历史确定主要的访问模式。预取器还根据主要访问模式在主存取方向上预存入高速缓冲存储器，历史指示的存储器块的高速缓存行尚未被最近访问。

9. 发明授权

EP1622029B1 Memory control device, move-in buffer control method 有权
标题翻译：存储器控制单元，用于预取缓冲存储器控制方法
公开(公告)号：EP1622029B1
公开(公告)日：2011-07-06
申请号：EP04257447.5
申请日：2004-11-30
申请人： FUJITSU LIMITED
发明人： Yamazaki, Iwao Fujitsu Limited
IPC分类号： G06F12/08
CPC分类号： G06F12/0859 , G06F9/3802 , G06F9/3814 , G06F9/383 , G06F12/0897

10. 发明授权

EP1826665B1 Data reordering apparatus 有权
标题翻译：数据转换装置
公开(公告)号：EP1826665B1
公开(公告)日：2009-07-15
申请号：EP06116289.7
申请日：2006-06-29
申请人： FUJITSU LIMITED
发明人： Takahashi, Takuji c/o FUJITSU LIMITED
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/3802 , G06F9/3814 , G06F9/384 , G06F9/3855 , G06F9/3857

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式