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1. 发明公开

EP3239837A1 METHOD FOR HANDLING EXCEPTIONS IN EXCEPTION-DRIVEN SYSTEM 有权转让
标题翻译：处理异常驱动系统异常的方法
公开(公告)号：EP3239837A1
公开(公告)日：2017-11-01
申请号：EP17168092.9
申请日：2017-04-25
申请人： Imagination Technologies Limited
发明人： SMITH, Christopher Philip
IPC分类号： G06F9/48 , G06F9/46
CPC分类号： G06F9/3865 , G06F9/461 , G06F9/4812
摘要： A method of processing exceptions in an exception-driven computing-based system that operates in either initialisation mode or exception-driven mode. The method includes, upon detecting an exception has occurred, causing the processor to execute exception handling instructions. When the system is operating in initialisation mode the exception handling instructions invoke a first exception handler that causes a main register set to be saved before processing the exception and restored after processing the exception, and when the system is operating in exception-driven mode the exception handling instructions invoke a second exception handler that does not cause the main register set to be saved and restored. In some examples, the exception handling instructions are initially configured to invoke the first exception handler and are dynamically updated when the system switches from initialisation mode to exception-driven mode to invoke the second exception handler.
摘要翻译：在异常驱动的基于计算的系统中处理异常的方法，可以在初始化模式或异常驱动模式下运行。该方法包括在检测到发生异常时使处理器执行异常处理指令。当系统在初始化模式下运行时，异常处理指令调用第一个异常处理程序，该异常处理程序在处理异常之前导致主寄存器集保存并在处理异常之后恢复，并且当系统以异常驱动模式运行时异常处理指令调用第二个不会导致主寄存器集被保存和恢复的异常处理程序。在一些示例中，异常处理指令最初被配置为调用第一异常处理程序，并在系统从初始化模式切换到异常驱动模式以调用第二异常处理程序时动态更新。

2. 发明授权

EP2776919B1 REDUCING HARDWARE COSTS FOR SUPPORTING MISS LOOKAHEAD 有权
标题翻译：降低支持MISS LOOKAHEAD的硬件成本
公开(公告)号：EP2776919B1
公开(公告)日：2017-09-06
申请号：EP12784387.8
申请日：2012-10-11
申请人： Oracle International Corporation
发明人： CHOU, Yuan, C. , MAHURIN, Eric, W.
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3842 , G06F9/30127 , G06F9/383 , G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3857 , G06F9/3859 , G06F9/3863 , G06F9/3865

3. 发明授权

EP2430522B1 DECIMAL FLOATING-POINT QUANTUM EXCEPTION DETECTION 有权转让
标题翻译：十进制浮点型量子例外检测
公开(公告)号：EP2430522B1
公开(公告)日：2017-07-19
申请号：EP10775821.1
申请日：2010-11-08
申请人： International Business Machines Corporation
发明人： SCHWARZ, Eric, Mark , YEH, Phil , COWLISHAW, Michael, Frederic , MUELLER, Silvia, Melitta
IPC分类号： G06F9/302 , G06F7/491 , G06F7/499 , G06F9/38
CPC分类号： G06F7/49905 , G06F9/30014 , G06F9/30094 , G06F9/3865 , G06F2207/4911

4. 发明公开

EP2963540A1 GENERATION AND UPDATE OF STATUS FLAGS IN A DATA PROCESSOR 审中-公开
标题翻译：艾滋病毒感染者艾滋病毒感染者
公开(公告)号：EP2963540A1
公开(公告)日：2016-01-06
申请号：EP15179650.5
申请日：2009-02-11
申请人： Renesas Electronics Corporation
发明人： ARAKAWA, Fumio
IPC分类号： G06F9/30 , G06F9/302 , G06F9/318 , G06F9/32
CPC分类号： G06F9/30185 , G06F9/3001 , G06F9/30029 , G06F9/30058 , G06F9/30094 , G06F9/3016 , G06F9/30181 , G06F9/3865
摘要： The RISC data processor is based on the idea that in case that there are many flag-generating instructions, the number of flags generated by each instruction is increased so that a decrease of flag-generating instructions exceeds an increase of flag-using instructions in quantity, thereby achieving the decrease in instructions. With the data processor, an instruction for generating flags according to operands' data sizes is defined. To an instruction set handled by the RISC data processor, an instruction capable of executing an operation on operand in more than one data size, which performs a process identical to an operation process conducted on the small-size operand on low-order bits of the large-size operand, and generates flags capable of coping with the respective data sizes regardless of the data size of each operand subjected to the operation is added. Thus, the reduction in instruction code space of the RISC data processor tight in instruction code space can be achieved.
摘要翻译： RISC数据处理器基于以下思想：在存在许多标志生成指令的情况下，由每个指令产生的标志数量增加，使得标志生成指令的减少超过了使用量的指令数量的增加，从而实现指令的减少。使用数据处理器，定义了根据操作数的数据大小生成标志的指令。对于由RISC数据处理器处理的指令集，指令能够执行对多于一个数据大小的操作数的操作，该指令执行与在低位上的小规模操作数上进行的操作处理相同的处理并且生成能够应对各个数据大小的标志，而不管添加了经过操作的每个操作数的数据大小。因此，可以实现RISC数据处理器在指令代码空间中紧缩的指令代码空间的减少。

5. 发明公开

EP2862057A1 PROGRAM INTERRUPTION FILTERING IN TRANSACTIONAL EXECUTION 有权
标题翻译：程序中断过滤器一交易执行
公开(公告)号：EP2862057A1
公开(公告)日：2015-04-22
申请号：EP12878862.7
申请日：2012-11-26
申请人： International Business Machines Corporation
发明人： GREINER, Dan , JACOBI, Christian , SLEGEL, Timothy , MITRAN, Marcel
IPC分类号： G06F9/06 , G06F9/44 , G06F9/45 , G06F9/54
CPC分类号： G06F9/3865 , G06F9/3004 , G06F9/30087 , G06F9/3857 , G06F9/466 , G06F9/4812
摘要： Program exception conditions cause a transaction to abort and typically result in an interruption in which the operating system obtains control. A program interruption filtering control is provided to selectively present the interrupt. That is, the interrupt from the program exception condition may or may not be presented depending at least on the program interruption filtering control and a transaction class associated with the program exception condition. The program interruption filtering control is provided by a TRANSACTION BEGIN instruction.

6. 发明授权

EP1673692B1 SELECTIVELY DEFERRING THE EXECUTION OF INSTRUCTIONS WITH UNRESOLVED DATA DEPENDENCIES 有权转让
标题翻译：选择性复位未解决的数据相关指令的执行
公开(公告)号：EP1673692B1
公开(公告)日：2013-03-13
申请号：EP04784741.3
申请日：2004-09-09
申请人： Oracle America, Inc.
发明人： CHAUDHRY, Shailender , TREMBLAY, Marc
IPC分类号： G06F9/38
CPC分类号： G06F9/3842 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865

7. 发明公开

EP2159710A4 INFORMATION PROCESSOR AND ITS CONTROL METHOD 有权
标题翻译：信息处理器及其控制方法
公开(公告)号：EP2159710A4
公开(公告)日：2012-03-14
申请号：EP07790173
申请日：2007-06-20
申请人： FUJITSU LTD
发明人： KAN RYUJI
IPC分类号： G06F12/16 , G06F11/10 , G06F11/22
CPC分类号： G06F11/1064 , G06F9/30105 , G06F9/30127 , G06F9/30138 , G06F9/3865 , G06F11/2215 , G06F11/2236

8. 发明公开

EP0945787A3 Risc microprocessor architecture implementing fast trap and exception state 失效
标题翻译： Risc-Mikroprozessorarchitektur mit schneller Unterbrechung und Ausnahmezustand
公开(公告)号：EP0945787A3
公开(公告)日：2008-12-31
申请号：EP99112833.1
申请日：1992-07-07
申请人： Seiko Epson Corporation
发明人： Nguyen, Le Trong , Miyayama, Yoshiyuki , Garg, Sanjiv , Trang, Quang H. , Lentz, Derek J. , Hagiwara, Yasuaki , Wang, Johannes , Lau, Tei-li
IPC分类号： G06F9/38
CPC分类号： G06F9/3865 , G06F9/3017 , G06F9/32 , G06F9/322 , G06F9/3802 , G06F9/3804 , G06F9/3814 , G06F9/3836 , G06F9/384 , G06F9/3857 , G06F9/3861 , G06F9/3885 , G06F9/462 , G06F9/4812 , G06F15/7842
摘要： Fast trap mechanism for a microprocessor, wherein a vector trap table is maintained which contains space for a plurality of instructions in each table entry. When a fast trap occurs, control is transferred directly into the table entry corresponding to the trap number. The trap handler can be located completely inside the table entry, or it can transfer control to additional handler code.
摘要翻译：一种用于微处理器的快速陷阱机制，其中维护一个矢量陷阱表，其中包含每个表条目中的多个指令的空间。当发生快速陷阱时，控制将直接传输到与陷阱号对应的表条目中。陷阱处理程序可以完全位于表条目中，也可以将控制权转移到附加处理程序代码。

9. 发明授权

EP1098248B1 A method and apparatus for performing breakpoint instructions in a processor 有权
标题翻译：用于在处理器中执行的代码的断点指令的方法和装置
公开(公告)号：EP1098248B1
公开(公告)日：2004-12-08
申请号：EP00309167.5
申请日：2000-10-18
申请人： Texas Instruments Incorporated
发明人： Matt, David R. , Natarajan, Venkatesh , Karthikeyan, M.R.
IPC分类号： G06F11/00
CPC分类号： G06F11/362 , G06F9/3005 , G06F9/3802 , G06F9/382 , G06F9/3865

10. 发明授权

EP0951672B1 COMPUTER ARCHITECTURE FOR THE DEFERRAL OF EXCEPTIONS OF STATICAL SPECULATIVE INSTRUCTIONS 有权
标题翻译：计算机体系结构推迟异常的静态投机COMMANDS
公开(公告)号：EP0951672B1
公开(公告)日：2003-02-19
申请号：EP98952242.0
申请日：1998-10-09
申请人： Institute for the Development of Emerging Architectures, L.L.C.
发明人： ROSS, Jonathan, K. , MILLS, Jack, D. , HAYS, James, O. , BURGER, Stephen, G. , MORRIS, Dale, C. , THOMPSON, Carol, L. , GUPTA, Rajiv , FREUDENBERGER, Stefan, M. , HAMMOND, Gary , KLING, Ralph, M.
IPC分类号： G06F9/38
CPC分类号： G06F9/3865 , G06F9/3842
摘要： The inventive system (300) and method allows for software control (320) of hardware (330) deferral of exceptions in speculative operations (104), and comprises three components. The first component is processor stored information (107) which reflects the code generation strategy of applications and is used by hardware and the operating system to control exception deferral. The second component is processor stored information (105) set by the operating system to specify to hardware which type of faults should be automatically deferred. The third component is further processor stored information (102) which indicates to the hardware to defer certain exception causing aspects of the speculative operation, while performing other non excepting aspects of the speculative operation. The stored information is set after the operating system exception handler (200) has unsuccessfully attempted fault resolution (213).

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