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1. 发明公开

EP3355198A3 RUNTIME ADDRESS DISAMBIGUATION IN ACCELERATION HARDWARE 审中-公开
公开(公告)号：EP3355198A3
公开(公告)日：2018-10-31
申请号：EP17207172.2
申请日：2017-12-13
申请人： INTEL Corporation
发明人： FLEMING, JR., Kermin Elliott , STEELY JR., Simon C. , GLOSSOP, Kent D.
IPC分类号： G06F13/16 , G06F9/38 , G06F9/30 , G06F3/06
CPC分类号： G06F3/0619 , G06F3/065 , G06F3/067 , G06F9/30043 , G06F9/3826 , G06F9/3834 , G06F12/00 , G06F13/16
摘要： An integrated circuit includes a processor to execute instructions and to interact with memory, and acceleration hardware, to execute a sub-program corresponding to instructions. A set of input queues includes a store address queue to receive, from the acceleration hardware, a first address of the memory, the first address associated with a store operation and a store data queue to receive, from the acceleration hardware, first data to be stored at the first address of the memory. The set of input queues also includes a completion queue to buffer response data for a load operation. A disambiguator circuit, coupled to the set of input queues and the memory, is to, responsive to determining the load operation, which succeeds the store operation, has an address conflict with the first address, copy the first data from the store data queue into the completion queue for the load operation.

2. 发明公开

EP3304283A1 SYSTEM, APPARATUS, AND METHOD FOR TEMPORARY LOAD INSTRUCTION 有权
标题翻译：用于临时加载指令的系统，装置和方法
公开(公告)号：EP3304283A1
公开(公告)日：2018-04-11
申请号：EP16725336.8
申请日：2016-05-17
申请人： Qualcomm Incorporated
发明人： MAHURIN, Eric , GOLAB, Jakub Pawel
IPC分类号： G06F9/38
CPC分类号： G06F9/30043 , G06F1/10 , G06F9/3824 , G06F9/3826 , G06F9/383 , G06F9/3853
摘要： A transient load instruction for a processor may include a transient or temporary load instruction that is executed in parallel with a plurality of input operands. The temporary load instruction loads a memory value into a temporary location for use within the instruction packet. According to some examples, a VLIW based microprocessor architecture may include a temporary cache for use in writing/reading a temporary memory value during a single VLIW packet cycle. The temporary cache is different from the normal register bank that does not allow writing and then reading the value just written during the same VLIW packet cycle.

3. 发明公开

EP3271815A1 RESERVATION STATION CIRCUIT FOR EXECUTION OF LOOP INSTRUCTIONS BY OUT-OF-ORDER PROCESSOR, D RELATED METHOD, AND COMPUTER-READABLE MEDIA 审中-公开
标题翻译：无序处理器执行循环指令的预约站电路，D相关方法和计算机可读介质
公开(公告)号：EP3271815A1
公开(公告)日：2018-01-24
申请号：EP16711395.0
申请日：2016-02-25
申请人： Qualcomm Incorporated
发明人： CHATHA, Karamvir, Singh , YEN, Kevin, Weikong , OH, Rick, Seokyong , DANIELS, John, Paul , HOWARD, Michael, Alexander , PEREZ, Francisco, Miranda , ARVELO, Eladio, Clemente , CHAUHAN, Ramesh, Chandra
IPC分类号： G06F9/38
CPC分类号： G06F9/3855 , G06F9/325 , G06F9/381 , G06F9/3826 , G06F9/3832 , G06F9/3836 , G06F9/3838 , G06F9/3867 , G06F15/825
摘要： Providing lower-overhead management of dataflow execution of loop instructions by out-of-order processors (OOPs), and related circuits, methods, and computer-readable media are disclosed. In one aspect, a reservation station circuit including multiple reservation station segments, each storing a loop instruction of a computer program loop is provided. Each reservation station segment also stores an instruction execution credit indicator indicative of whether the corresponding loop instruction may be provided for dataflow execution. The reservation station circuit further includes a dataflow monitor providing an entry for each loop instruction, each entry comprising a consumer count indicator and a reservation station (RS) tag count indicator. The dataflow monitor is configured to determine whether all consumer instructions of a loop instruction have executed based on the consumer count indicator and the RS tag count indicator for the loop instruction. If so, the dataflow monitor issues an instruction execution credit to the loop instruction.

4. 发明公开

EP3256942A1 RESERVATION STATION HAVING INSTRUCTION WITH SELECTIVE USE OF SPECIAL REGISTER AS A SOURCE OPERAND ACCORDING TO INSTRUCTION BITS 审中-公开
标题翻译：根据指示位选择使用特殊注册表作为源操作的指令的预约站
公开(公告)号：EP3256942A1
公开(公告)日：2017-12-20
申请号：EP16702472.8
申请日：2016-01-15
申请人： Qualcomm Incorporated
发明人： WRIGHT, Gregory Michael
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3859 , G06F9/30101 , G06F9/30163 , G06F9/30185 , G06F9/3826 , G06F9/3836 , G06F9/3844 , G06F9/3853
摘要： A computer processor core for fan out of a result of a producer instruction, using first through fourth sets of memory cells and circuitry. The first set of memory cells is a special register configured to store the result of a producer instruction. The second to fourth sets are a reservation station record of a consumer instruction. The second set is configured to store an operation code of the consumer instruction. The third set is configured to store operand selection information of the consumer instruction. The fourth set is configured to store an operand for the consumer instruction. The circuitry can be configured to connect the fourth set to an execution unit and to cause, in response to information in the third set, the execution unit to be configured to selectively receive a content of the first set as the operand for the second instruction. A format of the consumer instruction includes sets of bits designated for the operation code and for the operand selection information.

5. 发明公开

EP3103011A1 OPPORTUNITY MULTITHREADING IN A MULTITHREADED PROCESSOR WITH INSTRUCTION CHAINING CAPABILITY 审中-公开
标题翻译：多样性 - 多元化北美多种多样的食品添加剂麻省理工学院ANWEISUNGSVERKETTUNGSKAPAZITÄT
公开(公告)号：EP3103011A1
公开(公告)日：2016-12-14
申请号：EP15746129.4
申请日：2015-02-03
申请人： Optimum Semiconductor Technologies, Inc.
发明人： WANG, Shenghong , GLOSSNER, C., John , NACER, Gary, J.
IPC分类号： G06F9/30
CPC分类号： G06F9/3826 , G06F9/3818 , G06F9/382 , G06F9/3822 , G06F9/3838 , G06F9/3851 , G06F9/3853 , G06F9/46
摘要： A computing device determines that a current software thread of a plurality of software threads having an issuing sequence does not have a first instruction waiting to be issued to a hardware thread during a clock cycle. The computing device identifies one or more alternative software threads in the issuing sequence having instructions waiting to be issued. The computing device selects, during the clock cycle by the computing device, a second instruction from a second software thread among the one or more alternative software threads in view of determining that the second instruction has no dependencies with any other instructions among the instructions waiting to be issued. Dependencies are identified by the computing device in view of the values of a chaining bit extracted from each of the instructions waiting to be issued. The computing device issues the second instruction to the hardware thread.
摘要翻译：计算设备确定具有发布序列的多个软件线程的当前软件线程在时钟周期期间不具有等待发送到硬件线程的第一指令。计算设备识别发布序列中的一个或多个备选软件线程，其中有等待发出的指令。考虑到在等待等待的指令中确定第二指令与任何其他指令没有任何依赖关系，计算设备在计算设备的时钟周期期间选择来自一个或多个替代软件线程中的第二软件线程的第二指令被发行。考虑到从每个等待发出的指令提取的链接位的值，计算设备识别依赖关系。计算设备向硬件线程发出第二条指令。

6. 发明公开

EP2862087A4 A DISAMBIGUATION-FREE OUT OF ORDER LOAD STORE QUEUE 审中-公开
标题翻译： EINDEUTIGEIRREGULÄRELADE- / SPEICHERWARTESCHLANGE
公开(公告)号：EP2862087A4
公开(公告)日：2016-12-14
申请号：EP13805015
申请日：2013-06-14
申请人： SOFT MACHINES INC
发明人： ABDALLAH MOHAMMAD
IPC分类号： G06F12/02 , G06F9/38
CPC分类号： G06F9/30043 , G06F9/30032 , G06F9/3826 , G06F9/3834 , G06F9/3855 , G06F9/3857

7. 发明公开

EP3096222A1 PIPELINED CASCADED DIGITAL SIGNAL PROCESSING STRUCTURES AND METHODS 有权
标题翻译： KASKADIERTE管道数字数字信号处理器
公开(公告)号：EP3096222A1
公开(公告)日：2016-11-23
申请号：EP16170576.9
申请日：2016-05-20
申请人： Altera Corporation
发明人： Langhammer, Martin
IPC分类号： G06F7/544
CPC分类号： G06F9/3869 , G06F7/523 , G06F7/5443 , G06F9/3001 , G06F9/30105 , G06F9/3012 , G06F9/3826 , G06F9/3867 , G06F15/80 , G06F2207/3868 , G06F2207/3888 , G06F2207/3892
摘要： Circuitry operating under a floating-point mode or a fixed-point mode includes a first circuit accepting a first data input and generating a first data output. The first circuit includes a first arithmetic element accepting the first data input, a plurality of pipeline registers disposed in connection with the first arithmetic element, and a cascade register that outputs the first data output. The circuitry further includes a second circuit accepting a second data input and generating a second data output. The second circuit is cascaded to the first circuit such that the first data output is connected to the second data input via the cascade register. The cascade register is selectively bypassed when the first circuit is operated under the fixed-point mode.
摘要翻译：在浮点模式或定点模式下运行的电路包括接受第一数据输入并产生第一数据输出的第一电路。第一电路包括接受第一数据输入的第一算术元件，与第一算术元件连接设置的多个流水线寄存器，以及输出第一数据输出的级联寄存器。电路还包括接受第二数据输入并产生第二数据输出的第二电路。第二电路级联到第一电路，使得第一数据输出经由级联寄存器连接到第二数据输入。当第一电路在定点模式下运行时，级联寄存器被选择性旁路。

8. 发明公开

EP3014468A1 METHOD AND APPARATUS FOR ASYNCHRONOUS PROCESSOR WITH AUXILIARY ASYNCHRONOUS VECTOR PROCESSOR 审中-公开
标题翻译：方法和设备异步处理器与附加异步向量处理器
公开(公告)号：EP3014468A1
公开(公告)日：2016-05-04
申请号：EP14842884.0
申请日：2014-09-08
申请人： Huawei Technologies Co., Ltd.
发明人： ZHANG, Qifan , SHI, Wuxian , GE, Yiqun , HUANG, Tao , TONG, Wen
IPC分类号： G06F15/163
CPC分类号： G06F9/30145 , G06F1/08 , G06F1/10 , G06F9/30036 , G06F9/30189 , G06F9/3826 , G06F9/3828 , G06F9/3836 , G06F9/3851 , G06F9/3853 , G06F9/3871 , G06F9/3877 , G06F9/3885 , G06F9/3889 , G06F9/3891 , G06F9/5011 , G06F15/8007 , G06F15/8053 , G06F15/8092 , G06F2009/3883
摘要： A clock-less asynchronous processing circuit or system is configured to operation in a plurality of modes. In an initialization mode (e.g., reset, initialization, boot up), a self-clocked generator associated with the asynchronous circuit is configured to generate an active complete signal (to latch output processed data) within a first period of time after receiving a trigger signal. In a normal mode, the self-clocked generator is configured to generate the active complete signal within a second period of time after receiving the trigger signal. In one embodiment, during the initialization mode, the asynchronous circuit latches the output slower than when in the normal mode.

9. 发明公开

EP2862072A1 A LOAD STORE BUFFER AGNOSTIC TO THREADS IMPLEMENTING FORWARDING FROM DIFFERENT THREADS BASED ON STORE SENIORITY 有权转让
标题翻译：线程AGNOSTIC LAST存储缓冲器进行循环不同的线程对记忆优先权基础
公开(公告)号：EP2862072A1
公开(公告)日：2015-04-22
申请号：EP13805130.5
申请日：2013-06-10
申请人： Soft Machines, Inc.
发明人： ABDALLAH, Mohammad
IPC分类号： G06F9/46 , G06F9/38
CPC分类号： G06F9/30043 , G06F9/30047 , G06F9/3009 , G06F9/3017 , G06F9/3826 , G06F9/3834 , G06F9/3851 , G06F12/1425 , G06F2212/1052
摘要： In a processor, a thread agnostic unified store queue and a unified load queue method for out of order loads in a memory consistency model using shared memory resources. The method includes implementing a memory resource that can be accessed by a plurality of asynchronous cores, wherein the plurality of cores share a unified store queue and a unified load queue; and implementing an access mask that functions by tracking which words of a cache line are accessed via a load, wherein the cache line includes the memory resource, wherein the load sets a mask bit within the access mask when accessing a word of the cache line, and wherein the mask bit blocks accesses from other loads from a plurality of cores. The method further includes checking the access mask upon execution of subsequent stores from the plurality of cores to the cache line, wherein stores from different threads can forward to loads of different threads while still maintaining in order memory consistency semantics; and causing a miss prediction when a subsequent store to the portion of the cache line sees a prior mark from a load in the access mask, wherein the subsequent store will signal a load queue entry corresponding to that load by using a tracker register and a thread ID register.

10. 发明公开

EP2862068A1 REORDERED SPECULATIVE INSTRUCTION SEQUENCES WITH A DISAMBIGUATION-FREE OUT OF ORDER LOAD STORE QUEUE 有权转让
标题翻译： NEUGEORDNETE SPEKULATIVE BEFEHLSFOLGEN MIT EINER EINDEUTIGENIRREGULÄRENLADE- / SPEICHERWARTESCHLANGE
公开(公告)号：EP2862068A1
公开(公告)日：2015-04-22
申请号：EP13803665.2
申请日：2013-06-10
申请人： Soft Machines, Inc.
发明人： ABDALLAH, Mohammad
IPC分类号： G06F9/46 , G06F9/38
CPC分类号： G06F9/30043 , G06F9/30032 , G06F9/30047 , G06F9/3017 , G06F9/30185 , G06F9/3826 , G06F9/3834 , G06F9/3842 , G06F9/3855 , G06F9/3857
摘要： In a processor, a disambiguation-free out of order load store queue method. The method includes implementing a memory resource that can be accessed by a plurality of asynchronous cores; implementing a store retirement buffer, wherein stores from a store queue have entries in the store retirement buffer in original program order; and implementing speculative execution, wherein results of speculative execution can be saved in the store retirement/reorder buffer as a speculative state. The method further includes, upon dispatch of a subsequent load from a load queue, searching the store retirement buffer for address matching; and, in cases where there are a plurality of address matches, locating a correct forwarding entry by scanning for the store retirement buffer for a first match, and forwarding data from the first match to the subsequent load. Once speculative outcomes are known, the speculative state is retired to memory.
摘要翻译：在一个处理器中，一个无歧义的乱序加载存储队列方法。该方法包括实现可由多个异步核心访问的存储器资源; 实施商店退休缓冲器，其中来自商店队列的商店在原始程序顺序中具有商店退休缓冲器中的条目; 并执行推测执行，其中推测执行的结果可以作为推测状态保存在商店退休/重新排序缓冲器中。该方法还包括：在从负载队列发送后续负载时，搜索商店退出缓冲区以进行地址匹配; 并且在存在多个地址匹配的情况下，通过扫描第一匹配的商店退出缓冲器来定位正确的转发条目，以及将数据从第一匹配转发到后续加载。一旦推测结果已知，投机状态就会退休至记忆。

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