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1. 发明公开

EP3198729A4 TECHNOLOGIES FOR EFFICIENT LZ77-BASED DATA DECOMPRESSION 审中-公开
公开(公告)号：EP3198729A4
公开(公告)日：2018-06-13
申请号：EP15843355
申请日：2015-08-24
申请人： INTEL CORP
发明人： GOPAL VINODH , GULLEY SEAN M , GUILFORD JAMES D
IPC分类号： H03M7/30
CPC分类号： H03M7/3086 , G06F3/0604 , G06F3/064 , G06F3/065 , G06F3/0673 , G06F9/3818 , G06F9/3863 , G06F12/023 , G06F12/0875 , G06F2212/1044 , G06F2212/452 , H03M7/3091 , H03M7/6005 , H03M7/6017
摘要： Technologies for data decompression include a computing device that reads a symbol tag byte from an input stream. The computing device determines whether the symbol can be decoded using a fast-path routine, and if not, executes a slow-path routine to decompress the symbol. The slow-path routine may include data-dependent branch instructions that may be unpredictable using branch prediction hardware. For the fast-path routine, the computing device determines a next symbol increment value, a literal increment value, a data length, and an offset based on the tag byte, without executing an unpredictable branch instruction. The computing device sets a source pointer to either literal data or reference data as a function of the tag byte, without executing an unpredictable branch instruction. The computing device may set the source pointer using a conditional move instruction. The computing device copies the data and processes remaining symbols. Other embodiments are described and claimed.

2. 发明授权

EP1984814B1 METHOD AND APPARATUS FOR ENFORCING MEMORY REFERENCE ORDERING REQUIREMENTS AT THE L1 CACHE LEVEL 有权转让
标题翻译：用于在L1高速缓存级别上执行存储器参考订购要求的方法和设备
公开(公告)号：EP1984814B1
公开(公告)日：2018-03-28
申请号：EP07717171.8
申请日：2007-02-02
申请人： Oracle America, Inc.
发明人： CHAUDHRY, Shailender , TREMBLAY, Marc
IPC分类号： G06F9/38
CPC分类号： G06F9/3834 , G06F9/30189 , G06F9/3842 , G06F9/3863
摘要： One embodiment of the present invention provides a system that enforces memory reference ordering requirements, such as Total Store Ordering (TSO), at a Level 1 (L1) cache in a multiprocessor. During operation, while executing instructions in a speculative-execution mode, the system receives an invalidation signal for a cache line at the L1 cache wherein the invalidation signal is received from a cache-coherence system within the multiprocessor. In response to the invalidation signal, if the cache line exists in the L1 cache, the system examines a load-mark in the cache line, wherein the load-mark being set indicates that the cache line has been loaded from during speculative execution. If the load-mark is set, the system fails the speculative-execution mode and resumes a normal-execution mode from a checkpoint. By failing the speculative-execution mode, the system ensures that a potential update to the cache line indicated by the invalidation signal will not cause the memory reference ordering requirements to be violated during the speculative-execution mode.

3. 发明公开

EP2908242A3 Processor that recovers from excessive approximate computing error 有权转让
标题翻译：处理器从过度的近似计算错误中恢复
公开(公告)号：EP2908242A3
公开(公告)日：2018-01-24
申请号：EP15154560.5
申请日：2015-02-10
申请人： VIA Alliance Semiconductor Co., Ltd.
发明人： Henry, G Glenn , Parks, Terry , Hooker, Rodney E
IPC分类号： G06F9/38
CPC分类号： G06F11/1446 , G06F9/30014 , G06F9/30185 , G06F9/38 , G06F9/3863 , G06F11/0754 , G06F11/0793 , G06F11/1402 , G06F11/1435 , G06F2201/84
摘要： A processor includes a storage configured to receive a snapshot of a state of the processor prior to performing a set of computations in an approximating manner. The processor also includes an indicator that indicates an amount of error accumulated while the set of computations is performed in the approximating manner. When the processor detects that the amount of error accumulated has exceeded an error bound, the processor is configured to restore the state of the processor to the snapshot from the storage.
摘要翻译：处理器包括存储器，该存储器被配置为在以近似方式执行一组计算之前接收处理器的状态的快照。处理器还包括指示器，该指示器指示以近似方式执行该组计算时累积的误差量。当处理器检测到累积的错误量已超过错误界限时，处理器被配置成将处理器的状态恢复到来自存储器的快照。

4. 发明公开

EP3060979A4 PROCESSOR AND METHODS FOR IMMEDIATE HANDLING AND FLAG HANDLING 有权转让
标题翻译： PROZESSOR UND VERFAHREN ZUR SOFORTIGEN MARKIERUNGSHANDHABUNG
公开(公告)号：EP3060979A4
公开(公告)日：2017-07-05
申请号：EP14855674
申请日：2014-10-24
申请人： ADVANCED MICRO DEVICES INC
发明人： VENKATACHAR ASHOK , PUNUKOLLU KARTHIK , AREKAPUDI SRIKANTH , CHITNIS SAMIR A , TALPES EMIL
IPC分类号： G06F9/06
CPC分类号： G06F9/384 , G06F9/30094 , G06F9/30098 , G06F9/30167 , G06F9/3838 , G06F9/3863 , G06F9/3865
摘要： Described herein are methods and processors for flag renaming in groups to eliminate dependencies of instructions. Decoder and execution units in the processor may be configured to rename flags into groups that allow each group to be treated separately as appropriate. This flag renaming eliminates flag dependencies with respect to instructions. This allows an instruction to write exactly the flags that the instruction wants without having to create merge dependencies. Methods and processors are provided for handling immediate values embedded in instructions. A 16 bit immediate bus and a 4 bit encoding/control bus are added at the interface between decode and execution units. For an 8 or 12 bit immediate, the upper 4 bits of the immediate bus contain the encoding bits. For a 16 bit immediate, the encoding/control bus contains the encoding bits. The encoding/control bus indicates when to look at the top four bits of the immediate bus.
摘要翻译：这里描述的是用于组中的标志重命名以消除指令的依赖性的方法和处理器。处理器中的解码器和执行单元可以被配置为将标志重命名为组，从而允许每个组适当分开处理。该标志重命名消除了关于指令的标志依赖性。这允许指令精确地写入指令想要的标志而不必创建合并依赖关系。提供方法和处理器用于处理指令中嵌入的即时值。解码和执行单元之间的接口增加了一个16位立即总线和一个4位编码/控制总线。对于立即数8或12位，立即总线的高4位包含编码位。对于16位立即数，编码/控制总线包含编码位。编码/控制总线指示何时查看直接总线的前四位。

5. 发明公开

EP3115888A1 CHECK POINTING A SHIFT REGISTER 审中-公开
标题翻译： ERSTELLUNG VONPRÜFPUNKTENEINES SCHIEBEREGISTERS
公开(公告)号：EP3115888A1
公开(公告)日：2017-01-11
申请号：EP16178017.6
申请日：2016-07-05
申请人： Imagination Technologies Limited
发明人： DAY, Philip
IPC分类号： G06F9/38
CPC分类号： G06F3/065 , G06F3/0619 , G06F3/0656 , G06F3/0673 , G06F5/01 , G06F5/017 , G06F9/30116 , G06F9/30134 , G06F9/3844 , G06F9/3851 , G06F9/3863
摘要： A hardware structure provides a way for check pointing a main shift register one or more times. The hardware structure includes an extended shift register used to store the data elements most recently shifted onto the main shift register which has an extra data position for each check point. An update history shift register has a data position for each check point which is used to store information indicating whether the extended shift register was updated. Check point generation logic derives each check point by selecting a subset of the data elements stored in the extended shift register based on the information stored in the update history shift register.
摘要翻译：硬件结构提供了一种或多种检查指向主移位寄存器的方法。硬件结构包括扩展移位寄存器，用于存储最近移到主移位寄存器上的数据元素，该移位寄存器具有用于每个检查点的额外数据位置。更新历史移位寄存器具有用于每个检查点的数据位置，用于存储指示扩展移位寄存器是否被更新的信息。检查点生成逻辑通过基于存储在更新历史移位寄存器中的信息来选择存储在扩展移位寄存器中的数据元素的子集来导出每个检查点。

6. 发明公开

EP3043269A1 SHARING VIRTUAL FUNCTIONS IN A SHARED VIRTUAL MEMORY BETWEEN HETEROGENEOUS PROCESSORS OF A COMPUTING PLATFORM 有权
标题翻译：共享虚拟函数的具有计算机平台的异构处理器之间的接头虚拟存储器
公开(公告)号：EP3043269A1
公开(公告)日：2016-07-13
申请号：EP16158622.7
申请日：2010-09-24
申请人： Intel Corporation
发明人： YAN, Shoumeng , LUO, Sai , ZHOU, Xiaocheng , GAO, Ying , CHEN, Hu , SAHA, Bratin
IPC分类号： G06F15/167 , G06F9/54
CPC分类号： G06F12/1072 , G06F8/447 , G06F9/3863 , G06F9/3885 , G06F9/548 , G06F2212/657
摘要： A computing platform may include heterogeneous processors (e.g., CPU and a GPU) to support sharing of virtual functions between such processors. In one embodiment, a CPU side vtable pointer used to access a shared object from the CPU 110 may be used to determine a GPU vtable if a GPU-side table exists. In other embodiment, a shared non-coherent region, which may not maintain data consistency, may be created within the shared virtual memory. The CPU and the GPU side data stored within the shared non-coherent region may have a same address as seen from the CPU and the GPU side. However, the contents of the CPU-side data may be different from that of GPU-side data as shared virtual memory may not maintain coherency during the run-time. In one embodiment, the vptr may be modified to point to the CPU vtable and GPU vtable stored in the shared virtual memory.
摘要翻译：一种计算平台可以包括异构处理器（例如，CPU和GPU）来支持寻求处理器之间的虚函数共享。在一个，用于从CPU 110访问的共享对象中的CPU实施方式侧虚表指针可以被用于确定性地挖掘一个GPU虚函数表，如果GPU侧表中存在。在其它，实施例的共享的非相干区域，这可能不保持数据的一致性，可以在共享虚拟存储器内被创建。从CPU和GPU侧看到的CPU和存储在共享非相干区域内的GPU侧数据可具有相同的地址。然而，CPU侧的数据的内容可以是不同的，从做GPU侧数据作为在运行时间共享虚拟存储器可能无法保持一致性。在一个中，实施方式的vptr可被修改为指向存储在共享虚拟存储器中的CPU和GPU的vtable虚表。

7. 发明授权

EP1703375B1 Real-time control apparatus having a multi-thread processor 有权转让
标题翻译：与多线程处理器的实时控制器
公开(公告)号：EP1703375B1
公开(公告)日：2015-08-26
申请号：EP06005552.2
申请日：2006-03-17
申请人： Marvell World Trade Ltd.
发明人： Sehat, Sutardja
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/3012 , G06F9/30123 , G06F9/3863 , G06F9/3867 , G06F9/462

8. 发明公开

EP2908242A2 Processor that recovers from excessive approximate computing error 有权转让
标题翻译： Prozessor，der sich von einemübermäßigenAnnäherungsberechnungsfehlererholt
公开(公告)号：EP2908242A2
公开(公告)日：2015-08-19
申请号：EP15154560.5
申请日：2015-02-10
申请人： VIA Technologies, Inc.
发明人： Henry, G Glenn , Parks, Terry , Hooker, Rodney E
IPC分类号： G06F9/38
CPC分类号： G06F11/1446 , G06F9/30014 , G06F9/30185 , G06F9/38 , G06F9/3863 , G06F11/0754 , G06F11/0793 , G06F11/1402 , G06F11/1435 , G06F2201/84
摘要： A processor includes a storage configured to receive a snapshot of a state of the processor prior to performing a set of computations in an approximating manner. The processor also includes an indicator that indicates an amount of error accumulated while the set of computations is performed in the approximating manner. When the processor detects that the amount of error accumulated has exceeded an error bound, the processor is configured to restore the state of the processor to the snapshot from the storage.
摘要翻译：处理器包括被配置为在以近似方式执行一组计算之前接收处理器的状态的快照的存储器。处理器还包括指示器，其指示以近似方式执行计算集合时累积的误差量。当处理器检测到累积的错误量超过了错误限制时，处理器被配置为将处理器的状态从存储恢复到快照。

9. 发明授权

EP2724228B1 TRANSACTION ABORT INSTRUCTION 有权
标题翻译：命令取消事务
公开(公告)号：EP2724228B1
公开(公告)日：2015-07-01
申请号：EP13724242.6
申请日：2013-05-17
申请人： International Business Machines Corporation
发明人： GREINER, Dan , JACOBI, Christian , SLEGEL, Timothy , MITRAN, Marcel
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3861 , G06F9/30087 , G06F9/30101 , G06F9/3834 , G06F9/3859 , G06F9/3863

10. 发明公开

EP2862092A1 SAVING/RESTORING SELECTED REGISTERS IN TRANSACTIONAL PROCESSING 有权
标题翻译： SPEICHERUNG / WIEDERHERSTELLUNGAUSGEWÄHLTER注册在DER TRANSAKTIONALEN VERARBEITUNG
公开(公告)号：EP2862092A1
公开(公告)日：2015-04-22
申请号：EP12878930.2
申请日：2012-11-26
申请人： International Business Machines Corporation
发明人： GREINER, Dan , JACOBI, Christian , SLEGEL, Timothy
IPC分类号： G06F13/40 , G06F9/308 , G06F9/312
CPC分类号： G06F9/3861 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3859 , G06F9/3863 , G06F9/462 , G06F9/466 , G06F9/467
摘要： A TRANSACTION BEGIN instruction begins execution of a transaction and includes a general register save mask having bits, that when set, indicate registers to be saved in the event the transaction is aborted. At the beginning of the transaction, contents of the registers are saved in memory not accessible to the program, and if the transaction is aborted, the saved contents are copied to the registers.
摘要翻译：一个TRANSACTION BEGIN指令开始执行一个事务，并且包括具有位的通用寄存器保存掩码，当设置时，指示在事务中止的情况下要保存的寄存器。在交易开始时，寄存器的内容保存在程序无法访问的存储器中，如果事务中止，则将保存的内容复制到寄存器中。

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