专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

EP4208792B1 TRACKING REPEATED READS TO GUIDE DYNAMIC SELECTION OF CACHE COHERENCE PROTOCOLS IN PROCESSOR-BASED DEVICES 有权
公开(公告)号：EP4208792B1
公开(公告)日：2024-06-26
申请号：EP21733345.9
申请日：2021-05-28
IPC分类号： G06F12/0811 , G06F12/0815 , G06F12/0831
CPC分类号： G06F12/0811 , G06F12/0815 , G06F12/0831

2. 发明授权

EP2786255B1 A DRAM CACHE WITH TAGS AND DATA JOINTLY STORED IN PHYSICAL ROWS 有权转让
公开(公告)号：EP2786255B1
公开(公告)日：2018-11-14
申请号：EP12795975.7
申请日：2012-11-21
申请人： Advanced Micro Devices, Inc.
发明人： LOH, Gabriel H. , HILL, Mark D.
IPC分类号： G06F12/0879 , G06F12/0864 , G06F12/0831 , G06F12/0893 , G06F12/123 , G11C7/10
CPC分类号： G06F12/0893 , G06F12/0831 , G06F12/0864 , G06F12/0879 , G06F12/123 , Y02D10/13
摘要： A system and method for efficient cache data access in a large row-based memory of a computing system. A computing system includes a processing unit and an integrated three-dimensional (3D) dynamic random access memory (DRAM). The processing unit uses the 3D DRAM as a cache. Each row of the multiple rows in the memory array banks of the 3D DRAM stores at least multiple cache tags and multiple corresponding cache lines indicated by the multiple cache tags. In response to receiving a memory request from the processing unit, the 3D DRAM performs a memory access according to the received memory request on a given cache line indicated by a cache tag within the received memory request. Rather than utilizing multiple DRAM transactions, a single, complex DRAM transaction may be used to reduce latency and power consumption.

3. 发明公开

EP3382548A1 SHARED MEMORY FOR INTELLIGENT NETWORK INTERFACE CARDS 审中-公开
公开(公告)号：EP3382548A1
公开(公告)日：2018-10-03
申请号：EP18154434.7
申请日：2018-01-31
申请人： Intel Corporation
发明人： BERNAT, Francesc Guim , BARRAGAN, Daniel Rivas , DOSHI, Kshitij A. , SCHMISSEUR, Mark A.
IPC分类号： G06F9/54 , H04L29/12 , H04L12/46 , G06F12/0817
CPC分类号： G06F13/1663 , G06F9/544 , G06F9/545 , G06F12/082 , G06F12/0822 , G06F12/0831 , G06F12/1018 , G06F2212/1024 , G06F2212/621 , H04L12/4625 , H04L49/9068
摘要： In an example, there is disclosed a host-fabric interface (HFI), including: an interconnect interface to communicatively couple the HFI to an interconnect; a network interface to communicatively couple the HFI to a network; network interface logic to provide communication between the interconnect and the network; a coprocessor configured to provide an offloaded function for the network; a memory; and a caching agent configured to: designate a region of the memory as a shared memory between the HFI and a core communicatively coupled to the HFI via the interconnect; receive a memory operation directed to the shared memory; and issue a memory instruction to the memory according to the memory operation.

4. 发明授权

EP3046035B1 REQUEST RESPONSE METHOD AND DEVICE BASED ON A NODE CONTROLLER 有权
标题翻译：基于节点控制器的请求响应方法和装置
公开(公告)号：EP3046035B1
公开(公告)日：2018-04-25
申请号：EP14843838.5
申请日：2014-09-05
申请人： Huawei Technologies Co., Ltd.
发明人： WANG, Gongyi , CHEN, Ben , ZHAO, Yafei
IPC分类号： G06F3/06 , G06F9/54 , G06F12/0817
CPC分类号： G06F3/0638 , G06F3/0604 , G06F3/0673 , G06F9/54 , G06F12/0813 , G06F12/0817 , G06F12/0831 , G06F2212/1048
摘要： Embodiments of the present invention disclose a node controller-based request responding method and apparatus, where the method includes: receiving, by a first node controller, a first packet; acquiring an information directory, and querying, in the information directory, whether a memory address requested by the first packet is occupied by a second node controller; when the memory address requested by the first packet is occupied by the second node controller, querying node presence information to determine whether the second node controller exists; and when it is determined that the second node controller does not exist, generating and sending an invalid response packet, where a destination node identifier DNID of the invalid response packet is a source node identifier SNID of the first packet, and an SNID of the invalid response packet is a DNID of the first packet.

5. 发明公开

EP3198466A4 MULTICORE MEMORY DATA RECORDER FOR KERNEL MODULE 审中-公开
公开(公告)号：EP3198466A4
公开(公告)日：2018-04-18
申请号：EP14902388
申请日：2014-09-25
申请人： INTEL CORP
发明人： LUO SAI , NGAI TIN FOOK , CHEN HU , ZHOU XIAOCHENG , LIN CHUNXIAO , ZHAO KANG
IPC分类号： G06F15/167 , G06F9/52 , G06F11/36
CPC分类号： G06F12/0842 , G06F9/00 , G06F11/36 , G06F11/3632 , G06F12/0831 , G06F12/0833 , G06F12/0875 , G06F2212/1016 , G06F2212/1032 , G06F2212/452 , G06F2212/621
摘要： A processing device includes a processing core, coupled to a memory, to execute a task including a code segment identified as being monitored and a kernel recorder, coupled to the processing core via a core interface. The kernel recorder includes a first filter circuit to responsive to determining that the task being executed enters the code segment, set the kernel recorder to a first mode under which the kernel recorder is to record, in a first record, a plurality of memory addresses accessed by the code segment, and responsive to determining that the execution of the task exits the code segment, set the kernel recorder to a second mode under which the kernel recorder is to detect a write operation to a memory address recorded in the first record and record the memory address in a second record.

6. 发明公开

EP3117332A4 APPARATUS AND METHOD OF RESOLVING PROTOCOL CONFLICTS IN AN UNORDERED NETWORK 审中-公开
公开(公告)号：EP3117332A4
公开(公告)日：2018-01-10
申请号：EP15761069
申请日：2015-03-12
申请人： HEWLETT PACKARD ENTPR DEVELOPMENT LP
发明人： MALEWICKI MICHAEL E
IPC分类号： G06F15/16 , G06F9/445 , G06F12/0831
CPC分类号： G06F12/0831 , G06F2212/621
摘要： An apparatus and method of accessing data in a memory in a multi-node, high performance computing system has a requesting agent and a home agent. The requesting agent is a member of a first node of the high performance computing system, while the home agent is a member of a second node of the high performance computing system. The home agent forwards data in a specified memory toward the requesting agent across the unordered network, and determines that a snoop request is to be sent to the requesting agent. After determining that the requesting agent has received the requested data in the specified memory of the second node, the home agent forwards the snoop request to the requesting agent across the unordered network.

7. 发明授权

EP2629206B1 Directory replacement method and device 有权转让
标题翻译：目录替换方法和设备
公开(公告)号：EP2629206B1
公开(公告)日：2017-11-22
申请号：EP12193965.6
申请日：2012-11-23
申请人： Huawei Technologies Co., Ltd.
发明人： Yao, Ce , Zhao, Yafei , Xu, Jianrong
IPC分类号： G06F12/0817 , G06F12/12
CPC分类号： G06F12/0891 , G06F12/082 , G06F12/0831 , G06F12/12
摘要： The present invention provides a directory replacement method and device. A home agent (HA) receives a data access request including a first address from a first CA, if a designated storage where a directory is located is entirely occupied by the directory, and a first directory entry corresponding to the first address is not in the directory, the HA selects a second directory entry from the directory, deletes it and adds the first directory entry into the directory; before the HA replaces the directory entry in the directory, no matter what status (for example, Invalid status, Shared status or Any status) a share status of a cache line corresponding to an address in the directory entry to be replaced is, the HA does not need to request a corresponding CA to perform an invalidating operation on data, but directly replaces the directory entry in the directory, thereby improving replacement efficiency.

8. 发明公开

EP3198824A1 REDUCING INTERCONNECT TRAFFICS OF MULTI-PROCESSOR SYSTEM WITH EXTENDED MESI PROTOCOL 审中-公开
标题翻译：用扩展的MESI协议减少多处理器系统的互连业务
公开(公告)号：EP3198824A1
公开(公告)日：2017-08-02
申请号：EP14902420.0
申请日：2014-09-25
申请人： Intel Corporation
发明人： WANG, Kebing , BIAN, Bianny
IPC分类号： H04L29/06
CPC分类号： G06F12/0808 , G06F12/0806 , G06F12/0811 , G06F12/0817 , G06F12/0831 , G06F2212/1016 , G06F2212/283 , G06F2212/621
摘要： A processor includes a first core including a first cache including a cache line, a second core including a second cache, and a cache controller to set a flag stored in a flag section of the cache line of the first cache to one of a processor share (PS) state in response to data stored in the cache line being shared by the second cache, or to a global share (GS) state in response to the data stored in the first cache line being shared by a third cache of a second processor.
摘要翻译：处理器包括第一核和第二核，所述第一核包括包含高速缓存行的第一高速缓存，包括第二高速缓存的第二核以及用于将存储在第一高速缓存的高速缓存行的标志部分中的标志设置为处理器份中的一个的高速缓存控制器响应于存储在第一高速缓存行中的数据被第二处理器的第三高速缓存所共享，响应于存储在高速缓存行中的数据被第二高速缓存共享，或者响应于全局共享（GS）状态，。

9. 发明公开

EP3198466A1 MULTICORE MEMORY DATA RECORDER FOR KERNEL MODULE 审中-公开
标题翻译：多核存储器数据记录器内核模块
公开(公告)号：EP3198466A1
公开(公告)日：2017-08-02
申请号：EP14902388.9
申请日：2014-09-25
申请人： Intel Corporation
发明人： LUO, Sai , NGAI, Tin-Fook , CHEN, Hu , ZHOU, Xiaocheng , LIN, Chunxiao , ZHAO, Kang
IPC分类号： G06F15/167
CPC分类号： G06F12/0842 , G06F11/36 , G06F11/3632 , G06F12/0831 , G06F12/0833 , G06F12/0875 , G06F2212/1016 , G06F2212/1032 , G06F2212/452 , G06F2212/621
摘要： A processing device includes a processing core, coupled to a memory, to execute a task including a code segment identified as being monitored and a kernel recorder, coupled to the processing core via a core interface. The kernel recorder includes a first filter circuit to responsive to determining that the task being executed enters the code segment, set the kernel recorder to a first mode under which the kernel recorder is to record, in a first record, a plurality of memory addresses accessed by the code segment, and responsive to determining that the execution of the task exits the code segment, set the kernel recorder to a second mode under which the kernel recorder is to detect a write operation to a memory address recorded in the first record and record the memory address in a second record.
摘要翻译：处理设备包括耦合到存储器的处理核心，用于执行包括被识别为被监视的代码段的任务和经由核心接口耦合到处理核心的内核记录器。内核记录器包括第一滤波器电路，用于响应于确定正在执行的任务进入代码段，将内核记录器设置为第一模式，在该第一模式下内核记录器将在第一记录中记录访问的多个存储器地址通过所述代码段，并且响应于确定所述任务的执行退出所述代码段，将所述内核记录器设置为第二模式，在所述第二模式下所述内核记录器将检测对记录在所述第一记录中的存储器地址的写入操作，并且记录内存地址在第二条记录中。

10. 发明公开

EP3055769A4 MECHANISM TO PRECLUDE LOAD REPLAYS DEPENDENT ON PAGE WALKS IN OUT-OF-ORDER PROCESSOR 有权
标题翻译： MECHANICALUS ZURPRÄKLUSIONVON LASTWIEDERHOLUNGABHÄNGIGVON PAGEWALKS BEI EINEM无序投影仪
公开(公告)号：EP3055769A4
公开(公告)日：2017-07-19
申请号：EP14891601
申请日：2014-12-14
申请人： VIA ALLIANCE SEMICONDUCTOR CO LTD
发明人： COL GERARD M , EDDY COLIN , HENRY G GLENN
IPC分类号： G06F9/38
CPC分类号： G06F9/3855 , G06F1/3228 , G06F1/3296 , G06F9/30043 , G06F9/30101 , G06F9/38 , G06F9/3824 , G06F9/3836 , G06F9/384 , G06F9/3861 , G06F12/0831 , G06F12/0875 , G06F12/1009
摘要： An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The resources include a system memory that is accessed via a memory bus, the system memory comprising one or more page tables, configured to store one or more mappings between virtual addresses and physical addresses.
摘要翻译：一种包括第一和第二保留站的装置。第一保留站分派加载微指令，并且在保持总线上指示加载微指令是否是指定的加载微指令以从除了核心上高速缓存存储器之外的指定资源中检索操作数。第二保留站耦合到保持总线，并且在派发第一加载微指令之后的多个时钟周期之后，在其中分派一个或多个较新的微指令，这些微指令取决于加载微指令以执行，并且如果它指示为所述加载微指令是指定的加载微指令的所述保持总线，所述第二保留站被配置为停止所述一个或更多个更新的微指令的分派，直到所述加载微指令已取回所述操作数为止。资源包括经由存储器总线访问的系统存储器，系统存储器包括一个或多个页面表，其被配置为存储虚拟地址与物理地址之间的一个或多个映射。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式