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1. 发明授权

EP3022738B1 RESISTANCE-BASED MEMORY CELLS WITH MULTIPLE SOURCE LINES 有权
标题翻译：具有多个源线路电阻存储器单元
公开(公告)号：EP3022738B1
公开(公告)日：2017-02-01
申请号：EP14776976.4
申请日：2014-09-18
申请人： Qualcomm Incorporated
发明人： DONG, Xiangyu
IPC分类号： G11C11/00 , G11C11/16 , G11C11/56 , G11C13/00 , G11C17/02 , G11C17/14 , G11C7/10 , G11C8/16
CPC分类号： G11C11/1673 , G11C7/1075 , G11C8/16 , G11C11/005 , G11C11/16 , G11C11/1659 , G11C11/56 , G11C11/5671 , G11C13/0002 , G11C17/02 , G11C17/14 , G11C2213/74 , G11C2213/79

2. 发明公开

EP3114689A1 VARIABLE READ DELAY SYSTEM 有权
标题翻译：系统ZUR VARIABLENLESEVERZÖGERUNG
公开(公告)号：EP3114689A1
公开(公告)日：2017-01-11
申请号：EP15718001.9
申请日：2015-03-20
申请人： Qualcomm Incorporated
发明人： KIM, Jung Pill , KIM, Taehyun , KIM, Sungryul , DONG, Xiangyu
IPC分类号： G11C7/08 , G11C7/06 , G11C7/10
CPC分类号： G11C29/026 , G06F11/106 , G06F11/1072 , G06F11/1076 , G11C7/06 , G11C7/08 , G11C7/1006 , G11C7/1072 , G11C11/16 , G11C11/1673 , G11C13/004 , G11C14/0081 , G11C14/009 , G11C16/26 , G11C16/30 , G11C29/30 , G11C29/52 , G11C2029/0411
摘要： A device includes a plurality of memory cells of a memory array, a sense amplifier of the memory array, and selection logic of the memory array. The sense amplifier is configured to sense at least one data value from at least one memory cell of the plurality of memory cells. The selection logic is configured to select between causing the sense amplifier to sense the at least one data value using a first sensing delay and causing the sense amplifier to sense the at least one data value using a second sensing delay. The second sensing delay is longer than the first sensing delay.
摘要翻译：一种器件包括存储器阵列的多个存储单元，存储器阵列的读出放大器和存储器阵列的选择逻辑。感测放大器被配置为感测来自多个存储器单元中的至少一个存储单元的至少一个数据值。选择逻辑被配置为在使感测放大器使用第一感测延迟来感测至少一个数据值并使得感测放大器使用第二感测延迟来感测至少一个数据值之间进行选择。第二感测延迟比第一感测延迟更长。

3. 发明公开

EP3108367A1 KERNEL MASKING OF DRAM DEFECTS 审中-公开
标题翻译：内核MASK DRAM缺损
公开(公告)号：EP3108367A1
公开(公告)日：2016-12-28
申请号：EP15708993.9
申请日：2015-02-20
申请人： Qualcomm Incorporated
发明人： CHUN, Dexter T. , LI, Yanru , DONG, Xiangyu , SUH, Jungwon , KIM, Jung Pill , SRIRAMAGIRI, Deepti Vijayalakshmi
IPC分类号： G06F11/10 , G06F12/00
CPC分类号： G11C29/44 , G06F11/1048 , G06F11/1076 , G06F11/2053 , G06F12/0246 , G06F2212/7209 , G11C2029/4402
摘要： Systems, methods, and computer programs are disclosed for kernel masking dynamic random access memory (DRAM) defects. One such method comprises: detecting and correcting a single-bit error associated with a physical address in a dynamic random access memory (DRAM); receiving error data associated with the physical address from the DRAM; storing the received error data in a failed address table located in a non-volatile memory; and retiring a kernel page corresponding to the physical address if a number of errors associated with the physical address exceeds an error count threshold.

4. 发明公开

EP3090343A1 BIT REMAPPING SYSTEM 有权
标题翻译： BIT-重映-SYSTEM
公开(公告)号：EP3090343A1
公开(公告)日：2016-11-09
申请号：EP14819237.0
申请日：2014-12-11
申请人： Qualcomm Incorporated
发明人： DONG, Xiangyu , KIM, Jung Pill , SAIFUDDIN, Mosaddiq
IPC分类号： G06F11/10 , G06F12/00
CPC分类号： G06F11/076 , G06F11/1048 , G06F11/1076 , G06F12/00 , G06F13/16 , G06F13/1668 , G06F2201/88
摘要： A method includes storing, at a counter, a first value indicating a count of read operations in which a bit error is detected in data associated with a first address. The method further includes, in response to the first value exceeding a first threshold value, remapping the first address to a second address using a controller that is coupled to a memory array. The first address corresponds to a first element of the memory array. The second address corresponds to a second element that is included at a memory within the controller. Remapping the first address includes, in response to receiving a first read request for data located at the first address, replacing a first value read from the first element with a second value read from the second element.
摘要翻译：一种方法包括在计数器处存储指示在与第一地址相关联的数据中检测到位错误的读取操作的计数的第一值。该方法还包括响应于第一值超过第一阈值，使用耦合到存储器阵列的控制器将第一地址重新映射到第二地址。第一个地址对应于存储器阵列的第一个元素。第二地址对应于包括在控制器内的存储器上的第二元素。响应于接收到位于第一地址的数据的第一读取请求，重映射第一地址包括用从第二元素读取的第二值替换从第一元素读取的第一值。

5. 发明公开

EP2946302A1 HETEROGENEOUS MEMORY SYSTEMS, AND RELATED METHODS AND COMPUTER-READABLE MEDIA FOR SUPPORTING HETEROGENEOUS MEMORY ACCESS REQUESTS IN PROCESSOR-BASED SYSTEMS 有权
标题翻译：异构存储系统和相关的方法和计算机可读媒体支持异构存储器的要求处理器的系统
公开(公告)号：EP2946302A1
公开(公告)日：2015-11-25
申请号：EP14703970.5
申请日：2014-01-14
申请人： Qualcomm Incorporated
发明人： DONG, Xiangyu , SUH, Jungwon
IPC分类号： G06F13/16
CPC分类号： G11C11/40603 , G06F12/08 , G06F13/1694 , Y02D10/14
摘要： Heterogeneous memory systems, and related methods and computer-readable media for supporting heterogeneous memory access requests in processor-based systems are disclosed. A heterogeneous memory system is comprised of a plurality of homogeneous memories that can be accessed for a given memory access request. Each homogeneous memory has particular power and performance characteristics. In this regard, a memory access request can be advantageously routed to one of the homogeneous memories in the heterogeneous memory system based on the memory access request, and power and/or performance considerations. The heterogeneous memory access request policies may be predefined or determined dynamically based on key operational parameters, such as read/write type, frequency of page hits, and memory traffic, as non-limiting examples. In this manner, memory access request times can be optimized to be reduced without the need to make tradeoffs associated with only having one memory type available for storage.

6. 发明授权

EP3061096B1 SPLIT WRITE OPERATION FOR RESISTIVE MEMORY CACHE 有权
公开(公告)号：EP3061096B1
公开(公告)日：2020-04-22
申请号：EP14783755.3
申请日：2014-10-01
申请人： Qualcomm Incorporated
发明人： DONG, Xiangyu , ZHU, Xiaochun , SUH, Jungwon
IPC分类号： G11C7/10 , G06F12/0855 , G06F12/0864 , G06F12/08 , G11C11/16 , G11C13/00

7. 发明授权

EP3069346B1 VOLATILE MEMORY SENDING REFRESH REQUEST SIGNAL TO MEMORY CONTROLLER 有权
公开(公告)号：EP3069346B1
公开(公告)日：2020-04-15
申请号：EP14799287.9
申请日：2014-10-30
申请人： Qualcomm Incorporated
发明人： SRIRAMAGIRI, Deepti Vijayalakshmi , KIM, Jung Pill , SUH, Jungwon , DONG, Xiangyu
IPC分类号： G11C11/406 , G06F13/16

8. 发明公开

EP3198602A1 READ OPERATION OF CACHE MRAM USING A REFERENCE WORD LINE 失效
标题翻译：使用参考字行阅读高速缓存MRAM的操作
公开(公告)号：EP3198602A1
公开(公告)日：2017-08-02
申请号：EP15767017.5
申请日：2015-09-09
申请人： Qualcomm Incorporated
发明人： KIM, Taehyun , KIM, Sungryul , KIM, Jung Pill , DONG, Xiangyu
IPC分类号： G11C11/16 , G06F12/08
CPC分类号： G11C11/1673 , G11C11/161 , G11C11/1693
摘要： Systems and methods relate to a read operation on a magnetoresistive random access memory (MRAM) coupled with a tag array, the method comprising: receiving an index and a tag; based on the index, accessing n memory locations in the tag array and for each of the accessed n memory locations comparing data stored therein with the received tag; based on the index, activating a dummy word line in the MRAM; after the activation of the dummy word line, generating a hit signal associated with one of the n memory locations if the comparing indicates a match for said one of the n memory locations; in response to the activation of the dummy word line obtaining a settled reference voltage for reading MRAM bit cells of the MRAM designated by the index; among the MRAM cells designated by the index, reading the MRAM cells having a memory location corresponding to the one of the n-memory location in the tag array providing said hit signal, the reading using the settled reference voltage.
摘要翻译：系统和方法涉及磁阻随机存取存储器（MRAM）上的读取操作。在确定MRAM中是否存在与读取操作相对应的第一地址的命中之前，基于第一地址的至少一部分比特来激活伪字线。基于连接到伪字线的伪单元，开始用于读取第一地址处的MRAM位单元的参考电压的建立过程，并且获得稳定的参考电压。如果有命中，则基于从第一地址确定的行地址激活第一字线，并且使用稳定的参考电压读取第一地址处的MRAM位单元。

9. 发明授权

EP3055864B1 REFRESH SCHEME FOR MEMORY CELLS WITH NEXT BIT TABLE 有权
标题翻译： AKTUALISIERUNGSSCHEMAFÜRSPEICHERZELLEN MIT EINER NEXT-BIT-TABELLE
公开(公告)号：EP3055864B1
公开(公告)日：2017-04-05
申请号：EP14812078.5
申请日：2014-11-20
申请人： Qualcomm Incorporated
发明人： DONG, Xiangyu , KIM, Jung Pill , SUH, Jungwon
IPC分类号： G11C11/406 , G06F12/02
CPC分类号： G11C11/406 , G06F12/0207 , G11C11/40615 , G11C11/40618 , G11C11/40622 , G11C2211/4061 , G11C2211/4065

10. 发明公开

EP2965209A1 CRITICAL-WORD-FIRST ORDERING OF CACHE MEMORY FILLS TO ACCELERATE CACHE MEMORY ACCESSES, AND RELATED PROCESSOR-BASED SYSTEMS AND METHODS 审中-公开
标题翻译：第一次请求缓存灌装采用代码字缓存的加速存取和相关的处理器为基础的系统和方法
公开(公告)号：EP2965209A1
公开(公告)日：2016-01-13
申请号：EP14714840.7
申请日：2014-03-04
申请人： QUALCOMM Incorporated
发明人： DONG, Xiangyu
IPC分类号： G06F12/08
CPC分类号： G06F12/128 , G06F12/0868 , G06F12/0893
摘要： Critical-word-first reordering of cache fills to accelerate cache memory accesses, and related processor-based systems and methods are disclosed. In this regard in one embodiment, a cache memory is provided. The cache memory comprises a data array comprising a cache line, which comprises a plurality of data entry blocks configured to store a plurality of data entries. The cache memory also comprises cache line ordering logic configured to critical-word-first order the plurality of data entries into the cache line during a cache fill, and to store a cache line ordering index that is associated with the cache line and that indicates the critical-word-first ordering of the plurality of data entries in the cache line. The cache memory also comprises cache access logic configured to access each of the plurality of data entries in the cache line based on the cache line ordering index for the cache line.

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