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1. 发明授权

EP3061096B1 SPLIT WRITE OPERATION FOR RESISTIVE MEMORY CACHE 有权
公开(公告)号：EP3061096B1
公开(公告)日：2020-04-22
申请号：EP14783755.3
申请日：2014-10-01
申请人： Qualcomm Incorporated
发明人： DONG, Xiangyu , ZHU, Xiaochun , SUH, Jungwon
IPC分类号： G11C7/10 , G06F12/0855 , G06F12/0864 , G06F12/08 , G11C11/16 , G11C13/00

2. 发明授权

EP3069346B1 VOLATILE MEMORY SENDING REFRESH REQUEST SIGNAL TO MEMORY CONTROLLER 有权
公开(公告)号：EP3069346B1
公开(公告)日：2020-04-15
申请号：EP14799287.9
申请日：2014-10-30
申请人： Qualcomm Incorporated
发明人： SRIRAMAGIRI, Deepti Vijayalakshmi , KIM, Jung Pill , SUH, Jungwon , DONG, Xiangyu
IPC分类号： G11C11/406 , G06F13/16

3. 发明公开

EP3198602A1 READ OPERATION OF CACHE MRAM USING A REFERENCE WORD LINE 有权
标题翻译：使用参考字行阅读高速缓存MRAM的操作
公开(公告)号：EP3198602A1
公开(公告)日：2017-08-02
申请号：EP15767017.5
申请日：2015-09-09
申请人： Qualcomm Incorporated
发明人： KIM, Taehyun , KIM, Sungryul , KIM, Jung Pill , DONG, Xiangyu
IPC分类号： G11C11/16 , G06F12/08
CPC分类号： G11C11/1673 , G11C11/161 , G11C11/1693
摘要： Systems and methods relate to a read operation on a magnetoresistive random access memory (MRAM) coupled with a tag array, the method comprising: receiving an index and a tag; based on the index, accessing n memory locations in the tag array and for each of the accessed n memory locations comparing data stored therein with the received tag; based on the index, activating a dummy word line in the MRAM; after the activation of the dummy word line, generating a hit signal associated with one of the n memory locations if the comparing indicates a match for said one of the n memory locations; in response to the activation of the dummy word line obtaining a settled reference voltage for reading MRAM bit cells of the MRAM designated by the index; among the MRAM cells designated by the index, reading the MRAM cells having a memory location corresponding to the one of the n-memory location in the tag array providing said hit signal, the reading using the settled reference voltage.
摘要翻译：系统和方法涉及磁阻随机存取存储器（MRAM）上的读取操作。在确定MRAM中是否存在与读取操作相对应的第一地址的命中之前，基于第一地址的至少一部分比特来激活伪字线。基于连接到伪字线的伪单元，开始用于读取第一地址处的MRAM位单元的参考电压的建立过程，并且获得稳定的参考电压。如果有命中，则基于从第一地址确定的行地址激活第一字线，并且使用稳定的参考电压读取第一地址处的MRAM位单元。

4. 发明授权

EP3055864B1 REFRESH SCHEME FOR MEMORY CELLS WITH NEXT BIT TABLE 有权
标题翻译： AKTUALISIERUNGSSCHEMAFÜRSPEICHERZELLEN MIT EINER NEXT-BIT-TABELLE
公开(公告)号：EP3055864B1
公开(公告)日：2017-04-05
申请号：EP14812078.5
申请日：2014-11-20
申请人： Qualcomm Incorporated
发明人： DONG, Xiangyu , KIM, Jung Pill , SUH, Jungwon
IPC分类号： G11C11/406 , G06F12/02
CPC分类号： G11C11/406 , G06F12/0207 , G11C11/40615 , G11C11/40618 , G11C11/40622 , G11C2211/4061 , G11C2211/4065

5. 发明公开

EP2965209A1 CRITICAL-WORD-FIRST ORDERING OF CACHE MEMORY FILLS TO ACCELERATE CACHE MEMORY ACCESSES, AND RELATED PROCESSOR-BASED SYSTEMS AND METHODS 审中-公开
标题翻译：第一次请求缓存灌装采用代码字缓存的加速存取和相关的处理器为基础的系统和方法
公开(公告)号：EP2965209A1
公开(公告)日：2016-01-13
申请号：EP14714840.7
申请日：2014-03-04
申请人： QUALCOMM Incorporated
发明人： DONG, Xiangyu
IPC分类号： G06F12/08
CPC分类号： G06F12/128 , G06F12/0868 , G06F12/0893
摘要： Critical-word-first reordering of cache fills to accelerate cache memory accesses, and related processor-based systems and methods are disclosed. In this regard in one embodiment, a cache memory is provided. The cache memory comprises a data array comprising a cache line, which comprises a plurality of data entry blocks configured to store a plurality of data entries. The cache memory also comprises cache line ordering logic configured to critical-word-first order the plurality of data entries into the cache line during a cache fill, and to store a cache line ordering index that is associated with the cache line and that indicates the critical-word-first ordering of the plurality of data entries in the cache line. The cache memory also comprises cache access logic configured to access each of the plurality of data entries in the cache line based on the cache line ordering index for the cache line.

6. 发明公开

EP2936493A1 INTEGRATED MRAM CACHE MODULE 有权
标题翻译：集成MRAM-CACHE-MODUL
公开(公告)号：EP2936493A1
公开(公告)日：2015-10-28
申请号：EP13822034.8
申请日：2013-12-20
申请人： Qualcomm Incorporated
发明人： DONG, Xiangyu , KIM, Jung Pill , SUH, Jungwon
IPC分类号： G11C11/16 , G06F12/08 , G11C15/00
CPC分类号： G11C11/16 , G11C11/1653 , G11C2211/5643 , Y10T29/49117
摘要： Systems and methods for integrated magnetoresistive random access memory (MRAM) modules. An integrated circuit includes a processor without a last level cache integrated on a first chip a MRAM module comprising a MRAM last level cache and a MRAM main memory integrated on a second chip, wherein the MRAM module is a unified structure fabricated as monolithic package or a plurality of packages. The second package further includes memory controller logic. A simplified interface structure is configured to couple the first and the second package. The MRAM module is designed for high speed, high data retention, aggressive prefetching between the MRAM last level cache and the MRAM main memory, improved page handling, and improved scalability.
摘要翻译：用于集成磁阻随机存取存储器（MRAM）模块的系统和方法。集成电路包括处理器，其没有集成在第一芯片上的最后一级高速缓存，MRAM模块包括MRAM最后一级高速缓存和集成在第二芯片上的MRAM主存储器，其中MRAM模块是制造为单片封装或多个包装。第二包还包括存储器控制器逻辑。简化的接口结构被配置为耦合第一和第二封装。 MRAM模块设计用于高速，高数据保留，MRAM最后一级缓存和MRAM主存储器之间的积极预取，改进的页面处理和改进的封印能力。

7. 发明授权

EP2973576B1 SYSTEM AND METHOD TO DYNAMICALLY DETERMINE A TIMING PARAMETER OF A MEMORY DEVICE 有权
标题翻译：用于动态确定存储器设备的时序参数的系统和方法
公开(公告)号：EP2973576B1
公开(公告)日：2017-11-08
申请号：EP14719146.4
申请日：2014-03-12
申请人： Qualcomm Incorporated
发明人： DONG, Xiangyu , SUH, Jungwon
IPC分类号： G11C11/4076 , G06F17/50 , H01L27/108 , G11C7/22 , G11C29/50 , G11C29/02 , G11C29/04
CPC分类号： G11C7/22 , G06F3/061 , G06F3/0611 , G06F3/0629 , G06F12/00 , G06F17/5031 , G11C11/4076 , G11C29/023 , G11C29/50012 , G11C2029/0409 , G11C2207/2254

8. 发明授权

EP2959391B1 METHODS AND APPARATUS FOR INTRA-SET WEAR-LEVELING FOR MEMORIES WITH LIMITED WRITE ENDURANCE 有权
标题翻译：方法和设备集合内的磨损补偿FOR内存限制的写作耐力
公开(公告)号：EP2959391B1
公开(公告)日：2017-05-17
申请号：EP14710096.0
申请日：2014-02-18
申请人： Qualcomm Incorporated
发明人： DONG, Xiangyu
IPC分类号： G06F12/08
CPC分类号： G06F12/0891 , G06F12/0895 , G06F12/121 , G06F2212/1032 , G06F2212/7211

9. 发明公开

EP3069346A2 VOLATILE MEMORY SENDING REFRESH REQUEST SIGNAL TO MEMORY CONTROLLER 有权
标题翻译： FLÜCHTIGENSPEICHER MIT SENDEN VON AKTUALISIERUNGSANFORDERUNGSSIGNALEN ZU EINER SPEICHERSTEUERUNG
公开(公告)号：EP3069346A2
公开(公告)日：2016-09-21
申请号：EP14799287.9
申请日：2014-10-30
申请人： Qualcomm Incorporated
发明人： SRIRAMAGIRI, Deepti Vijayalakshmi , KIM, Jung Pill , SUH, Jungwon , DONG, Xiangyu
IPC分类号： G11C11/406 , G06F13/16
摘要： A method includes sending a first signal from a memory device to a memory controller. The first signal indicates to the memory controller that particular memory cells of the memory device are to be refreshed by the memory device.
摘要翻译：一种方法包括将第一信号从存储器装置发送到存储器控制器。第一信号向存储器控制器指示存储器件的特定存储器单元将被存储器件刷新。

10. 发明公开

EP3022738A1 RESISTANCE-BASED MEMORY CELLS WITH MULTIPLE SOURCE LINES 有权
标题翻译： WIDERSTANDSSPEICHERZELLEN MIT MEHREREN QUELLLEITUNGEN
公开(公告)号：EP3022738A1
公开(公告)日：2016-05-25
申请号：EP14776976.4
申请日：2014-09-18
申请人： Qualcomm Incorporated
发明人： DONG, Xiangyu
IPC分类号： G11C11/00 , G11C11/16 , G11C11/56 , G11C13/00 , G11C17/02 , G11C17/14 , G11C7/10 , G11C8/16
CPC分类号： G11C11/1673 , G11C7/1075 , G11C8/16 , G11C11/005 , G11C11/16 , G11C11/1659 , G11C11/56 , G11C11/5671 , G11C13/0002 , G11C17/02 , G11C17/14 , G11C2213/74 , G11C2213/79
摘要： In a particular embodiment, a device includes a resistance-based memory cell having multiple source lines and multiple access transistors. A coupling configuration of the multiple access transistors to multiple source lines encodes a data value.
摘要翻译：在特定实施例中，器件包括具有多个源极线和多个存取晶体管的基于电阻的存储单元。多路存取晶体管与多条源极线的耦合配置对数据值进行编码。

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