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1. 发明公开

EP3382561A1 RECOVERY MECHANISM FOR LOW LATENCY METADATA LOG 审中-公开
公开(公告)号：EP3382561A1
公开(公告)日：2018-10-03
申请号：EP18164922.9
申请日：2018-03-29
申请人： Pavilion Data Systems, Inc.
发明人： DANTKALE, Suhas , SATISH, Venkeepuram , GOVINDASAMY, Raghuraman
IPC分类号： G06F12/0868 , G06F12/02
CPC分类号： G06F11/1435 , G06F11/1451 , G06F12/0246 , G06F12/0811 , G06F12/0868 , G06F12/1063 , G06F12/128 , G06F2201/84 , G06F2212/1024 , G06F2212/1032 , G06F2212/283 , G06F2212/285 , G06F2212/312 , G06F2212/621 , G06F2212/681 , G06F2212/69 , G06F2212/7203
摘要： A storage server includes an IO controller, a management controller and physical drives. The IO controller generates multiple metadata updates and writes a cache entry that includes the multiple metadata updates to a first cache in memory of the management controller. The IO controller additionally writes a copy of the cache entry to a second cache in a memory of the IO controller and increments a commit pointer in the first and second caches to indicate that the metadata updates are committed.

2. 发明授权

EP3224728B1 PROVIDING SHARED CACHE MEMORY ALLOCATION CONTROL IN SHARED CACHE MEMORY SYSTEMS 有权
公开(公告)号：EP3224728B1
公开(公告)日：2018-08-15
申请号：EP15797546.7
申请日：2015-11-09
申请人： Qualcomm Incorporated
发明人： HOWER, Derek Robert , CAIN, III, Harold Wade
IPC分类号： G06F12/084 , G06F12/08 , G06F12/12 , G06F11/34 , G06F12/0846 , G06F12/0842 , G06F12/0831 , G06F12/128
CPC分类号： G06F12/084 , G06F11/34 , G06F12/0833 , G06F12/0842 , G06F12/0846 , G06F12/12 , G06F12/128 , G06F2212/1016 , G06F2212/1044 , G06F2212/314 , G06F2212/6042 , G06F2212/62
摘要： Providing shared cache memory allocation control in shared cached memory systems is disclosed. In one aspect, a cache controller of a shared cache memory system comprising a plurality of cache lines is provided. The cache controller comprises a cache allocation circuit providing a minimum mapping bitmask for mapping a Quality of Service (QoS) class to a minimum partition of the cache lines, and a maximum mapping bitmask for mapping the QoS class to a maximum partition of the cache lines. The cache allocation circuit receives a memory access request comprising a QoS identifier (QoSID) of the QoS class, and is configured to determine whether the memory access request corresponds to a cache line of the plurality of cache lines. If not, the cache allocation circuit selects, as a target partition, the minimum partition mapped to the QoS class or the maximum partition mapped to the QoS class.

3. 发明公开

EP3336681A1 METHOD AND APPARATUS FOR READING DISK ARRAY 审中-公开
公开(公告)号：EP3336681A1
公开(公告)日：2018-06-20
申请号：EP16850338.1
申请日：2016-09-27
申请人： Huawei Technologies Co., Ltd.
发明人： ZHANG, Jian , ZHANG, Xiang , WU, Liming
IPC分类号： G06F3/06
CPC分类号： G06F12/0871 , G06F3/06 , G06F3/061 , G06F3/0652 , G06F3/0656 , G06F3/0659 , G06F3/0689 , G06F12/0808 , G06F12/0811 , G06F12/0866 , G06F12/0868 , G06F12/0897 , G06F12/128 , G06F2212/1024 , G06F2212/1041 , G06F2212/262 , G06F2212/312
摘要： The present invention relates to the field of storage technologies, and discloses a method and an apparatus for reading a redundant array of independent disks. The method includes: receiving a first read request, where the first read request includes an identifier of a to-be-read logical block (S101); sending a first command to a controller of a first hard disk when a first cache does not include data stored in the to-be-read logical block, where the first hard disk is a hard disk including the to-be-read logical block, and the first command is used to instruct the controller of the first hard disk to return the data stored in the to-be-read logical block (S102); outputting the data returned by the controller of the first hard disk, and storing the returned data in the first cache (S103); and deleting the returned data stored in the first cache, or controlling the controller of the first hard disk to delete the returned data stored in a second cache (S104), where the second cache is a cache of the controller, and the returned data stored in the second cache is stored after the controller of the first hard disk reads, according to the first command, the data from the to-be-read logical block, or is stored before the controller of the first hard disk receives the first command.

4. 发明公开

EP3306479A1 MEMORY STRUCTURE COMPRISING SCRATCHPAD MEMORY 审中-公开
标题翻译：包含SCRATCHPAD存储器的存储器结构
公开(公告)号：EP3306479A1
公开(公告)日：2018-04-11
申请号：EP16192581.3
申请日：2016-10-06
申请人： Stichting IMEC Nederland , IMEC VZW
发明人： CATTHOOR, Francky , SETOAIN RODRIGO, Javier , GOMEZ, Jose Ignacio , PAPASTERGIOU, Thomas , TENLLADO, Christian , XYDIS, Sotiris , BALOUKAS, Christos , DAS, Anup Kumar , HARTMANN, Matthias , SOUDRIS, Dimitrios
IPC分类号： G06F12/0897 , G06F12/1009 , G06F12/08 , G06F12/0864 , G06F12/02 , G06F9/50
CPC分类号： G06F12/1054 , G06F12/023 , G06F12/08 , G06F12/0811 , G06F12/0864 , G06F12/0897 , G06F12/1009 , G06F12/122 , G06F12/128 , G06F2212/1016 , G06F2212/2515 , G06F2212/283 , G06F2212/502 , G06F2212/621 , G06F2212/652 , Y02D10/13
摘要： The present invention relates to a memory hierarchy for a system-in-package. The memory hierarchy is directly connectable to a processor (10) via a memory management unit arranged for translating a virtual address sent by said processor into a physical address. The memory hierarchy has a data cache memory and a memory structure having at least a L1 memory array comprising at least one cluster (21) having one or more banks of scratchpad memory. The memory structure comprises a first data access controller (31) arranged for managing one or more of said banks of scratchpad memory of at least one of said clusters of at least said L1 memory array, comprising a data port for receiving at least one physical address and arranged for checking, for each received physical address, if said physical address is present in said one or more banks of said at least one cluster of at least said L1 memory array and, if so, as a part of said managing, for forwarding a data request to one or more banks of scratchpad memory where said physical address is required, and if not, for forwarding said physical address to a cache controller (40) steering said data cache memory.
摘要翻译：本发明涉及用于系统级封装的存储器层次结构。存储器层级经由存储器管理单元可直接连接到处理器（10），所述存储器管理单元被布置用于将由所述处理器发送的虚拟地址转换为物理地址。存储器层次结构具有数据高速缓冲存储器和具有至少一个L1存储器阵列的存储器结构，所述L1存储器阵列包括具有一个或多个暂存器存储器组的至少一个簇（21）。所述存储器结构包括第一数据存取控制器（31），所述第一数据存取控制器（31）被安排用于管理至少所述L1存储器阵列的所述群集中的至少一个的所述暂存器存储器的所述存储体中的一者或一者以上，所述数据端口包括用于接收并且被安排用于针对每个接收到的物理地址检查所述物理地址是否存在于所述至少一个L1存储器阵列的所述至少一个簇的所述一个或多个存储体中，并且如果存在，作为所述管理的一部分，向需要所述物理地址的暂存器存储器的一个或多个存储体提供数据请求，如果不是，则向所述物理地址转发给高速缓存控制器（40）以转向所述数据高速缓存存储器。

5. 发明公开

EP3255547A1 DATA BACKUP DEVICE AND METHOD 有权
标题翻译：数据备份装置和方法
公开(公告)号：EP3255547A1
公开(公告)日：2017-12-13
申请号：EP16761044.3
申请日：2016-03-02
申请人： Huawei Technologies Co., Ltd.
发明人： LI, Hehe , LIU, Yongpan , ZHAO, Qinghang , LUO, Rong , YANG, Huazhong
IPC分类号： G06F11/14
CPC分类号： G06F3/065 , G06F3/061 , G06F3/0619 , G06F3/0665 , G06F3/0688 , G06F11/1441 , G06F11/2015 , G06F11/3037 , G06F12/08 , G06F12/128 , G06F2201/88 , G06F2201/885 , G06F2212/621
摘要： The present invention provides a data backup apparatus and method. According to the data backup method, when a data backup apparatus is powered on, a quantity of dead blocks and a quantity of live blocks are counted, where the dead blocks and the live blocks correspond to a sequence access identifier that is at a time point when the data backup apparatus is powered on. After the data backup apparatus is powered off, a proportion occupied by dead blocks corresponding to each sequence access identifier at the power-on time point in a total quantity of sampled cache blocks corresponding to the sequence access identifier, is calculated according to the counted quantities of dead blocks and live blocks that correspond to the sequence access identifier at the time point when the data backup apparatus is powered on. The calculated proportion is compared with a preset threshold, and a dead block in a volatile memory unit is predicted according to a comparison result. During backup, a cache block that is predicted to be a dead block is not backed up. This reduces a backup data volume and improves backup efficiency.
摘要翻译：本发明提供了一种数据备份装置和方法。根据该数据备份方法，当数据备份装置上电时，统计死区块数量和活块数量，其中死区块和活体块对应于时间点的序列访问标识符当数据备份设备开机时。数据备份装置下电后，根据计数得到的数量，计算上电时间点对应序列访问标识对应的采样缓存块总数量中每个序列访问标识对应的死区占用的比例在数据备份装置开机的时间点，对应于序列访问标识符的死区块和活区块。将计算出的比例与预设阈值进行比较，根据比较结果预测易失性存储单元中的死区。在备份期间，不会备份预测为死区的高速缓存块。这减少了备份数据量并提高了备份效率。

6. 发明公开

EP3129886A1 DYNAMIC CACHE REPLACEMENT WAY SELECTION BASED ON ADDRESS TAG BITS 审中-公开
标题翻译：基于地址标记位的动态缓存替换方法
公开(公告)号：EP3129886A1
公开(公告)日：2017-02-15
申请号：EP14891603.4
申请日：2014-12-14
申请人： VIA Alliance Semiconductor Co., Ltd.
发明人： REED, Douglas, R.
IPC分类号： G06F12/00
CPC分类号： G06F12/0864 , G06F12/0893 , G06F12/126 , G06F12/128 , G06F2212/604 , Y02D10/13
摘要： A cache memory comprising: a mode input indicates in which of a plurality of allocation modes the cache memory is to operate; a set-associative array of entries having a plurality of sets by W ways; an input receives a memory address comprising: an index used to select a set from the plurality of sets; and a tag used to compare with tags stored in the entries of the W ways of the selected set to determine whether the memory address hits or misses; and allocation logic, when the memory address misses in the array: selects one or more bits of the tag based on the allocation mode; performs a function, based on the allocation mode, on the selected bits of the tag to generate a subset of the W ways of the array; and allocates into one way of the subset of the ways of the selected set.
摘要翻译：一种高速缓冲存储器，包括：模式输入指示高速缓冲存储器将在多种分配模式中的哪一种操作; 通过W路具有多个集合的条目的集合关联阵列; 输入接收存储器地址，所述存储器地址包括：用于从所述多个集合中选择集合的索引; 以及用于与存储在选定集的W路的条目中的标签进行比较以确定存储器地址命中还是未命中的标签; 和分配逻辑，当存储器地址在阵列中未命中时：基于分配模式选择标签的一个或多个比特; 基于分配模式在标签的所选位上执行功能以生成阵列的W路的子集; 并将其分配为所选集合的方式子集的一种方式。

7. 发明公开

EP3055774A1 MULTI-MODE SET ASSOCIATIVE CACHE MEMORY DYNAMICALLY CONFIGURABLE TO SELECTIVELY ALLOCATE INTO ALL OR SUBSET OR TIS WAYS DEPENDING ON MODE 审中-公开
标题翻译： BY多式联运组动态可配置的关联高速缓存模式相关的选择性分配他的所有路径或其中一部分
公开(公告)号：EP3055774A1
公开(公告)日：2016-08-17
申请号：EP14891602.6
申请日：2014-12-14
申请人： VIA Alliance Semiconductor Co., Ltd.
发明人： REED, Douglas, R.
IPC分类号： G06F12/08
CPC分类号： G06F12/023 , G06F12/0804 , G06F12/0846 , G06F12/0864 , G06F12/123 , G06F12/128 , G06F2212/1021 , G06F2212/282 , G06F2212/601 , G06F2212/6046 , Y02D10/13
摘要： A cache stores 2̂J-byte cache lines has an array of 2̂N sets each holds tags each X bits and 2̂W ways. An input receives a Q-bit address, MA[(Q−1):0], having a tag MA[(Q−1):(Q−X)] and index MA[(Q−X−1):J]. Q is at least (N+J+X−1). Set selection logic selects one set using the index and tag LSB; comparison logic compares all but the LSB of the tag with all but the LSB of each tag in the selected set and indicates a hit if a match; allocation logic, when the comparison logic indicates there is not a match: allocates into any of the 2̂W ways of the selected set when operating in a first mode; and into a subset of the 2̂W ways of the selected set when operating in a second mode. The subset of is limited based on bits of the tag portion.

8. 发明公开

EP2805241A4 POPULATING A FIRST STRIDE OF TRACKS FROM A FIRST CACHE TO WRITE TO A SECOND STRIDE IN A SECOND CACHE 有权
标题翻译：共享与服务平台的轨道的第一步从第一缓存写在第二步的第二高速缓存
公开(公告)号：EP2805241A4
公开(公告)日：2015-07-08
申请号：EP12865676
申请日：2012-12-10
申请人： IBM
发明人： GUPTA LOKESH MOHAN , KALOS MATTHEW JOSEPH , BENHASE MICHAEL THOMAS , NIELSEN KARL ALLEN , ASH KEVIN JOHN
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0868 , G06F12/0804 , G06F12/0897 , G06F12/128 , G06F2212/262 , G06F2212/312 , G06F2212/462
摘要： Provided are a computer program product, system, and method for managing data in a cache system comprising a first cache, a second cache, and a storage system. A determination is made of tracks stored in the storage system to demote from the first cache. A first stride is formed including the determined tracks to demote. A determination is made of a second stride in the second cache in which to include the tracks in the first stride. The tracks from the first stride are added to the second stride in the second cache. A determination is made of tracks in strides in the second cache to demote from the second cache. The determined tracks to demote from the second cache are demoted.
摘要翻译：本发明提供一种计算机程序产品，系统，以及用于在高速缓存系统，包括：第一高速缓存，第二高速缓存和存储系统中管理数据的方法。进行确定存储在所述存储系统从所述第一高速缓存降级轨道。第一步幅形成在包括确定性开采轨道降级。进行确定在其中所述第二高速缓存的第二步幅以包括在所述第一跨距的曲目。从第一步幅轨道被添加到在所述第二高速缓存中的第二步幅。的确定在步幅由轨道的所述第二高速缓存从第二高速缓存降级。确定性开采轨道从第二高速缓存降级被降级。

9. 发明公开

EP2660734A1 Deleting records in a multi-level storage architecture without record locks 审中-公开
标题翻译： LöschenvonDatensätzen在einer mehrstufigen Speicherarchitektur ohne Aufzeichnungssperren
公开(公告)号：EP2660734A1
公开(公告)日：2013-11-06
申请号：EP13002237.9
申请日：2013-04-26
申请人： SAP AG
发明人： Faerber, Franz , Lee, Juchang , Schreter, Ivan , Richtarsky, Martin
IPC分类号： G06F17/30
CPC分类号： G06F12/128 , G06F17/30315 , G06F17/30345
摘要： The multi-level storage system and method of deleting first level storage structure pages or records without record locks. The method includes determining whether a record to be deleted from the first level storage structure has any uncommitted write operation, and if the record has an uncommitted write operation, the record is kept in the first level storage structure. Record-moved version information is added to the record to designate the record being moved from the first level storage structure to the second level storage structure. Data change operations are executed for the record based on the record-moved version information without waiting until the record's movement from the first level storage structure to the second level storage structure finishes.
摘要翻译：多级存储系统和删除第一级存储结构页面或记录的方法，无记录锁。该方法包括确定要从第一级存储结构中删除的记录是否具有任何未提交的写入操作，并且如果记录具有未提交的写入操作，则该记录保存在第一级存储结构中。记录移动的版本信息被添加到记录中以指定从第一级存储结构移动到第二级存储结构的记录。基于记录移动版本信息对记录执行数据更改操作，而不等待直到记录从第一级存储结构向第二级存储结构的移动结束。

10. 发明公开

EP2527987A1 Apparatus and methods to reduce castouts in a multi-level cache hierarchy 审中-公开
标题翻译：设备和方法减少多级高速缓存层次结构的崩溃
公开(公告)号：EP2527987A1
公开(公告)日：2012-11-28
申请号：EP12177727.0
申请日：2008-01-30
申请人： QUALCOMM Incorporated
发明人： Speier, Thomas Philip , Dieffenderfer, James Norris , Sartorius, Thomas Andrew
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0897 , G06F12/0804 , G06F12/128 , G06F2212/1028 , Y02D10/13
摘要： Techniques and methods are used to reduce allocations to a higher level cache of cache lines displaced from a lower level cache. When it is determined that displaced lines have already been allocated in a higher level, the allocations of the displaced cache lines are prevented in the next level cache, thus, reducing castouts. To such ends, a line is selected to be displaced in a lower level cache. Information associated with the selected line is identified which indicates that the selected line is present in a higher level cache. An allocation of the selected line in the higher level cache is prevented based on the identified information. Preventing an allocation of the selected line saves power that would be associated with the allocation.
摘要翻译：技术和方法被用来减少分配到的从较低级高速缓存移位缓存行更高层次高速缓存中。当确定开采并流离失所线已经在一个较高的水平分配，流离失所的高速缓存行的分配是防止下一级高速缓存，从而减少投出局。要搜索的目的，选择了线一个较低级高速缓存到移动。与所选行相关的信息标识指示做选择的一行出现在更高级别的缓存。在高级高速缓存所选择的行的分配，防止基于所识别的信息。防止在所选线路的分配节省功耗确实将与分配相关联。

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