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1. 发明公开

EP4307130A3 FLEXIBLE CACHE ALLOCATION TECHNOLOGY PRIORITY-BASED CACHE LINE EVICTION ALGORITHM 审中-实审
公开(公告)号：EP4307130A3
公开(公告)日：2024-05-01
申请号：EP23211531.1
申请日：2020-09-24
申请人： INTEL Corporation
发明人： GHOLKAR, Neha , KUMAR, Akhilesh
IPC分类号： G06F12/126 , G06F12/0897 , G06F12/123 , G06F12/128
CPC分类号： G06F12/126 , G06F12/0897 , G06F12/123 , G06F12/128
摘要： Disclosed embodiments relate to a cache line eviction algorithm. In one example, a processor comprises a plurality of cores; a set associative cache to be shared by the plurality of cores; and a cache control circuit coupled with the set associative cache. The cache control circuit is to receive a cache fill request for an incoming cache line corresponding to an application, select a victim cache line in the set associative cache based on a maximum occupancy bound specified for the application and a current occupancy in the set associative cache for the application, wherein the maximum occupancy bound corresponds to a maximum number of ways per set to be used by the application, and wherein the current occupancy is a number of ways currently used by the application in a set indexed by the incoming cache line, and store the incoming cache line to a location of the selected victim cache line.

2. 发明公开

EP3314403A1 INSTRUCTION BLOCK ALLOCATION ACCORDING TO PERFORMANCE METRIC 有权转让
标题翻译：根据性能指标进行指令块分配
公开(公告)号：EP3314403A1
公开(公告)日：2018-05-02
申请号：EP16739295.0
申请日：2016-06-23
申请人： Microsoft Technology Licensing, LLC
发明人： GRAY, Jan S. , BURGER, Douglas C. , SMITH, Aaron L.
IPC分类号： G06F9/38 , G06F11/30
CPC分类号： G06F12/0833 , G06F9/30043 , G06F9/30047 , G06F9/3804 , G06F9/3806 , G06F9/381 , G06F9/382 , G06F9/3826 , G06F9/3828 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3846 , G06F9/3851 , G06F9/3853 , G06F9/3869 , G06F9/3891 , G06F11/30 , G06F12/128 , G06F2212/621
摘要： Apparatus and methods are disclosed for throttling processor operation in block-based processor architectures. In one example of the disclosed technology, a block-based instruction set architecture processor includes a plurality of processing cores configured to fetch and execute a sequence of instruction blocks. Each of the processing cores includes function resources for performing operations specified by the instruction blocks. The processor further includes a core scheduler configured to allocate functional resources for performing the operations. The functional resources are allocated for executing the instruction blocks based, at least in part, on a performance metric. The performance metric can be generated dynamically or statically based on branch prediction accuracy, energy usage tolerance, and other suitable metrics.

3. 发明公开

EP3255547A4 DATA BACKUP DEVICE AND METHOD 有权
公开(公告)号：EP3255547A4
公开(公告)日：2018-03-28
申请号：EP16761044
申请日：2016-03-02
申请人： HUAWEI TECH CO LTD
发明人： LI HEHE , LIU YONGPAN , ZHAO QINGHANG , LUO RONG , YANG HUAZHONG
IPC分类号： G06F11/14 , G06F11/20 , G06F11/30 , G06F12/08
CPC分类号： G06F3/065 , G06F3/061 , G06F3/0619 , G06F3/0665 , G06F3/0688 , G06F11/1441 , G06F11/2015 , G06F11/3037 , G06F12/08 , G06F12/128 , G06F2201/88 , G06F2201/885 , G06F2212/621
摘要： The present invention provides a data backup apparatus and method. According to the data backup method, when a data backup apparatus is powered on, a quantity of dead blocks and a quantity of live blocks are counted, where the dead blocks and the live blocks correspond to a sequence access identifier that is at a time point when the data backup apparatus is powered on. After the data backup apparatus is powered off, a proportion occupied by dead blocks corresponding to each sequence access identifier at the power-on time point in a total quantity of sampled cache blocks corresponding to the sequence access identifier, is calculated according to the counted quantities of dead blocks and live blocks that correspond to the sequence access identifier at the time point when the data backup apparatus is powered on. The calculated proportion is compared with a preset threshold, and a dead block in a volatile memory unit is predicted according to a comparison result. During backup, a cache block that is predicted to be a dead block is not backed up. This reduces a backup data volume and improves backup efficiency.

4. 发明公开

EP3224728A1 PROVIDING SHARED CACHE MEMORY ALLOCATION CONTROL IN SHARED CACHE MEMORY SYSTEMS 有权
标题翻译：在共享高速缓存存储器系统中提供共享高速缓存存储器分配控制
公开(公告)号：EP3224728A1
公开(公告)日：2017-10-04
申请号：EP15797546.7
申请日：2015-11-09
申请人： Qualcomm Incorporated
发明人： HOWER, Derek, Robert , CAIN, III, Harold, Wade
IPC分类号： G06F12/08 , G06F12/12 , G06F11/34
CPC分类号： G06F12/084 , G06F11/34 , G06F12/0833 , G06F12/0842 , G06F12/0846 , G06F12/12 , G06F12/128 , G06F2212/1016 , G06F2212/1044 , G06F2212/314 , G06F2212/6042 , G06F2212/62
摘要： Providing shared cache memory allocation control in shared cached memory systems is disclosed. In one aspect, a cache controller of a shared cache memory system comprising a plurality of cache lines is provided. The cache controller comprises a cache allocation circuit providing a minimum mapping bitmask for mapping a Quality of Service (QoS) class to a minimum partition of the cache lines, and a maximum mapping bitmask for mapping the QoS class to a maximum partition of the cache lines. The cache allocation circuit receives a memory access request comprising a QoS identifier (QoSID) of the QoS class, and is configured to determine whether the memory access request corresponds to a cache line of the plurality of cache lines. If not, the cache allocation circuit selects, as a target partition, the minimum partition mapped to the QoS class or the maximum partition mapped to the QoS class.
摘要翻译：提供共享高速缓存存储器系统中的共享高速缓存存储器分配控制。在一个方面，提供了包括多个高速缓存行的共享高速缓存存储器系统的高速缓存控制器。高速缓存控制器包括提供用于将服务质量（QoS）类映射到高速缓存线的最小分区的最小映射位掩码的高速缓存分配电路和用于将QoS类映射到高速缓存线的最大分区的最大映射位掩码。缓存分配电路接收包括QoS类的QoS标识符（QoSID）的存储器访问请求，并且被配置为确定存储器访问请求是否对应于多个缓存线中的缓存线。如果否，则高速缓存分配电路选择映射到QoS类的最小分区或映射到QoS类的最大分区作为目标分区。

5. 发明公开

EP3028163A4 A METHOD, APPARATUS AND SYSTEM FOR PERFORMING MANAGEMENT COMPONENT TRANSPORT PROTOCOL (MCTP) COMMUNICATIONS WITH A UNIVERSAL SERIAL BUS (USB) DEVICE 审中-公开
标题翻译： VERFAHREN，VORRICHUNG UND系统ZURDURCHFÜHRUNGZURDURCHFÜHRUNGDERÜBERTRAGUNGDES管理组件 - 传输协议（MCTP）MIT EINER VORRICHTUNG MIT UNIVERSELLEM SERIELLEM总线（USB）
公开(公告)号：EP3028163A4
公开(公告)日：2017-07-12
申请号：EP13890341
申请日：2013-07-31
申请人： INTEL CORP
发明人： SHANBHOGUE VEDVYAS , KUMAR ARVIND
IPC分类号： G06F13/42 , G06F13/40
CPC分类号： G06F12/0811 , G06F12/0808 , G06F12/084 , G06F12/128 , G06F13/4027 , G06F13/4269 , G06F2212/284 , G06F2212/305 , G06F2212/69 , G11C7/1072

6. 发明公开

EP3121703A4 DATA CACHING METHOD, CACHE AND COMPUTER SYSTEM 有权
标题翻译： DATENZWISCHENSPEICHERUNGSVERFAHREN，ZWISCHENSPEICHER UND COMPUTERSYSTEM
公开(公告)号：EP3121703A4
公开(公告)日：2017-05-17
申请号：EP15789250
申请日：2015-05-07
申请人： HUAWEI TECH CO LTD
发明人： WEI WEI , ZHANG LIXIN , XIONG JIN , JIANG DEJUN
IPC分类号： G06F3/06 , G06F12/08
CPC分类号： G06F12/0868 , G06F3/061 , G06F3/0619 , G06F3/0631 , G06F3/065 , G06F3/068 , G06F3/0685 , G06F12/08 , G06F12/122 , G06F12/128 , G06F2212/604
摘要： A data caching method, a cache, and a computer system are provided. In the method, when a miss of an access request occurs and a cache needs to determine a to-be-replaced cache line, not only a historical access frequency of the cache line but also a type of a memory corresponding to the cache line needs to be considered. Therefore, a cache line corresponding to a DRAM type may be preferably replaced, which reduces a caching amount in the cache for data stored in a DRAM. The cache can increase a caching amount for data stored in an NVM, and for an access request for the data stored in the NVM, corresponding data can be found in the cache whenever possible, thereby reducing cases of reading data from the NVM, reducing a delay in reading data from the NVM, and effectively improving access efficiency.
摘要翻译：数据缓存方法，缓存和计算机系统被提供。在该方法中，当发生访问请求的遗漏并且高速缓存需要确定将被更换的高速缓存行时，不仅高速缓存行的历史访问频率而且高速缓存行对应的存储器的类型都需要要考虑。因此，可以优选地替换与DRAM类型相对应的高速缓存行，这降低了存储在DRAM中的数据在高速缓存中的高速缓存量。高速缓存可以增加NVM中存储的数据的高速缓存量，并且对于存储在NVM中的数据的访问请求，只要可能就可以在高速缓存中找到相应的数据，由此减少了从NVM读取数据的情况，减少了延迟从NVM读取数据，并有效提高访问效率。

7. 发明公开

EP3043266A4 STORE MERGE PROCESSING DEVICE, STORE MERGE PROCESSING SYSTEM, STORE MERGE PROCESSING METHOD, AND STORAGE MEDIUM 审中-公开
标题翻译： SPEICHERVEREINIGUNGS-VERARBEITUNGSVORRICHTUNG，SPEICHERVEREINIGUNGS-VERARBEITUNGSSYSTEM UND AUFZEICHNUNGSMEDIUM
公开(公告)号：EP3043266A4
公开(公告)日：2017-04-19
申请号：EP14842063
申请日：2014-09-02
申请人： NEC PLATFORMS LTD
发明人： OSADA TAKASHI
IPC分类号： G06F12/00 , G06F3/06 , G06F12/1036 , G06F12/121 , G06F12/128
CPC分类号： G06F12/121 , G06F3/0611 , G06F3/064 , G06F3/0679 , G06F12/1036 , G06F12/128 , G06F2212/621 , G06F2212/657
摘要： To enable implementation of store merge processing with simple hardware even when there are accesses with different block sizes relating to write data for a storage device. A store merge processing device 40 includes: a storage means that stores a plurality of entries, with regard to a plurality of first write instructions that are a plurality of write instructions issued by an external device issuable of write instructions of different block sizes, have access addresses including upper addresses and lower addresses, of which upper addresses are equal and have equal block sizes for writing data to a storage device, the entries including identification information for identifying a block size, a plurality of pieces of block data, address information indicating an upper address, and storage information indicating a storage state for each piece of the block data in association with one another; and an update means for, when the entries include an entry of which identification information and address information matches those of a second write instruction that has been newly issued by the external device, writing the block data included in the second write instruction in a position specified by the access address in the entry, and updates the storage information regarding the block data.
摘要翻译：即使存在与存储设备的写入数据有关的不同块大小的访问，也能够实现具有简单硬件的存储合并处理。存储合并处理装置40包括：存储装置，其存储多个第一写指令，多个第一写指令是由可发出不同块大小的写指令的外部装置发出的多个写指令，具有访问权包括高地址和下地址的地址，其高地址相等并且具有用于将数据写入存储设备的相等的块大小，该条目包括用于识别块大小的标识信息，多个块数据，表示一个块地址的地址信息指示每个块数据的存储状态相关联的存储信息; 以及更新装置，用于当条目包括标识信息和地址信息的条目与外部设备新发布的第二写入指令的条目相匹配时，将包括在第二写入指令中的块数据写入指定的位置通过条目中的访问地址，并更新关于块数据的存储信息。

8. 发明公开

EP3126985A1 ADAPTIVE CACHE PREFETCHING BASED ON COMPETING DEDICATED PREFETCH POLICIES IN DEDICATED CACHE SETS TO REDUCE CACHE POLLUTION 审中-公开
标题翻译：自适应缓冲器预取基于竞争DEDICATED VORABRUFPOLITIK专用组缓冲溶液组，以减少污染BUFFER
公开(公告)号：EP3126985A1
公开(公告)日：2017-02-08
申请号：EP15719903.5
申请日：2015-04-02
申请人： Qualcomm Incorporated
发明人： CAIN, III, Harold, Wade , PALFRAMAN, David, John
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/0864 , G06F12/0875 , G06F12/128 , G06F2212/283 , G06F2212/602 , G06F2212/6024 , G06F2212/6046 , Y02D10/13
摘要： Adaptive cache prefetching based on competing dedicated prefetch policies in dedicated cache sets to reduce cache pollution is disclosed. In one aspect, an adaptive cache prefetch circuit is provided for prefetching data into a cache. The adaptive cache prefetch circuit is configured to determine which prefetch policy to use as a replacement policy based on competing dedicated prefetch policies applied to dedicated cache sets in the cache. Each dedicated cache set has an associated dedicated prefetch policy used as a replacement policy for the given dedicated cache set. Cache misses for accesses to each of the dedicated cache sets are tracked by the adaptive cache prefetch circuit. The adaptive cache prefetch circuit can be configured to apply a prefetch policy to the other follower (i.e., non-dedicated) cache sets in the cache using the dedicated prefetch policy that incurred fewer cache misses to its respective dedicated cache sets to reduce cache pollution.
摘要翻译：基于在专用高速缓存竞争专用预取策略自适应缓存预取设置，以减少缓存污染是游离缺失盘。在一个方面中，到自适应高速缓存预取电路设置用于预取数据到高速缓存。自适应高速缓存预取电路配置确定性矿预取哪些政策，基于竞争的缓存适用于专用高速缓存组专用预取政策的替代政策来使用。每个专用高速缓存组具有作为给定的专用高速缓存组替换政策相关联的专用预取的政策。对于访问到每个专用高速缓存组的高速缓存未命中是由自适应高速缓存预取电路跟踪。自适应高速缓存预取电路可以被配置以施加预取策略应用到其它从动件（即，非专用的）使用专用的预取策略高速缓存组中高速缓存没有招致更少的高速缓存未命中其respectivement专用高速缓存设置为减少高速缓存污染。

9. 发明公开

EP2867778A4 HIGH-PERFORMANCE CACHE SYSTEM AND METHOD 审中-公开
标题翻译：强大的LATCH系统和方法
公开(公告)号：EP2867778A4
公开(公告)日：2016-12-28
申请号：EP13809284
申请日：2013-06-26
申请人： SHANGHAI XIN HAO MICRO ELECTRONICS CO LTD
发明人： LIN KENNETH CHENGHAO
IPC分类号： G06F12/08 , G06F9/345 , G06F9/38
CPC分类号： G06F12/128 , G06F9/3455 , G06F9/3804 , G06F9/3808 , G06F9/382 , G06F9/383 , G06F9/3832 , G06F12/0862 , G06F12/0875 , G06F2212/452 , Y02D10/13
摘要： A method for facilitating operation of a processor core is provided. The method includes: examining instructions being filled from a second instruction memory to a third instruction memory, extracting instruction information containing at least branch information and generating a stride length of base register corresponding to every data access instruction; creating a plurality of tracks based on the extracted instruction; filling at least one or more instructions that are likely to be executed by the processor core based on one or more tracks from the plurality of tracks from a first instruction memory to the second instruction memory; filling at least one or more instructions based on one or more tracks from the plurality of tracks from the second instruction memory to the third instruction memory; calculating possible data access address of the data access instruction to be executed next time based on the stride length of the base register.

10. 发明授权

EP2622485B1 METHOD AND APPARATUS FOR REDUCING PROCESSOR CACHE POLLUTION CAUSED BY AGGRESSIVE PREFETCHING 有权
标题翻译：方法和设备以最小化的处理器缓存污染激进ADVANCE STORE
公开(公告)号：EP2622485B1
公开(公告)日：2016-10-26
申请号：EP11761810.8
申请日：2011-09-22
申请人： Advanced Micro Devices Inc.
发明人： CONWAY, Patrick
IPC分类号： G06F12/12 , G06F12/08
CPC分类号： G06F12/128 , G06F12/0862 , G06F12/0888 , G06F12/0897 , G06F2212/1021

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