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1. 发明公开

EP1581876A2 MEMORY CONTROLLER AND METHOD FOR WRITING TO A MEMORY 有权转让
标题翻译：以便写入内存的内存管理和方法
公开(公告)号：EP1581876A2
公开(公告)日：2005-10-05
申请号：EP03813945.7
申请日：2003-11-26
申请人： Koninklijke Philips Electronics N.V.
发明人： HOOGERBRUGGE, Jan
IPC分类号： G06F13/16
CPC分类号： G06F13/1631 , Y02D10/14
摘要： The invention provides a controller for a memory having at least one memory cell, that involves a higher cost for writing than for reading. The memory cell is allocated to a first address information and adapted to store memory data. The memory controller of the invention comprises a register. A write controller connected with said register and said memory is adapted to receive a write request comprising said first address information and first write data allocated thereto, ascertain whether said first address information is stored in said register. If yes, the write controller compares said first write data with second write data of an earlier write request in said register allocated to said first address information. If no, it compares said first write data with said memory data allocated to the first address information. The write controller further forwards said first address information and said first write data to said register, respectively, and initiates a write operation of said first or second write data, respectively, from said register to said memory, if the first or second write data, respectively, is different from said memory data. With the memory controller of the invention write power can be saved while providing continuous access to the memory.

2. 发明公开

EP1405174A1 METHOD, APPARATUS AND COMPILER FOR PREDICTING INDIRECT BRANCH TARGET ADDRESSES 审中-公开
标题翻译：方法，装置及编译器为预测间接分支目标地址
公开(公告)号：EP1405174A1
公开(公告)日：2004-04-07
申请号：EP02738525.1
申请日：2002-06-20
申请人： Koninklijke Philips Electronics N.V.
发明人： HOOGERBRUGGE, Jan
IPC分类号： G06F9/32 , G06F9/38
CPC分类号： G06F9/3806 , G06F9/30058 , G06F9/3844
摘要： The present invention relates to a method, processor and compile r for predicting a branch target of a program. A hint operation is provided in the program to hint the branch prediction about upcoming indirect branches. A table of branch targets of indirect branches can be used to improve prediction accuracy of indirect branches. The branch target is determined on the basis of a key information derived from the hint operation.

3. 发明公开

EP1305707A1 DATA PROCESSOR WITH BRANCH TARGET BUFFER 审中-公开
标题翻译：随着结目标缓冲区数据处理器
公开(公告)号：EP1305707A1
公开(公告)日：2003-05-02
申请号：EP01969352.2
申请日：2001-07-06
申请人： Koninklijke Philips Electronics N.V.
发明人： HOOGERBRUGGE, Jan
IPC分类号： G06F9/38 , G06F9/32
CPC分类号： G06F9/324 , G06F9/322 , G06F9/3806
摘要： A data processor comprising contains a branch target memory that stores partial branch target information for instructions. The branch target information is used for advanced determination of the target address of a branch, so that the instruction at the target address can be prefetched. The partial branch target information indicates a position of an expected branch target address in a part of instruction address space defined relative to the current instruction address. Preferably, the relevant part of instruction address space is a page that contains the current instruction address, the partial branch target information providing only the least significant part of the branch target address.

4. 发明公开

EP1236095A1 DATA PROCESSOR WITH MULTI-COMMAND INSTRUCTION WORDS 有权
标题翻译：与MEHERERN数据处理器命令的完整命令字
公开(公告)号：EP1236095A1
公开(公告)日：2002-09-04
申请号：EP01916981.2
申请日：2001-02-12
申请人： Koninklijke Philips Electronics N.V.
发明人： HOOGERBRUGGE, Jan
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/3848 , G06F9/3885
摘要： The data processor that addresses instructions as groups of commands which may contain more than one branch command, such as VLIW instructions that contain several commands for parallel execution. The processor selects an expected taken branch command from the branch commands in a group. The processor also selects a tentative target for the expected taken branch command and tentatively redirects control flow to a further group of commands identified by the tentative target. The processor contains an associative target memory for storing targets of previously executed branch commands. Targets are retrieved with an associative address that identifies a command in the group, the tentative target being selected on the basis of a match between the associative address associated with the tentative target and an indication of the expected taken command.

5. 发明授权

EP1514172B1 SPACECAKE COPROCESSOR COMMUNICATION 有权
标题翻译： SPACECAKE COPROZESSOR KOMMUNIKATION
公开(公告)号：EP1514172B1
公开(公告)日：2006-04-05
申请号：EP03727825.6
申请日：2003-05-21
申请人： Koninklijke Philips Electronics, N.V.
发明人： HOOGERBRUGGE, Jan , STRAVERS, Paul
IPC分类号： G06F5/06
CPC分类号： G06F5/12 , G06F2205/106 , G06F2205/123
摘要： The invention is based on the idea to maintain two counters for an input or output port of a FIFO. A device for writing data elements from a coprocessor into a FIFO memory is provided. Said device is embedded in a multiprocessing environment comprising at least one coprocessor, a FIFO memory and a controller. Said device comprises a first counter for counting the available room in said FIFO memory, and a second counter for counting the number of data elements written into said FIFO memory. Said device further comprises a control means for checking said first counter for available room in said FIFO memory, and for checking said second counter whethera predetermined number N of data elements have been written into said FIFO memory. Said control means decrements the count of said first counter and increments the count of said second counter, after a data element has been written into said FIFO memory. Said device finally comprises an output means for outputting data elements to said FIFO memory. Said control means issues a first message when the count of said second counter has reached said predetermined number N and issues a first call for available room in said FIFO memory to said controller. Said output means forwards said first message and/or said first call to said controller.

6. 发明公开

EP1346280A1 DATA PROCESSING DEVICE WITH A CONFIGURABLE FUNCTIONAL UNIT 审中-公开
标题翻译：有可配置的功能单元中的数据处理装置
公开(公告)号：EP1346280A1
公开(公告)日：2003-09-24
申请号：EP01271578.5
申请日：2001-12-06
申请人： Koninklijke Philips Electronics N.V.
发明人： OLIVEIRA KASTRUP PEREIRA DE, Bernardo , HOOGERBRUGGE, Jan
IPC分类号： G06F9/318 , G06F9/38
CPC分类号： G06F9/3885 , G06F9/3897
摘要： A data processing device has a configurable functional unit for executing an instruction according to a configurable function. The configurable functional unit has a plurality of independent configurable logic blocks for performing programmable logic operations to implement the configurable function. Configurable connection circuits are provided between the configurable logic blocks and both the inputs and the outputs of the configurable functional unit. This allows an optimalization of the distribution of logic functions over the configurable logic blocks.

7. 发明公开

EP0978031A2 A METHOD FOR STRUCTURING A MULTI-INSTRUCTION COMPUTER PROGRAM 审中-公开
标题翻译：方法构建以多命令计算机程序
公开(公告)号：EP0978031A2
公开(公告)日：2000-02-09
申请号：EP99902771.7
申请日：1999-02-22
申请人： Koninklijke Philips Electronics N.V.
发明人： AUGUSTEIJN, Alexander , HOOGERBRUGGE, Jan
IPC分类号： G06F9/30
CPC分类号： G06F8/433
摘要： A method for structuring a multi-instruction computer program as containing a plurality of basic blocks, that each compose from internal instructions and external jumps organized in an internal directed acyclic graph, characterized by within various particular first subsets of successor instructions that each collectively emanate from a respectively associated single predecessor instruction, executing on each successor instruction within the first subset in question a respective guarding, all guardings being mutually exclusive with respect to their respectively associated basic block, with respect to a second subset of joined instructions that converge onto a single join/target instruction, allowing unconditional joining by letting each respective instruction in the second subset being executed under mutually non-overlapping conditions, with respect to a jump instruction specifying all operations that must have been executed previously, and furthermore linking various such basic blocks in a directed acyclic graph which allows parallel execution of any further subset of instructions contained therein and being usable as a single basic block for inclusion in a higher level tree of basic blocks.

8. 发明公开

EP1586039A2 USING A CACHE MISS PATTERN TO ADDRESS A STRIDE PREDICTION TABLE 审中-公开
标题翻译：使用缓存缺失填充图案为解决一个箭步PRÄDIKTIONSTABELLE
公开(公告)号：EP1586039A2
公开(公告)日：2005-10-19
申请号：EP03772449.9
申请日：2003-11-11
申请人： Koninklijke Philips Electronics N.V.
发明人： VAN DE WAERDT, Jan-Willem , HOOGERBRUGGE, Jan
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/6022 , G06F2212/6026
摘要： Data prefetching is used to reduce an average latency of memory references for retrieval of data therefrom. The prefetching process is typically based on anticipation of future processor data references. In example embodiment, there is a method of data retrieval that comprises providing a first memory circuit (610), a stride prediction (611) table (SPT) and a cache memory circuit (612). Instructions for accessing data (613) within the first memory are executed. A cache miss (614) is detected. Only when a cache miss is detected is the SPT accessed and updated (615). A feature of this embodiment includes using a stream buffer as the cache memory circuit. Another feature includes using random access cache memory as the cache memory circuit.

9. 发明公开

EP1520228A2 MULTI-PROCESSOR COMPUTER SYSTEM 审中-公开
标题翻译：多处理器计算机系统
公开(公告)号：EP1520228A2
公开(公告)日：2005-04-06
申请号：EP03740905.9
申请日：2003-06-23
申请人： Koninklijke Philips Electronics N.V.
发明人： HOOGERBRUGGE, Jan
IPC分类号： G06F9/46 , G06F1/32 , G06F9/52 , G06F12/08
CPC分类号： G06F9/5011 , G06F1/3228 , G06F9/5094 , G06F12/0831 , G06F2209/5014 , Y02D10/22
摘要： The present invention relates to a multi-processor computer system comprising at least two processors for parallel execution of processes, at least two cache memory units, each being associated with and connected to a separate processor, a connection bus connecting said processors and said cache memory units, and a process list unit connected to said connection line for storing a process list of processes to be available for execution by said processors. In order to enable power saving if no processes for execution are available while guaranteeing a fast wake-up procedure if such processes are available it is proposed according to the present invention that said processors are adapted for loading a global wake-up variable signalling process additions of processes to said process list into their associated cache memory unit, for switching into a low-power mode if said process list contains no process for execution by said processors and for switching into a normal-power mode if said wake-up variable signals an addition of a process to said process list. Thus, according to the present invention the cache coherence protocol is used for communicating and signalling the availability of processes for execution.

10. 发明公开

EP1449061A1 EFFICIENT FIFO COMMUNICATION USING SEMAPHORES 审中-公开
标题翻译：旗语高效FIFO通信
公开(公告)号：EP1449061A1
公开(公告)日：2004-08-25
申请号：EP02779804.0
申请日：2002-10-25
申请人： Koninklijke Philips Electronics N.V.
发明人： HOOGERBRUGGE, Jan , STRAVERS, Paul
IPC分类号： G06F5/06
CPC分类号： G06F5/06 , G06F2205/108
摘要： The invention relates to a method and a device for reading/writing data elements from/into a shared FIFO buffer, wherein the signalling that a data element or a storage space for a data element is available in a FIFO buffer, i.e. performing a V-operation, is not performed atomically as soon as a data element or a storage space for a data element becomes available in said FIFO buffer but to wait until L data elements or L storage spaces for L data elements have become available in said FIFO buffer before performing one signalling of the availability of the L data elements or L storage spaces for L data elements. In a sense, the signalling of the availability of the data elements or the storage spaces for data elements, i.e. performing a V-operation, is buffered until a certain amount of V-operations is collected before outputting of the signalling of the availability.

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