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1. 发明授权

EP0806004B1 DATA TRANSMISSION SYSTEM WITH A DATA BUFFER HAVING A TREE SHAPED STRUCTURE OF MULTIPLEXERS 失效
标题翻译：与数据缓冲器具有含多路复用器的树结构数据传输系统
公开(公告)号：EP0806004B1
公开(公告)日：2002-04-10
申请号：EP96902030.4
申请日：1996-01-19
申请人： TELEFONAKTIEBOLAGET LM ERICSSON
发明人： ARVIDSSON, Carl-Erik , LINDBLOM, Martin
IPC分类号： G06F5/06
CPC分类号： G06F5/10 , G06F2205/106 , G11C8/00
摘要： A data buffer includes a number of data storing elements (202), a tree shaped structure (218) of multiplexer elements (216), a write address generator (21), and a read address generator (214). The data storing elements have data inputs connected in parallel to an input for a data stream from a sending clock domain. The tree shaped structure of multiplexer elements is arranged for receiving data from the data storing elements, and emits on an output a data stream to a receiving clock domain. The write address generator generates, controlled by a write clock signal (C1) from the clock of the sending clock domain, write addresses for entering data from the sending clock domain into the data storing elements, one at a time. The read address generator generates, controlled by a read clock signal (c2) from the clock generator of the receiving clock domain, read addresses for reading out data from the data storing elements in the same order as they were read in.

2. 发明公开

EP0555382A1 ADDRESS GENERATOR FOR CIRCULAR BUFFER 失效
标题翻译：地址发生器的环形缓冲区。
公开(公告)号：EP0555382A1
公开(公告)日：1993-08-18
申请号：EP92900366.0
申请日：1991-11-01
申请人： Analog Devices, Inc.
发明人： GARDE, Douglas
IPC分类号： G06F5 , G06F9 , G06F12 , G06F7
CPC分类号： G06F5/10 , G06F7/72 , G06F9/3552 , G06F2205/106
摘要： L'invention comprend un générateur d'adresses construit par matériel et destiné à une mémoire tampon circulaire pouvant présenter toute dimension et se situer à toute position dans la mémoire. Le générateur d'adresses calcule à la fois une valeur absolue et une valeur bouclée et en sélectionne une selon que la valeur bouclée tombe à l'intérieur des limites de la mémoire tampon.

3. 发明公开

EP1514172A2 SPACECAKE COPROCESSOR COMMUNICATION 有权
标题翻译： Spacecake协处理器通信
公开(公告)号：EP1514172A2
公开(公告)日：2005-03-16
申请号：EP03727825.6
申请日：2003-05-21
申请人： Koninklijke Philips Electronics N.V.
发明人： HOOGERBRUGGE, Jan , STRAVERS, Paul
IPC分类号： G06F5/06
CPC分类号： G06F5/12 , G06F2205/106 , G06F2205/123
摘要： The invention is based on the idea to maintain two counters for an input or output port of a FIFO. A device for writing data elements from a coprocessor into a FIFO memory is provided. Said device is embedded in a multiprocessing environment comprising at least one coprocessor, a FIFO memory and a controller. Said device comprises a first counter for counting the available room in said FIFO memory, and a second counter for counting the number of data elements written into said FIFO memory. Said device further comprises a control means for checking said first counter for available room in said FIFO memory, and for checking said second counter whethera predetermined number N of data elements have been written into said FIFO memory. Said control means decrements the count of said first counter and increments the count of said second counter, after a data element has been written into said FIFO memory. Said device finally comprises an output means for outputting data elements to said FIFO memory. Said control means issues a first message when the count of said second counter has reached said predetermined number N and issues a first call for available room in said FIFO memory to said controller. Said output means forwards said first message and/or said first call to said controller.

4. 发明公开

EP1293888A2 Methods and circuitry for implementing first-in first-out structure 有权
标题翻译：的方法和电路，用于执行一个FIFO结构
公开(公告)号：EP1293888A2
公开(公告)日：2003-03-19
申请号：EP02253454.9
申请日：2002-05-15
申请人： Broadcom Corporation
发明人： Momtaz, Afshin D. , Wang, Xin , Cao, Jun , Hairapetian, Armond , Chung, David
IPC分类号： G06F5/06
CPC分类号： G06F5/10 , G06F2205/106
摘要： Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.

5. 发明公开

EP0635782A1 Method and system for address access 失效
标题翻译： Verfahren und System zum Addressenzugriff。
公开(公告)号：EP0635782A1
公开(公告)日：1995-01-25
申请号：EP94305259.7
申请日：1994-07-18
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： Saito, Yoshiko , Uesugi, Mitsuru , Asano, Nobuo , Ishikawa, Toshihiro
IPC分类号： G06F7/50 , G06F5/06 , G06F12/02 , G06F9/355
CPC分类号： G06F7/5055 , G06F5/10 , G06F7/505 , G06F9/3552 , G06F12/0223 , G06F2205/106 , G06F2207/382
摘要： Different multi-bit addresses extending from a stating address to an ending address are sequentially assigned to respective memory segments in a designated area of a memory which stores data. A fixed-value register stores fixed-value data representative of a predetermined unit address increment, and outputs the fixed-value data. A multi-bit adder adds output data from an address pointer register and the output fixed-value data from the fixed-value register, and outputs data representative of a result of the addition. The address pointer register stores starting-address data representative of the starting address and outputs the starting-address data to the memory and the adder during an initial stage. The address pointer register stores the output data from the adder and outputs the stored data to the memory and the adder during a stage following the initial stage. The adder includes adding circuit elements corresponding to respective bits. In the adder, propagation of a carry from a given one of the adding circuit elements to a subsequent one of the adding circuit elements is inhibited so that an address represented by the output data from the adder returns from the ending address to the starting address when an address represented by the output data from the address pointer register reaches the ending address.
摘要翻译：从指定地址延伸到结束地址的不同的多位地址被依次分配给存储数据的存储器的指定区域中的相应存储器段。固定值寄存器存储表示预定单位地址增量的固定值数据，并输出固定值数据。多位加法器从地址指针寄存器和固定值寄存器的输出固定值数据中加入输出数据，并输出表示相加结果的数据。地址指针寄存器存储表示起始地址的起始地址数据，并且在初始阶段将起始地址数据输出到存储器和加法器。地址指针寄存器存储来自加法器的输出数据，并且在初始阶段之后的阶段将存储的数据输出到存储器和加法器。加法器包括加上与各个位对应的电路元件。在加法器中，禁止从相加电路元件中的给定一个加法电路元件的进位到后一个加法电路元件的传播，使得来自加法器的输出数据所表示的地址从结束地址返回到起始地址，当由地址指针寄存器的输出数据表示的地址到达结束地址。

6. 发明公开

EP1710702A3 Method and apparatus for queue depth detection in a memory system 审中-公开
标题翻译：方法和装置用于在存储系统中计算的队列长度
公开(公告)号：EP1710702A3
公开(公告)日：2008-01-16
申请号：EP06300293.5
申请日：2006-03-28
申请人： Alcatel Lucent
发明人： JONES, Thomas Carleton
IPC分类号： G06F5/14
CPC分类号： G06F5/14 , G06F2205/106 , G06F2205/126
摘要： A method and apparatus for detecting a queue depth of a memory queue in a memory system is described. The method includes estimating a start position of the queue by examining a portion of a queue start identifier of the memory queue, estimating an end position of the queue by examining a portion of a queue end identifier of the memory queue, and utilizing the start position and the end position to estimate the queue depth of the memory queue. The apparatus applies the method. One embodiment of the method and apparatus may be suitable for implementation on look-up tables of field general programmable gate arrays.

7. 发明公开

EP1293888A3 Methods and circuitry for implementing first-in first-out structure 有权
标题翻译： Verfahren und Schaltung zurAusführungeiner FIFO Struktur
公开(公告)号：EP1293888A3
公开(公告)日：2006-08-23
申请号：EP02253454.9
申请日：2002-05-15
申请人： Broadcom Corporation
发明人： Momtaz, Afshin D. , Wang, Xin , Cao, Jun , Hairapetian, Armond , Chung, David
IPC分类号： G06F5/06
CPC分类号： G06F5/10 , G06F2205/106
摘要： Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.
摘要翻译：用于实现高速先进先出（FIFO）结构的方法和电路。在一个实施例中，公开了允许一个时钟（例如写时钟）的频率与另一（读取）时钟的频率不同的（例如，一半）的FIFO。在另一个实施例中，呈现可以异步地设置和/或复位的FIFO。公开了其他实施例，其中有效地监视读取和写入指针，以确保正确的时序关系，以检测时钟损耗以及检测其他异常FIFO条件。

8. 发明公开

EP1410509A2 NON-POWER-OF-TWO GRAY-CODE COUNTER SYSTEM HAVING BINARY INCREMENTER WITH COUNTS DISTRIBUTED WITH BILATERAL SYMMETRY 有权
标题翻译：并非在两个POTENZ BASED格雷码计数器与二进制INCREMENTIERER两制双面对称分布号码
公开(公告)号：EP1410509A2
公开(公告)日：2004-04-21
申请号：EP01978284.6
申请日：2001-08-17
申请人： Koninklijke Philips Electronics N.V.
发明人： PONTIUS, Timothy, A.
IPC分类号： H03K23/00
CPC分类号： G06F5/14 , G06F2205/102 , G06F2205/106 , H03K23/005
摘要： A gray-code counter system (AP1) for a RAM-based FIFO comprises a read pointer (10), a write pointer (20), and a detector (30). The read pointer includes a gray-code decoder (11), a binary incrementer (12), a gray-code encoder (13), and a register (14) that holds the pointer count). The binary incrementer increments by 1 except when the input is 0110 (decimal 6) or 1110 (decimal 14); in these cases, it increments by 3. The result is a 4-bit modulo-12 gray-code sequence with the twelve allowed gray-code values being distributed among the sixteen possible 4-bit gray code values with translational and reflective bilateral symmetry. The write pointer is similar. Because of the translational symmetry, detectors that work with counters with modulo numbers that are power of two work with the corresponding non-power-of-two counter to provide 'full' and 'empty' indications. When read and write counts differ at the two most-significant bit positions but are equal at the remaining bit positions, the detector provides a 'full' indication for a 6-count FIFO. The gray-code counter design is scaleable to any non-power-of-two modulo number divisible by four.

9. 发明公开

EP0806004A1 DATA TRANSMISSION SYSTEM 失效
标题翻译：数据传输系统
公开(公告)号：EP0806004A1
公开(公告)日：1997-11-12
申请号：EP96902030.0
申请日：1996-01-19
申请人： TELEFONAKTIEBOLAGET LM ERICSSON
发明人： ARVIDSSON, Carl-Erik , LINDBLOM, Martin
IPC分类号： G06F5 , G11C8
CPC分类号： G06F5/10 , G06F2205/106 , G11C8/00
摘要： A data buffer includes a number of data storing elements (202), a tree shaped structure (218) of multiplexer elements (216), a write address generator (21), and a read address generator (214). The data storing elements have data inputs connected in parallel to an input for a data stream from a sending clock domain. The tree shaped structure of multiplexer elements is arranged for receiving data from the data storing elements, and emits on an output a data stream to a receiving clock domain. The write address generator generates, controlled by a write clock signal (C1) from the clock of the sending clock domain, write addresses for entering data from the sending clock domain into the data storing elements, one at a time. The read address generator generates, controlled by a read clock signal (c2) from the clock generator of the receiving clock domain, read addresses for reading out data from the data storing elements in the same order as they were read in.

10. 发明授权

EP1293888B1 Methods and circuitry for implementing a first-in first-out structure 有权
标题翻译：的方法和电路，用于执行一个FIFO结构
公开(公告)号：EP1293888B1
公开(公告)日：2010-03-03
申请号：EP02253454.9
申请日：2002-05-15
申请人： Broadcom Corporation
发明人： Momtaz, Afshin D. , Wang, Xin , Cao, Jun , Hairapetian, Armond , Chung, David
IPC分类号： G06F5/06
CPC分类号： G06F5/10 , G06F2205/106

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