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1. 发明公开

EP2870529A2 COMPUTER PROCESSOR AND SYSTEM WITHOUT AN ARITHMETIC AND LOGIC UNIT 审中-公开
标题翻译：计算机处理器和系统，而不算术和逻辑单元
公开(公告)号：EP2870529A2
公开(公告)日：2015-05-13
申请号：EP13765470.3
申请日：2013-07-06
申请人： Koninklijke Philips N.V.
发明人： DENG, Mina , GORISSEN, Paulus Mathias Hubertus Mechtildis Antonius , TOLHUIZEN, Ludovicus Marinus Gerardus Maria , NIESSEN, Arnoldus Jeroen
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38 , G06F1/03
CPC分类号： G06F9/30145 , G06F1/03 , G06F9/30 , G06F9/30007 , G06F9/3001 , G06F9/30029 , G06F9/30061 , G06F9/324 , G06F9/3867
摘要： A computer system comprising a processor and a memory, the processor comprising an instruction cycle circuit configured to repeatedly obtain a next instruction of a computer program, an instruction decoder configured to decode and execute the instruction obtained by the instruction cycle circuit, the computer system supporting multiple arithmetic and/or logic operations under control of one or more of the instructions, wherein the memory stores multiple tables, each specific one of the multiple arithmetic and/or logic operations being supported by a specific table stored in the memory, each specific table comprising the result of the specific arithmetic operations for a range of inputs.

2. 发明公开

EP1934770A2 IMPROVED MULTI-THREADING PROCESSORS, INTEGRATED CIRCUIT DEVICES, SYSTEMS, AND PROCESSES OF OPERATION AND MANUFACTURE 审中-公开
标题翻译：改进的多线程处理器，集成电路，用于使用和生产系统和流程
公开(公告)号：EP1934770A2
公开(公告)日：2008-06-25
申请号：EP06802632.7
申请日：2006-08-30
申请人： Texas Instruments Incorporated
发明人： TRAN, Thang
IPC分类号： G06F15/00
CPC分类号： G06F9/3851 , G06F1/324 , G06F1/3296 , G06F9/30181 , G06F9/30189 , G06F9/324 , G06F9/3822 , G06F9/3836 , G06F9/3838 , G06F9/3857 , G06F9/3861 , G06F9/3885
摘要： A multi-threaded microprocessor (1105) for processing instructions in threads. The microprocessor (1105) includes first and second decode pipelines (1730.0, 1730.1), first and second execute pipelines (1740, 1750), and coupling circuitry (1916) operable in a first mode to couple first and second threads from the first and second decode pipelines (1730.0, 1730.1) to the first and second execute pipelines (1740, 1750) respectively, and the coupling circuitry (1916) operable in a second mode to couple the first thread to both the first and second execute pipelines (1740, 1750). Various processes of manufacture, articles of manufacture, processes and methods of operation, circuits, devices, and systems are disclosed.

3. 发明公开

EP1258802A3 Instruction address generation 有权
标题翻译：指令地址生成
公开(公告)号：EP1258802A3
公开(公告)日：2007-09-05
申请号：EP02253489.5
申请日：2002-05-17
申请人： Broadcom Corporation
发明人： Kruckemyer, David A. , Murray, Daniel C.
IPC分类号： G06F9/32
CPC分类号： G06F9/324 , G06F9/30054 , G06F9/3806
摘要： A link address/sequential address generation circuit is provided for generating a link/sequential address. The circuit receives the most significant bits of at least two addresses: a first address of a first set of bytes including a branch instruction and a second address of a second set of bytes contiguous to the first set. The least significant bits of the branch PC (those bits not included in the most significant bits of the addresses received by the circuit) are used to generate the least significant bits of the link/sequential address and to select one of the first address and the second address to supply the most significant bits.

5. 发明公开

EP1305707A1 DATA PROCESSOR WITH BRANCH TARGET BUFFER 审中-公开
标题翻译：随着结目标缓冲区数据处理器
公开(公告)号：EP1305707A1
公开(公告)日：2003-05-02
申请号：EP01969352.2
申请日：2001-07-06
申请人： Koninklijke Philips Electronics N.V.
发明人： HOOGERBRUGGE, Jan
IPC分类号： G06F9/38 , G06F9/32
CPC分类号： G06F9/324 , G06F9/322 , G06F9/3806
摘要： A data processor comprising contains a branch target memory that stores partial branch target information for instructions. The branch target information is used for advanced determination of the target address of a branch, so that the instruction at the target address can be prefetched. The partial branch target information indicates a position of an expected branch target address in a part of instruction address space defined relative to the current instruction address. Preferably, the relevant part of instruction address space is a page that contains the current instruction address, the partial branch target information providing only the least significant part of the branch target address.

6. 发明公开

EP0953898A3 A processor for executing Instructions from memory according to a program counter, and a compiler, an assembler, a linker and a debugger for such a processor 审中-公开
标题翻译：处理器用于通过一个程序计数器和编译器，汇编程序，程序和调试器连接器，用于这样的处理器从所述存储器执行指令
公开(公告)号：EP0953898A3
公开(公告)日：2003-03-26
申请号：EP99303231.7
申请日：1999-04-26
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： Takayama, Shuichi , Ogawa, Hajime , Kawaguchi, Kenichi , Higaki, Nobuo, Shining-Sato 2H , Odani, Kensuke , Tanaka, Tetsuya , Miyaji, Shinya , Heishi, Taketo
IPC分类号： G06F9/32 , G06F9/30 , G06F9/45 , G06F11/00 , G06F9/38
CPC分类号： G06F9/3802 , G06F9/30149 , G06F9/30152 , G06F9/30167 , G06F9/321 , G06F9/322 , G06F9/324 , G06F9/3822 , G06F9/3853
摘要： The processor executes instructions in units unrelated to the units in which instructions are read. The upper part of a program counter indicates the storage position of a processing packet in memory; the lower part indicates the position in the processing packet of an instruction to be executed. Separate adders are used for updating the upper and lower parts of the program counter. Compiler, linker, assembler and optimizing apparatus generate the instruction sequence. A debbugger converts instruction bytes into processing packets.

7. 发明授权

EP1095330B1 REGISTER RENAMING IN WHICH MOVES ARE ACCOMPLISHED BY SWAPPING RENAME TAGS 有权
标题翻译： REGISTER WHERE RENAME传输指令BY RENAME标志标牌待实现
公开(公告)号：EP1095330B1
公开(公告)日：2002-12-11
申请号：EP99902346.8
申请日：1999-01-18
申请人： ADVANCED MICRO DEVICES INC.
发明人： WITT, David, B.
IPC分类号： G06F9/315
CPC分类号： G06F9/3842 , G06F9/30032 , G06F9/30054 , G06F9/30069 , G06F9/30152 , G06F9/322 , G06F9/324 , G06F9/3806 , G06F9/3816 , G06F9/382 , G06F9/383 , G06F9/384
摘要： An apparatus for accelerating move operations includes a lookahead unit which detects move instructions prior to the execution of the move instructions (e.g. upon selection of the move operations for dispatch within a processor). Upon detecting a move instruction, the lookahead unit signals a register rename unit, which reassigns the rename register associated with the source register to the destination register. In one particular embodiment, the lookahead unit attempts to accelerate moves from a base pointer register to a stack pointer register (and vice versa). An embodiment of the lookahead unit generates lookahead values for the stack pointer register by maintaining cumulative effects of the increments and decrements of previously dispatched instructions. The cumulative effects of the increments and decrements prior to a particular instruction may be added to a previously generated value of the stack pointer register to generate a lookahead value for that particular instruction. For such an embodiment, reassigning the rename register as described above may thereby provide a valid value for the stack pointer register, and hence may allow for the generation of lookahead stack pointer values for instruction subsequent to the move instruction to proceed prior to execution of the move instruction. The present embodiment of the register rename unit may also assign the destination rename register selected for the move instruction to the source register of the move instruction (i.e. the rename tags for the source and destination are 'swapped').

8. 发明公开

EP1122638A3 Branch instruction execution device 失效
标题翻译：设备的分支指令的执行，
公开(公告)号：EP1122638A3
公开(公告)日：2002-01-23
申请号：EP01110865.1
申请日：1992-06-22
申请人： Hitachi, Ltd. , Hitachi ULSI Systems Co.,Ltd.
发明人： Fukada, Kaoru Semiconductor & I.Circuits , Yamazaki, Takanaga Semiconductor & I.Circuits , Akao, Yasushi Hitachi, Ltd., Intel. Prop. Group , Baba, Shiro Hitachi, Ltd., Intel. Prop. Group , Kihara, Toshimasa Semiconductor & I.Circuits , Kurakazu, Keiichi Semiconductor & I.Circuits , Tawara, Yasuhiro Semiconductor & I.Circuits , Kashiwagi, Yugo Semiconductor & I.Circuits , Fujita, Shuya Semiconductor & I.Circuits , Ishida, Katsuhiko Semiconductor & I.Circuits , Chaki, Hideaki Semiconductor & I.Circuits , Sugawara, Tadahiko Hitachi,Ltd. Intel. Prop.Group , Kainaga, Masahiro Semiconductor & I.Circuits , Noguchi, Koki Semiconductor & I.Circuits , Kawasaki, Shumpei Semiconductor & I.Circuits , Sakakibara, Eiji Hitachi Ltd., Intel. Prop.Group , Tsukamoto, Takashi Hitachi Ulsi Systems Co, , Masumura, Shigeki Hitachi Ulsi Systems Co, , Sawa, Noriko Hitachi Ltd., Intel. Prop. Group , Asano, Yoichi Hitachi Ltd., Intel. Prop. Group , Watabe, Mitsuro Hitachi Ltd., Intel. Prop. Group
IPC分类号： G06F9/32 , G06F9/34
CPC分类号： G06F7/535 , G06F9/30 , G06F9/3001 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30163 , G06F9/30167 , G06F9/30181 , G06F9/30189 , G06F9/322 , G06F9/324 , G06F9/3557 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3867 , G06F2207/5352
摘要： A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and low system cost, while enjoying the advantage of simplification of the instruction de-coding as in the RISC machine having a fixed length instruction format of the prior art, by adopting an instruction format of a fixed length of 2 n bits which is smaller than the length of the maximum data word fed to instruction execution means. The control of the coded division is executed by noting the code bits.

9. 发明授权

EP0729605B1 PROCESSING SYSTEM WITH WORD-ALIGNED BRANCH TARGET 失效
标题翻译：使用Word对准JUNCTION目标处理系统
公开(公告)号：EP0729605B1
公开(公告)日：2001-12-05
申请号：EP95927064.6
申请日：1995-08-21
申请人： Koninklijke Philips Electronics N.V.
发明人： MIZRAHI-SHALOM, Ori , KO, Kung-Ling
IPC分类号： G06F9/32 , G06F9/30 , G06F9/38 , G06F9/42
CPC分类号： G06F9/324 , G06F9/30149 , G06F9/321 , G06F9/322 , G06F9/3804 , G06F9/3806 , G06F9/3816
摘要： A microcontroller or processor architecture that performs word aligned multibyte fetches but allows byte aligned instructions. Jump target addresses are word aligned, resulting in a word aligned fetch of the jump-to instruction. An assembler or compiler loads code into an instruction memory with branch instruction target addresses aligned on word boundaries. Returns from interrupts load the program counter with the complete return address which is byte aligned.

10. 发明公开

EP1122638A2 Branch instruction execution device 失效
标题翻译：装置和计算机程序产品，用于分支指令的执行，
公开(公告)号：EP1122638A2
公开(公告)日：2001-08-08
申请号：EP01110865.1
申请日：1992-06-22
申请人： Hitachi, Ltd. , Hitachi ULSI Systems Co.,Ltd.
发明人： Fukada, Kaoru Semiconductor & I.Circuits , Yamazaki, Takanaga Semiconductor & I.Circuits , Akao, Yasushi Semiconductor & I.Circuits , Baba, Shiro Semiconductor & I.Circuits , Kihara, Toshimasa Semiconductor & I.Circuits , Kurakazu, Keiichi Semiconductor & I.Circuits , Tawara, Yasuhiro Semiconductor & I.Circuits , Kashiwagi, Yugo Semiconductor & I.Circuits , Fujita, Shuya Semiconductor & I.Circuits , Ishida, Katsuhiko Semiconductor & I.Circuits , Chaki, Hideaki Semiconductor & I.Circuits , Sugawara, Tadahiko Semiconductor & I.Circuits , Kainaga, Masahiro Semiconductor & I.Circuits , Noguchi, Koki Semiconductor & I.Circuits , Kawasaki, Shumpei Semiconductor & I.Circuits , Sakakibara, Eiji Semiconductor & I.Circuits , Tuskamoto, Takashi Semiconductor & I.Circuits , Masumura, Shigeki Semiconductor & I.Circuits , Sawa, Noriko Semiconductor & I.Circuits , Asano, Yoichi Semiconductor & I.Circuits , Watabe, Mitsuru Semiconductor & I.Circuits
IPC分类号： G06F9/32 , G06F9/34
CPC分类号： G06F7/535 , G06F9/30 , G06F9/3001 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30163 , G06F9/30167 , G06F9/30181 , G06F9/30189 , G06F9/322 , G06F9/324 , G06F9/3557 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3867 , G06F2207/5352
摘要： A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and low system cost, while enjoying the advantage of simplification of the instruction de-coding as in the RISC machine having a fixed length instruction format of the prior art, by adopting an instruction format of a fixed length of 2 n bits which is smaller than the length of the maximum data word fed to instruction execution means. The control of the coded division is executed by noting the code bits.

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